DE102012212611A1 - Halbleiterpackung und Verfahren zur Herstellung derselben - Google Patents

Halbleiterpackung und Verfahren zur Herstellung derselben Download PDF

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Publication number
DE102012212611A1
DE102012212611A1 DE102012212611A DE102012212611A DE102012212611A1 DE 102012212611 A1 DE102012212611 A1 DE 102012212611A1 DE 102012212611 A DE102012212611 A DE 102012212611A DE 102012212611 A DE102012212611 A DE 102012212611A DE 102012212611 A1 DE102012212611 A1 DE 102012212611A1
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DE
Germany
Prior art keywords
insulating layer
connection terminal
substrate
chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE102012212611A
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German (de)
English (en)
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DE102012212611A8 (de
Inventor
YoungLyong KIM
Taehoon Kim
ChulYong JANG
Jongho Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020120029739A external-priority patent/KR101936788B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102012212611A1 publication Critical patent/DE102012212611A1/de
Publication of DE102012212611A8 publication Critical patent/DE102012212611A8/de
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/24—Configurations of stacked chips at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE102012212611A 2011-07-18 2012-07-18 Halbleiterpackung und Verfahren zur Herstellung derselben Withdrawn DE102012212611A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2011-0071016 2011-07-18
KR20110071016 2011-07-18
KR1020120029739A KR101936788B1 (ko) 2011-07-18 2012-03-23 반도체 패키지 및 그 제조 방법
KR10-2012-0029739 2012-03-23

Publications (2)

Publication Number Publication Date
DE102012212611A1 true DE102012212611A1 (de) 2013-03-07
DE102012212611A8 DE102012212611A8 (de) 2013-05-08

Family

ID=47534598

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102012212611A Withdrawn DE102012212611A1 (de) 2011-07-18 2012-07-18 Halbleiterpackung und Verfahren zur Herstellung derselben

Country Status (4)

Country Link
US (2) US8970046B2 (https=)
JP (1) JP2013026625A (https=)
CN (1) CN102891136B (https=)
DE (1) DE102012212611A1 (https=)

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JP6560496B2 (ja) * 2015-01-26 2019-08-14 株式会社ジェイデバイス 半導体装置
US10486548B2 (en) * 2016-01-13 2019-11-26 Ford Global Technologies, Llc Power inverter for a vehicle
US9875993B2 (en) * 2016-01-14 2018-01-23 Micron Technology, Inc. Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture
KR102556327B1 (ko) * 2016-04-20 2023-07-18 삼성전자주식회사 패키지 모듈 기판 및 반도체 모듈
US20200066701A1 (en) * 2016-09-28 2020-02-27 Intel Corporation Stacked chip package having substrate interposer and wirebonds
KR102337647B1 (ko) 2017-05-17 2021-12-08 삼성전자주식회사 반도체 패키지 및 그 제조 방법
KR102432379B1 (ko) * 2017-10-16 2022-08-12 삼성전자주식회사 반도체 소자
US10879225B2 (en) * 2018-10-24 2020-12-29 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing semiconductor package
US11024604B2 (en) * 2019-08-10 2021-06-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
US11171109B2 (en) * 2019-09-23 2021-11-09 Micron Technology, Inc. Techniques for forming semiconductor device packages and related packages, intermediate products, and methods
CN113964102A (zh) * 2019-11-29 2022-01-21 长江存储科技有限责任公司 芯片封装结构及其制造方法
US11373956B2 (en) 2020-01-14 2022-06-28 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
DE112021002956T5 (de) * 2020-05-26 2023-03-09 Rohm Co., Ltd. Halbleiterbauteil und verfahren zum herstellen eines halbleiterbauteils
US11647633B2 (en) 2020-07-13 2023-05-09 Micron Technology, Inc. Methods used in forming integrated circuitry comprising a stack comprising vertically-alternating first tiers and second tiers with the stack comprising a cavity therein that comprises a stair-step structure
US11942430B2 (en) * 2021-07-12 2024-03-26 Micron Technology, Inc. Stacked die modules for semiconductor device assemblies and methods of manufacturing stacked die modules
US12500148B2 (en) 2021-07-30 2025-12-16 Stmicroelectronics S.R.L. Method of coupling semiconductor dice, tool for use therein and corresponding semiconductor device
US12525512B2 (en) * 2021-07-30 2026-01-13 Stmicroelectronics S.R.L. Method of coupling semiconductor dice and corresponding semiconductor device
CN114093822B (zh) * 2021-11-03 2025-10-31 长江存储科技有限责任公司 半导体封装结构及制备方法、待封装芯片的制备方法
US20230260949A1 (en) * 2022-02-16 2023-08-17 Western Digital Technologies, Inc. Semiconductor Device with Protective Layer
US12374647B2 (en) * 2022-05-12 2025-07-29 Renesas Electronics Corporation Semiconductor device including chip-to-chip bonding
US12374620B2 (en) * 2022-06-01 2025-07-29 Micron Technology, Inc. Memory circuitry and method used in forming memory circuitry
CN115642142A (zh) * 2022-10-19 2023-01-24 深圳市汇顶科技股份有限公司 芯片堆叠封装结构及封装方法
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Also Published As

Publication number Publication date
US20150155199A1 (en) 2015-06-04
DE102012212611A8 (de) 2013-05-08
US20130020720A1 (en) 2013-01-24
US8970046B2 (en) 2015-03-03
US9281235B2 (en) 2016-03-08
JP2013026625A (ja) 2013-02-04
CN102891136B (zh) 2017-06-23
CN102891136A (zh) 2013-01-23

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