TWI514486B - 致能無凸塊增層式(bbul)封裝體上之封裝體疊加(pop)墊表面修整層之技術 - Google Patents
致能無凸塊增層式(bbul)封裝體上之封裝體疊加(pop)墊表面修整層之技術 Download PDFInfo
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- TWI514486B TWI514486B TW101145664A TW101145664A TWI514486B TW I514486 B TWI514486 B TW I514486B TW 101145664 A TW101145664 A TW 101145664A TW 101145664 A TW101145664 A TW 101145664A TW I514486 B TWI514486 B TW I514486B
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
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- 229910052802 copper Inorganic materials 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229920000139 polyethylene terephthalate Polymers 0.000 claims description 4
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- 230000000996 additive effect Effects 0.000 claims description 3
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- 238000010329 laser etching Methods 0.000 claims description 2
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 23
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 20
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- 239000012790 adhesive layer Substances 0.000 description 7
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- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 6
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- HJBYDWKNARZTMJ-UHFFFAOYSA-N 1,2,3,4-tetrachloro-5-(2,3,5,6-tetrachlorophenyl)benzene Chemical compound ClC1=CC(Cl)=C(Cl)C(C=2C(=C(Cl)C(Cl)=C(Cl)C=2)Cl)=C1Cl HJBYDWKNARZTMJ-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
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- H05K3/341—Surface mounted components
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Description
本發明係大致有關於一種積體電路封裝體。更詳而言之,本發明係有關於一種無凸塊增層式(BBUL)積體電路封裝體。
在一倒裝晶片封裝體中,來自一積體電路晶粒之互連信號透過多數焊料凸塊(例如,C4凸塊)與一封裝體基材連接。由於積體電路變得更複雜,故需要越來越多之互連信號,且因此,在一封裝體中之焊料凸塊數目亦增加。隨著製造程序發展至較小之幾何形狀,焊料凸塊之密度大幅增加,這會嚴重地減少在該封裝體中留下用以路由數目不斷增加互連信號的空間量。因此,該等焊料凸塊之放置呈指數地變得非常困難。
對一倒裝晶片封裝體之另一種封裝技術是一無凸塊增層式(BBUL)封裝體。與一倒裝晶片封裝體不同,該
BBUL封裝體不使用焊料凸塊來互連由該晶粒至該封裝體基材之信號。相反地,該BBUL封裝體具有多數直接形成在該晶粒上之增層。多數互連層係埋設在該等增層中作為該增層程序之一部份。由於不需要焊料凸塊,一BBUL封裝體容許路由密度增加以配合互連信號數目之增加。
該BBUL封裝體之另一優點是封裝體疊加(PoP)墊可形成在該封裝體之頂側上作為該增層程序之一部份。該PoP墊容許例如記憶體裝置之其他積體電路裝置及如去耦電容器之其他電組件附接在該BBUL封裝體之頂側。這使這些組件之放置更靠近該晶粒以改善該積體電路之效能。一種PoP墊表面修整層是一藉一電解電鍍程序形成之鎳-金(Ni-Au)表面修整層。該Ni-Au表面修整層係藉由電解電鍍一Au層在一銅(Cu)之蝕刻層,且接著電解電鍍一Ni層在該Au層上而形成。因為這表面修整層係藉一電解電鍍程序形成,故一製造者必須具有電解表面修整層設備以製造該BBUL封裝體。
依據本發明之一實施例,係特地提出一種製造一積體電路(IC)封裝體之方法,該方法包含:提供一封裝體核心,且多數封裝體疊加(PoP)墊位置形成在該封裝體核心上,其中該等多數PoP墊位置係以一導電材料之蝕刻層電鍍;在該等PoP墊位置在該蝕刻層上電鍍一次表面修整層,該次表面修整層係一10族元素;在設置在該封裝體核心上之一晶粒及該等PoP墊位置上方形成至少一增層,該增層包
括多數形成於其中之互連體;及在一與該增層相反之側上暴露該等PoP墊位置。
依據本發明之一實施例,係特地提出一種製造一積體電路(IC)封裝體,包含:一晶粒;一無凸塊增層,其包括形成在該晶粒之一作用側之多數互連層;及多數封裝體疊加(PoP)墊,係形成在該無凸塊增層之一第一側上,其中該等PoP墊具有一表面修整層,且該表面修整層係選自於一由Pd、Ni-Pd、Ni-Pd-Au及Pd-Ni-Pd-Au構成之群組。
依據本發明之一實施例,係特地提出一種積體電路封裝體,包含:一晶粒;一無凸塊增層,其包括形成在該晶粒之一作用側之多數互連層;及多數封裝體疊加(PoP)墊,其具有一非晶質墊表面修整層,且該非晶質墊表面修整層係形成在該無凸塊增層之一第一側。
100‧‧‧積體電路封裝體
107‧‧‧墊表面修整層
112‧‧‧增層
150‧‧‧晶粒
160‧‧‧封裝體疊加(PoP)墊
170‧‧‧接觸墊
190‧‧‧積體電路封裝體
191‧‧‧晶粒
192‧‧‧封裝體基材
193‧‧‧C4焊料凸塊
194‧‧‧焊料球
195‧‧‧整合式散熱器(IHS)
198‧‧‧焊料球
199‧‧‧印刷電路板(PCB)
200‧‧‧BBUL程序流程
202,204,206,208‧‧‧步驟
302‧‧‧假封裝體核心
304A/B‧‧‧黏著膜;黏著層
305A/B‧‧‧蝕刻層
306A/B‧‧‧導電箔
307A/B‧‧‧次表面修整層
308A/B‧‧‧圖案化薄膜層
309A/B‧‧‧導電層
310A/B‧‧‧增層薄膜
311A/B‧‧‧導電互連層
312A/B‧‧‧增層薄膜
313A/B‧‧‧導電互連層
315A/B‧‧‧保護劑
316A/B‧‧‧阻焊(SR)塗層
319B‧‧‧次表面修整層
320‧‧‧保護薄膜
350A/B‧‧‧晶粒
360A/B‧‧‧PoP墊位置
1206‧‧‧第一通訊晶片
2200‧‧‧計算裝置
2202‧‧‧板
2204‧‧‧處理器
2206‧‧‧通訊晶片
圖1A顯示依據本發明一實施例之一積體電路BBUL封裝體的橫截面圖。
圖1B顯示依據本發明一實施例之一封裝體疊加總成之橫截面圖,且該封裝體疊加總成包括與另一積體電路封裝體組裝在一起之一積體電路BBUL封裝體。
圖2顯示用以使用依據本發明一實施例之一無凸塊增層式(BBUL)程序流程製造一積體電路封裝體的一方法。
圖3至21顯示依據本發明一實施例之一無凸塊增層式(BBUL)程序流程之製造步驟時一積體電路封裝體之橫截面
圖。
圖22顯示依據本發明一實施例之一計算系統。
以下詳細說明提出例如特定系統、組件、方法等之多數特定細節,以便良好地了解本發明之數個實施例。所屬技術領域中具有通常知識者應了解的是本發明之至少某些實施例可在沒有這些特定細節之情形下實施。在其他情形中,習知組件或方法未詳細說明或以一簡單方塊圖形式呈現以避免不必要地使本發明不清楚。因此,所提出之特定細節只是示範的。特定實施例可由這些示範細節變化且仍被預期到是在本發明之精神與範疇內。
在說明書之多處中出現該片語“在一實施例中”不一定全部指的是相同實施例。應了解的是本發明之各種實施例雖然不同,但是不一定是互相排他的。此外,在此使用之該等用語“上方”、“下方”、“在...之間”、“在...上”表示一組件相對於其他組件之一相對位置。因此,例如,在另一組件上方、下方或上之一組件可直接接觸另一組件或可具有一或多個中間組件。
在一方面,本發明之實施例揭露一改良無凸塊增層式(BBUL)程序流程,其使封裝體疊加(PoP)墊表面修整層可使用一無電電鍍程序形成。藉使PoP墊表面修整層可使用依據本發明實施例之一無電電鍍程序形成,製造者可不需購買新的表面修整層設備來製造BBUL封裝體。例如,假設
一製造者只有無電表面修整層設備。不需要購買新的表面修整層設備以構成具有一電解表面修整層之多數PoP墊的多數BBUL封裝體,該製造者可重覆使用該製造者已有之相同無電表面修整層設備來構成BBUL封裝體。此外,一無電電鍍之表面修整層可作成比一電解電鍍之表面修整層薄以減少材料成本,且由一無電電鍍程序產生之一表面修整層之非晶質性質亦產生一較高信賴性PoP墊連接。
在另一方面,本發明之實施例揭露用於一BBUL封裝體之PoP墊表面修整層選項,其可由藉該改良BBUL程序流程形成之鈀(Pd)、鎳-鈀(Ni-Pd)、鎳-鈀-金(Ni-Pd-Au)、或鈀-鎳-鈀-金(Pd-Ni-Pd-Au)構成。用以形成這些不同表面修整層選項之改良BBUL程序流程的一部份可使用一無電或一電解電鍍程序實施。這容許製造者在多數表面修整層電鍍程序之間選擇,這將可最佳地重覆使用製造者之現有設備以採用製造者之現有設備來構成BBUL封裝體。
圖1A顯示依據本發明實施例之一積體電路封裝體之橫截面圖。該積體電路封裝體100是一BBUL封裝體,且該BBUL封裝體包括一晶粒150,包括形成在該晶粒150之一作用表面上之多數互連層的一或多數增層112,多數形成在該無凸塊增層112之一側上之封裝體疊加(PoP)墊160,及多數形成在與該第一側相反之該無凸塊增層112之一第二側上之接觸墊170。該等接觸墊170被用來與一插座或一母板電耦合及附接。該晶粒150可以是一微處理器晶粒、一繪圖晶粒、一通訊晶粒、一記憶晶粒、或其他積體電路組件晶
粒。該等PoP墊160具有一墊表面修整層107,且該墊表面修整層107容許另一積體電路封裝體及/或一外電組件封裝體可被焊接在該等PoP墊160上。這容許另一積體電路封裝體及/或一外電組件封裝體可靠近該晶粒150被緊密地耦合在積體電路封裝體100上。
可與積體電路封裝體100之PoP墊160電耦合之該另一積體電路封裝體可以是一積體電路封裝體190,且該積體電路封裝體190包括,例如,透過C4焊料凸塊193安裝在一封裝體基材192上之一晶粒191,一設置在該晶粒191上之整合式散熱器(IHS)195,及多數用以耦合該積體電路封裝體190與積體電路封裝體100之PoP墊160之焊料球194。該積體電路封裝體190之晶粒191可以是另一微處理器晶粒、一繪圖晶粒、一通訊晶粒、或一記憶晶粒。例如封裝體去耦電容器之外電組件封裝體,例如一晶體震盪器之PK封裝體積分率時脈源,及/或容易伴隨長信號線路產生寄生現象之具有高速信號的封裝體電組件亦可與該等PoP墊160耦合。在其他實施例中,其他積體電路封裝體可與該等PoP墊160耦合。
圖1B顯示包括與另一積體電路封裝體190組裝在一起之該積體電路封裝體100之一封裝體疊加總成的橫截面圖。該積體電路封裝體100係在該等接觸墊170透過多數焊料球198附接於例如一母板之一印刷電路板(PCB)199。該積體電路封裝體190係在該等PoP墊160透過多數焊料球194附接於該積體電路封裝體100。藉將該積體電路封裝體190
放置成靠近該積體電路封裝體100之晶粒150,可縮短互連該積體電路封裝體190與該晶粒150之信號通路以減少伴隨長信號線路之信號衰減。此外,連接該積體電路封裝體190與該晶粒150之互連信號可在不需要通過該PCB199之情形下在該等增層112之積體電路封裝體100內路由。這避免伴隨通過一PCB之路由信號的進一步信號衰減。因此,藉使例如積體電路封裝體190之其他積體電路封裝體及/或外電組件封裝體可放置成更靠近該晶粒150,該積體電路封裝體100之PoP墊160可改善一系統之效能。
依據本發明實施例之PoP墊表面修整層選項包括Pd、Ni-Pd、Ni-Au、Ni-Pd-Au、或Pd-Ni-Pd-Au。應注意的是這些表面修整層表示多層不同材料而不是不同化學化合物之次表面修整層。例如積體電路封裝體190及/或外電組件封裝體之其他積體電路封裝體係透過一可由錫、銀及銅構成之焊料耦合於該等PoP墊160。在組裝時,附接於這些其他封裝體之焊料球194係熔化在該等PoP墊160上以形成焊接接頭以便電耦合這些組件與該晶粒150。該PoP墊表面修整層107之性質及材料影響該焊料之溶解度。因此,在該積體電路封裝體100與耦合於該等PoP墊160之例如積體電路封裝體190及/或外電組件封裝體之外電組件封裝體之間的該等焊接接頭之信賴性(即,該等電接頭)係取決於該PoP墊表面修整層107之性質及材料影響該焊料之溶解度。
在某些實施例中,該PoP墊表面修整層107係藉由一無電電鍍程序形成。藉一無電電鍍程序形成之PoP墊表面
修整層107具有一非晶質或非結晶結構。一非晶質PoP墊表面修整層107更具耐腐蝕性且提供一更可焊接表面。此外,一非晶質PoP墊表面修整層107亦容許添加劑添加至該表面修整層以進一步改善該焊接接頭之信賴性。例如,在一實施例中,一等於或小於5重量%量之磷添加劑可添加至該非晶質PoP墊表面修整層107以改善焊接接頭信賴性。藉改善焊接接頭信賴性,該PoP墊表面修整層107亦可形成為更薄以減少材料成本。在一實施例中,該非晶質PoP墊表面修整層107可為大約等於或小於60奈米(nm)。
在其他實施例中,該PoP墊表面修整層107可以使用一電解電鍍程序形成。一互連該等PoP墊位置之導電層必須可實施該電解電鍍程序。雖然一電解電鍍程序會產生一結晶表面修整層,但是具有包括Pd之PoP墊表面修整層107的實施例仍可提供一改良PoP墊,因為Pd比其他表面修整層材料更不易氧化且更具耐腐蝕性。在一實施例中,藉一電解程序形成之PoP墊表面修整層107之厚度可為等於或小於300nm。
圖2顯示用以形成依據本發明實施例之一BBUL封裝體之一BBUL程序流程200的流程圖。在步驟202,提供一封裝體核心,且在該封裝體核心上形成多數封裝體疊加(PoP)墊位置。該等多數PoP墊位置係電解或無電電鍍有一例如銅(Cu)之導電材料之蝕刻層。在步驟204,一例如鈀(Pd)或鎳(Ni)之10族元素次表面修整層層係無電或電解電鍍在該導電材料之蝕刻層上。在某些實施例中,另一10族元素
之另一次表面修整層層可無電或電解電鍍在該第一次表面修整層層上。在步驟206,在一設置在該封裝體核心上之晶粒上方且在該等POP墊位置上方形成包括其中形成多數互連體之至少一增層。設置在該封裝體核心上之晶粒被該增層至少部份地覆蓋或封裝。該增層亦形成在該等PoP墊位置上方以覆蓋該PoP墊位置。該增層可包括形成於其中之互連體以互連該晶粒與該等PoP墊位置。在步驟208,使該等PoP墊位置暴露在與該增層相反之側。在某些實施例中,該等暴露之PoP墊位置在步驟208後將具有最後表面修整層。在其他實施例中,該等PoP墊之最後表面修整層係藉無電電鍍及/或浸鍍另外之次表面修整層層的另外步驟而形成。
以下將參照圖3至21更詳細地說明該BBUL程序流程200。圖3至21顯示一BBUL封裝體在依據本發明實施例之一BBUL程序流程之各種階段之製造步驟時形成的橫截面圖。表1總結用於依據本發明實施例之各種PoP墊表面修整層之BBUL程序流程200。
在步驟202中提供具有電鍍有一導電材料之蝕刻層之多數PoP墊位置之一封裝體核心的操作係顯示在圖3至5中。在圖3中,設有一假封裝體核心302。該假封裝體核心302係作為一載體使用,且各種BBUL封裝體層係建構在該載體上。應注意的是兩BBUL封裝體(在該假封裝體核心302之各側上各一)可藉由利用該封裝體核心之兩側形成在該假封裝體核心302上。如圖3所示,一BBUL封裝體可形成在該假封裝體核心302之頂側,且另一BBUL封裝體可形成在該假封裝體核心302之底側。在該BBUL程序流程200之一稍後階段移除該假封裝體核心302。形成在該假封裝體核心302之
頂側之BBUL封裝體將具有一靠近該假封裝體核心302之頂側的晶粒側(與該焊墊側相反),且形成在該假封裝體核心302之底側之另一BBUL封裝體將具有一靠近該假封裝體核心302之底側的晶粒側(與該焊墊側相反)。在另一實施例中,只有一BBUL封裝體可形成在該假封裝體核心302之一側。
圖4顯示依據某些實施例在該假封裝體核心302上層疊一黏著膜304A/B且在該黏著膜304A/B上層疊該導電材料之一導電箔306A/B後的結構。該黏著膜304A/B作為一黏著層以容許該BBUL封裝體可建構在該假封裝體核心302上。在一實施例中,黏著膜304A/B是一聚對苯二甲酸乙二酯(PET)薄膜。在其他實施例中,可使用其他黏著材料作為該黏著層。該導電箔306A/B可由Cu或其他導電材料構成。在使用一電解電鍍程序之實施例中,可使用該導電箔306A/B作為在該BBUL程序流程200之後續階段中之電解電鍍程序中用於一電極之一連接點。
圖5顯示在層疊一圖案化薄膜層308A/B以形成該等PoP墊位置360A/B,或在該PoP墊位置360A/B上無電或電解電鍍一導電材料之蝕刻層305A/B後的結構。在一實施例中,該圖案化薄膜層308A/B是一乾膜電阻(DRF)層。將該圖案化薄膜層顯影以界定該等PoP墊位置360A/B。在界定該等PoP墊位置360A/B後,將一蝕刻層305A/B電鍍在該導電箔306A/B上。在一實施例中,該蝕刻層305A/B係由與該導電箔306A/B相同之材料構成,例如,Cu。在其他實施例中,
亦可使用其他可蝕刻導電材料作為該蝕刻層305A/B。
以下將參照圖6說明在依據本發明實施例之BBUL程序流程200之步驟204中在該導電材料之蝕刻層305A/B上無電或電解電鍍一10族元素次表面修整層307A/B的操作。在步驟204中,在該等PoP墊位置將一例如Pd或Ni之10族元素電鍍在該蝕刻層305A/B上以形成一次表面修整層307A/B。該次表面修整層307A/B可利用一無電電鍍程序或一電解電鍍程序電鍍。在一實施例中,該次表面修整層307A/B是Pd,且是唯一表面修整層以形成一Pd PoP墊表面修整層。在另一實施例中,將另一Ni層無電或電解電鍍在該Pd次表面修整層以形成一Ni-Pd PoP墊表面修整層。在這些實施例中,被電鍍在該蝕刻層305A/B上之Pd作為用於該BBUL程序流程200之後續步驟中之蝕刻程序的一防蝕刻或障壁層。被直接電鍍在該蝕刻層305A/B上之Pd亦是將在得到之BBUL封裝體中暴露之材料。Pd比其他表面修整層材料更不容易氧化,且因此藉具有Pd作為該暴露材料,得到之PoP墊表面修整層將比較不易受到腐蝕。
在其他其他中,在步驟204中被無電或電解電鍍在該蝕刻層305A/B上之次表面修整層307A/B是Ni。在這些實施例中,另外之次表面修整層係在該BBUL程序流程200之後續步驟中形成以形成Ni-Au或Ni-Pd-Au PoP墊表面修整層。在一不同實施例中,一Pd層被無電或電解電鍍在該次表面修整層307A/B上。在這不同實施例中,另外之次表面修整層係形成在該BBUL程序流程200之後續步驟中以形成
一Pd-Ni-Pd-Au PoP墊表面修整層。
以下將參照圖7至16說明在依據本發明實施例之設置在該假封裝體核心302上之一晶粒及該等PoP墊位置360A/B上方形成包括多數互連體之至少一增層之步驟206中的操作。另一導電層309A/B被無電或電解電鍍在該PoP墊位置360A/B上。在一實施例中,該導電層309A/B係由Cu或一Cu合金構成。在其他實施例中,可使用其他導電材料。接著剝除該圖案化薄膜層308A/B而產生如圖7所示之BBUL結構。在欲安裝一晶粒至該黏著層304A/B之位置向下蝕刻該導電箔306A/B到該黏著層304A/B。接著將一晶粒350A/B安裝在該黏著層304A/B上,如圖8所示。
接著,形成一互連層作為該增層之一部份以封裝該晶粒350A/B之至少一部份。將一增層薄膜310A/B層疊在該晶粒350A/B之至少一部份及該等PoP墊位置360A/B上方。在其他實施例中,該增層薄膜310A/B可封裝整個晶粒350A/B。在一示範實施例中,該增層薄膜310A/B是一味之素增層薄膜(Ajinomoto build-up film,ABF)。在其他實施例中,可使用其他增層材料。在圖10中,實施雷射蝕刻以在該增層薄膜310A/B中形成多數通孔位置。由該增層薄膜310A/B蝕刻之通孔位置包括在PoP墊位置360A/B及在該晶粒350A/B上之接觸墊位置的接觸點。在圖11中,一導電互連層311A/B被無電或電解電鍍在該等通孔位置上方以互連該等通孔位置。該導電互連層311A/B可由Cu,或其他導電材料構成。該導電互連層311A/B電連接該等PoP墊位置
360A/B與來自該晶粒350A/B之信號。
在某些實施例中,另外之互連層可形成在另外之增層中,如圖12至14所示。在圖12中,另一增層薄膜312A/B,例如,一ABF,被層疊在該導電互連層311A/B上方。另外之通孔位置被雷射蝕刻至增層薄膜312A/B中,如圖13所示。另一導電材料之導電互連層313A/B被無電或電解電鍍在該等通孔位置上,如圖14所示。在其他實施例中,其中形成互連體之任何數目之另外增層可藉重覆層疊另一增層薄膜、雷射蝕刻另外之通孔位置通過該另一增層薄膜、及無電或電解電鍍連接該等另外之通孔位置之另一導電互連層的步驟而形成。
在該BBUL封裝體之增層中形成該等互連層後,在該最後導電互連層313A/B上塗覆一阻焊(SR)塗層316A/B。將該SR塗層316A/B圖案化以在該BBUL封裝體之焊墊側形成接頭墊位置,如圖15所示。在某些實施例中,這些接頭墊位置係用於電連接該BBUL封裝體與一插座或一母板之接觸點。在圖16中,一保護劑315A/B塗覆在該等接頭墊位置上。在一實施例中,該保護劑315A/B是一有機可焊性保護劑(OSP)。在其他實施例中,其他保護劑可用以保護該等接頭墊位置之焊料黏著性質。
以下將參照圖17與18說明在該BBUL程序流程200之步驟208中暴露該等PoP墊位置360A/B之操作。在圖17中,該假封裝體核心302被分離以分離形成在該假封裝體核心302上之兩BBUL封裝體。在其他實施例中,只有一BBUL封
裝體可形成在該假封裝體核心302上。接著移除該假封裝體核心302及該黏著層304A/B。蝕刻去除該蝕刻層305A/B及該導電箔306A/B之任何剩餘部份以暴露該等PoP墊位置360A/B。得到之BBUL封裝體係顯示在圖18中。
在具有Pd被無電或電解電鍍在該導電箔306A/B上之Pd或Ni-Pd之PoP墊表面修整層選項的實施例中,該PoP墊表面修整層是完整的,且其他積體電路裝置及/或外電組件可在該等PoP墊位置360A/B安裝在BBUL封裝體上。以下將參照圖19至21說明在Ni被無電或電解電鍍在該導電箔306A/B上之其他實施例中,用以形成Ni-Au、Ni-Pd-Au或Pd-Ni-Pd-Au之最後PoP墊表面修整層選項之多數另外的加工步驟。
在圖19中,一保護薄膜320被層疊在該等焊墊側接頭墊位置上以保護該等接觸墊。在圖20中,該等另外之次表面修整層319B係形成在該等PoP墊位置360A/B上。記得該導電箔306A/B已移除,且因此,在某些實施例中,無法使用一電解電鍍程序形成該等另外之次表面修整層319B。在具有Ni-Au、Ni-Pd-Au或Pd-Ni-Pd-Au之PoP墊表面修整層選項之實施例中,另一Ni層可被電鍍在該次表面修整層307B。在這些實施例中,該Ni次表面修整層307B在蝕刻該蝕刻層305A/B時暴露。因為Ni作為一防蝕刻或障壁層之效果比Pd差,某些Ni次表面修整層307B會在蝕刻程序時已被蝕刻去除。為修復該Ni次表面修整層307B之表面,可在該Ni次表面修整層307B上電鍍另一Ni層以便為形成該墊表面
修整層之後續步驟提供一較佳表面。就該Ni-Au PoP墊表面修整層實施例而言,一金(Au)層被浸鍍在該Ni層上以形成該Ni-Au PoP墊表面修整層。就該Ni-Pd-Au及Pd-Ni-Pd-Au PoP墊表面修整層實施例而言,在浸鍍Au之前,一Pd層被無電電鍍在該Ni層上以形成該Ni-Pd-Au或Pd-Ni-Pd-Au PoP墊表面修整層。在圖21中,移除該保護薄膜320以形成得到之BBUL封裝體。
圖22顯示依據本發明一實施例之一計算裝置2200。該計算裝置2200收容一板2202。該計算裝置2200可包括多數組件,包括但不限於一處理器2204及至少一通訊晶片2206。該處理器2204係實體地且電氣地耦合於該板2202。在某些實施例中該至少一通訊晶片2206亦實體地且電氣地耦合於該板2202。在其他實施例中,該通訊晶片2206係該處理器2204之一部份。
依據其應用,計算裝置2200可包括會或不會實體地且電氣地耦合於該板2202的其他組件。這些其他組件包括,但不限於,依電性記憶體(例如,DRAM)、非依電性記憶體(例如,ROM)、快閃記憶體、一圖形處理器、一數位信號處理器、一密碼處理器、一晶片組、一天線、一顯示器、一觸控螢幕顯示器、一觸控螢幕控制器、一電池、一聲頻編碼解碼器、一視訊編碼解碼器、一功率放大器、一全球定位系統(GPS)裝置、一指南針、一加速計、一陀螺儀、一揚聲器、一照相機、及一大量儲存裝置(例如硬碟、光碟(CD)、數位多功能光碟(DVD)等)。
該通訊晶片2206可進行無線通訊以便傳送資料至該計算裝置2200及由該計算裝置2200傳送資料。該用語“無線”及其衍生字亦可用於說明可透過使用調變電磁輻射且透過一非實體媒體傳送資料之電路、裝置、系統、方法、技術、通訊通道等。該用語不表示相關裝置不包含電線,但是在某些實施例中該等相關裝置可不包含電線。該通訊晶片2206可實施任何數目之無線標準或協定,包括但不限於Wi-Fi(IEEE802.11家族)、WiMAX(IEEE802.16家族)、IEEE802.20、長期進化(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物,及被稱為3G、4G、5G等之任何其他無線協定。該計算裝置2200可包括多數通訊晶片2206。例如,一第一通訊晶片1206可專用於例如Wi-Fi及藍芽之較短範圍無線通訊且一第二通訊晶片2206可專用於例如、GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO等之較長範圍無線通訊。
該計算裝置2200之處理器2204包括一封裝在該處理器2204內之積體電路晶粒。在本發明之某些實施例中,該積體電路晶粒被封裝在一BBUL封裝體中且藉依據本發明實施例之BBUL程序流程形成一PoP墊一表面修整層。該用語“處理器”可表示任何裝置或一裝置之一部份,其處理來自暫存器及/或記憶體之電子資料以將該等電子資料轉變成可儲存在暫存器及/或記憶體之其他電子資料。
該通訊晶片2206亦包括一封裝在該通訊晶片
2206之積體電路晶粒。依據本發明之另一實施例,該通訊晶片2206之積體電路晶粒被封裝在一BBUL封裝體中且藉依據本發明實施例之BBUL程序流程形成一PoP墊一表面修整層。
在其他實施例中,被收容在該計算裝置2200內之另一組件可包含一積體電路晶粒,且該積體電路晶粒被封裝在一BBUL封裝體中且藉依據本發明實施例之BBUL程序流程形成一PoP墊一表面修整層。
在各種實施例中,該計算裝置2200可為一膝上型電腦、一輕省筆電、一筆記型電腦、一超薄型筆電、一智慧型手機、一平板電腦、一個人數位助理(PDA)、一超級移動電腦、一行動電話、一桌上型電腦、一伺服器、一印表機、一掃描器、一螢幕、一機上盒、一娛樂控制單元、一數位相機、一可攜式音樂播放器、或一數位錄影機。在其他實施例中,該計算裝置2200可為處理資料之任何其他電子裝置。
該等較佳實施例之前述說明係提供成用以使所屬技術領域中具有通常知識者製造或使用本發明。可對這些實施例進行各種修改,且在此提出之通用原理亦可應用於其他實施例。因此,本發明不是意圖受限於以上所示實施例,而是與符合在此以任何方式揭露之原理及新特徵之最大範圍一致。
該等較佳實施例之前述說明係提供成用以使所屬技術領域中具有通常知識者製造或使用本發明。可對這
些實施例進行各種修改,且在此提出之通用原理亦可應用於其他實施例。因此,本發明不是意圖受限於以上所示實施例,而是與符合在此以任何方式揭露之原理及新特徵之最大範圍一致。
100‧‧‧積體電路封裝體
107‧‧‧墊表面修整層
112‧‧‧增層
150‧‧‧晶粒
160‧‧‧封裝體疊加(PoP)墊
170‧‧‧接觸墊
190‧‧‧積體電路封裝體
191‧‧‧晶粒
192‧‧‧封裝體基材
193‧‧‧C4焊料凸塊
194‧‧‧焊料球
195‧‧‧整合式散熱器(IHS)
198‧‧‧焊料球
199‧‧‧印刷電路板(PCB)
Claims (25)
- 一種用於製造積體電路(IC)封裝體的方法,該方法包含以下步驟:使一封裝體核心具有形成於該封裝體核心上的多個封裝體疊加(PoP)墊位置,其中,該等多個PoP墊位置鍍有為導電材料的一蝕刻層;在位於該等PoP墊位置處的該蝕刻層上鍍上為一10族元素的一次表面修整層;在設置於該封裝體核心上的一晶粒及該等PoP墊位置上形成至少一增層,該增層含有形成於該增層內的數個互連體;以及在與該增層相反之側暴露出該等PoP墊位置。
- 如申請專利範圍第1項之方法,其中,該次表面修整層是Pd,用以形成一Pd PoP墊表面修整層。
- 如申請專利範圍第1項之方法,其中,該次表面修整層是Pd,且該方法進一步包含以下步驟:在該次表面修整層上鍍上Ni,以形成一Ni-Pd PoP墊表面修整層。
- 如申請專利範圍第1項之方法,其中,該次表面修整層是Ni,且該方法進一步包含以下步驟:在暴露出該等PoP墊位置之後:在該等PoP墊位置上浸鍍金(Au),以形成一Ni-Au PoP墊表面修整層。
- 如申請專利範圍第1項之方法,其中,該次表面修整層是Ni,且該方法進一步包含以下步驟:在暴露出該等PoP墊位置後:在該等PoP墊位置上無電電鍍上一Pb層;以及在該Pd層上浸鍍金(Au),以形成一Ni-Pd-Au PoP墊表面修整層。
- 如申請專利範圍第1項之方法,其中,該次表面修整層是Ni,且該方法進一步包含以下步驟:將該次表面修整層上鍍上一層Pd;在暴露出該等PoP墊位置之後:在該等PoP墊位置上無電電鍍上一附加Pd層;以及在該附加Pd層上浸鍍金(Au),以形成一Pd-Ni-Pd-Au PoP墊表面修整層。
- 如申請專利範圍第1項之方法,其中,使該封裝體核心具有該等多個封裝體疊加(PoP)墊位置的該步驟包含:提供一封裝體核心;在該封裝體核心的一表面上層疊一黏著薄膜;在該黏著薄膜上層疊為該導電材料的一導電箔;層疊一圖案化薄膜層以形成該等PoP墊位置;以及在該等PoP墊位置上鍍上該蝕刻層。
- 如申請專利範圍第1項之方法,其中,形成含有互連體的至少一增層的該步驟包含:在該等PoP墊位置上鍍上為該導電材料的一導電 層;剝除該圖案化薄膜層;蝕刻該導電箔的一部份,以暴露出該黏著薄膜的一區域;將該晶粒安裝至該黏著薄膜上;在該晶粒上形成該等增層中之一者,包含:層疊一增層薄膜;雷射蝕刻數個通孔位置;鍍上連接該等通孔位置的一導電互連層;以一阻焊塗層塗覆該導電互連層;將該阻焊層圖案化以形成數個接觸墊位置;以及以一保護劑塗覆該等接觸墊位置。
- 如申請專利範圍第8項之方法,其中,形成含有互連體的至少一增層的該步驟進一步包含:形成數個附加增層,其中,係藉由以下步驟來形成各個附加增層:層疊一附加增層薄膜;穿透該附加增層薄膜而雷射蝕刻數個附加通孔位置;鍍上連接該等附加通孔位置的一附加導電互連層。
- 如申請專利範圍第1項之方法,其中,暴露出該等PoP墊位置的該步驟包含:分離該封裝體核心; 移除該黏著薄膜;以及將該蝕刻層及該導電箔之剩餘部份蝕刻掉。
- 如申請專利範圍第1項之方法,其中,該導電材料是銅(Cu)。
- 如申請專利範圍第7項之方法,其中,該黏著薄膜是一聚對苯二甲酸乙二酯(PET)薄膜。
- 如申請專利範圍第8項之方法,其中,該增層薄膜是一味之素增層薄膜(ABF)。
- 如申請專利範圍第8項之方法,其中,該保護劑是一有機可焊性保護劑(OSP)。
- 一種積體電路封裝體,其包含:一晶粒;一無凸塊增層,其包括形成於該晶粒之一作用側上的多個互連層;以及形成於該無凸塊增層之一第一側上的多個封裝體疊加(PoP)墊,其中,該等PoP墊具有一表面修整層,該表面修整層係選自於由無電Pd、無電Ni-Pd、無電Ni-Pd-Au和無電Pd-Ni-Pd-Au所構成之群組。
- 如申請專利範圍第15項之積體電路封裝體,其中,該表面修整層具有小於或等於300奈米(nm)的厚度。
- 如申請專利範圍第15項之積體電路封裝體,其中,該表面修整層具有小於或等於60nm的厚度。
- 如申請專利範圍第15項之積體電路封裝體,其進一步包含: 形成於該無凸塊增層之與該第一側相反的一第二側上的多個接觸墊位置。
- 如申請專利範圍第15項之積體電路封裝體,其中,一積體電路組件透過一焊料而耦接至該等PoP墊,以電連接該積體電路組件與該晶粒。
- 一種積體電路封裝體,其包含:一晶粒;一無凸塊增層,其包括形成在該晶粒之一作用側上的多個互連層;以及多個封裝體疊加(PoP)墊,其具有形成於該無凸塊增層之一第一側上的一非晶質墊表面修整層。
- 如申請專利範圍第20項之積體電路封裝體,其中,該非晶質墊表面修整層係選自於由Pd、Ni-Pd、Ni-Au、Ni-Pd-Au和Pd-Ni-Pd-Au所構成之群組。
- 如申請專利範圍第20項之積體電路封裝體,其中,該非晶質墊表面修整層包含一磷添加劑。
- 如申請專利範圍第20項之積體電路封裝體,其中,該非晶質墊表面修整層具有小於或等於60nm的厚度。
- 如申請專利範圍第20項之積體電路封裝體,其進一步包含:在該無凸塊增層之與該第一側相反的一第二側上的多個接觸墊。
- 如申請專利範圍第20項之積體電路封裝體,其進一步包含: 一電組件,其透過一焊料而耦接至該等PoP墊,以使該電組件電連接至該晶粒。
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CN102605359A (zh) * | 2011-01-25 | 2012-07-25 | 台湾上村股份有限公司 | 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺 |
JP5270030B1 (ja) * | 2012-09-24 | 2013-08-21 | 日本写真印刷株式会社 | タッチパネル、及びタッチパネルの製造方法 |
US9331054B2 (en) * | 2013-03-14 | 2016-05-03 | Mediatek Inc. | Semiconductor package assembly with decoupling capacitor |
US9508636B2 (en) | 2013-10-16 | 2016-11-29 | Intel Corporation | Integrated circuit package substrate |
US9275955B2 (en) | 2013-12-18 | 2016-03-01 | Intel Corporation | Integrated circuit package with embedded bridge |
TWI538591B (zh) * | 2014-05-01 | 2016-06-11 | Tong Hsing Electronic Ind Ltd | Method for manufacturing multilayer ceramic heat dissipation circuit substrate and its product |
US9603247B2 (en) | 2014-08-11 | 2017-03-21 | Intel Corporation | Electronic package with narrow-factor via including finish layer |
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US20110147933A1 (en) * | 2009-12-22 | 2011-06-23 | Tao Wu | Multiple surface finishes for microelectronic package substrates |
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