TWI506745B - 電子裝置及電子裝置製造方法 - Google Patents

電子裝置及電子裝置製造方法 Download PDF

Info

Publication number
TWI506745B
TWI506745B TW101146178A TW101146178A TWI506745B TW I506745 B TWI506745 B TW I506745B TW 101146178 A TW101146178 A TW 101146178A TW 101146178 A TW101146178 A TW 101146178A TW I506745 B TWI506745 B TW I506745B
Authority
TW
Taiwan
Prior art keywords
substrate
die
semiconductor
pads
electronic device
Prior art date
Application number
TW101146178A
Other languages
English (en)
Other versions
TW201342550A (zh
Inventor
Choong Kooi Chee
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201342550A publication Critical patent/TW201342550A/zh
Application granted granted Critical
Publication of TWI506745B publication Critical patent/TWI506745B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

電子裝置及電子裝置製造方法
本發明係有關嵌入式矽穿孔技術。
已開發具有矽穿孔(TSV)互連結構的三維(3D)積體電路。TSV晶粒結構一般包含在矽中的垂直穿孔(取決於製程，界定穿孔的側壁可以不是垂直的)，垂直穿孔中含有導電材料且被用來製造互連。使用延伸穿過矽的矽穿孔(TSV)，可以造成比其它路由方法更縮短的互連長度、增進的電性能、及降低的耗電。
揭示電子組成件及其製造。一個實施例係有關裝置，此裝置包含多層基板，多層基板包括多個介電層及金屬層，多層基板包含第一側及第二側。半導體晶粒係嵌入於基板中，晶粒包含從晶粒的第一端延伸至第二端的多個半導體穿孔。半導體穿孔係電耦合至由金屬層所界定的導電路徑，導電路徑包含從晶粒的第一端延伸至基板的第一側上的墊的路徑、以及從晶粒的第二端延伸至基板的第二側上的墊的路徑。晶粒中的多個半導體穿孔具有小於基板的第一側上的墊的間距之間距。晶粒中的多個半導體穿孔具有也小於基板的第二側上的墊的間距之間距。
於下將參考圖式，其中，類似的結構係由類似代號來予以標示。為了最清楚地顯示各種實施例的結構，包含於其中的圖式包含電子裝置的概圖表示。因此，製成的結構之真正外觀可能不同，但是仍然具有所示的實施例之主張結構。此外，圖式僅顯示瞭解所示的實施例所需的結構。並未包含此技藝中所知的其它結構以使圖式簡明清楚。
某些實施例係有關於組成件結構，組成件結構包括嵌入於基板中的包含矽穿孔之晶粒(此處也稱為TSV晶粒)、以及間距大於晶粒中的矽穿孔的間距之從穿孔延伸至基板表面上的電路徑。
圖1顯示依據某些實施例之組成件(assembly)的互連細節，該組成件包含基板2，基板2包含具有矽穿孔(TSV)6的嵌入晶粒4。基板2包含多個介電層8、10、12、14、16。不同數目的層(更多或更少)也是可能的。如圖1中所示，基板2包含頂部介電層8上的第一表面18及底部介電層16上的第二表面20。在圖1中所示的實施例中，TSV晶粒4係位於堆疊中的中央介電層12之內。在其它實施例中，TSV晶粒可位於與圖1所示之不同的層堆疊中的垂直位置。TSV 6包含導電材料於其中。可以使用任何適當的導電材料，包含例如金屬。如同此處所使用般，金屬一詞包含純金屬及合金。基板2也包含從TSV延伸至第一表面18上的接合墊22以及第二表面20上的接合墊24之導電路徑。導電路徑可行經穿孔及沿著介電層 之內的佈線層。訊號可以經由組成件而往返，包含例如從接合墊24經過介電層16中的穿孔26及佈線層28、經過介電層14中的穿孔30及佈線層32、經過介電層12中晶粒4的TSV 6、經過介電層10中的佈線層34及穿孔36、以及經過介電層8中的佈線層38及穿孔40，以便到達接合墊22。
如圖1中所示，在矽晶粒4中的TSV具有小於第一表面18上的接合墊22的間距並且小於第二表面20上的接合墊24的間距之晶距(它們之間的間隔)。此種結構致使設有TSV 6的嵌入晶粒4能夠更容易被連接至其它結構，例如經由凸塊42而被耦合至基板2的組件48。在某些實施例中，組件48可以選自由處理器及記憶體組成的族群。如圖1中所示的基板2也經由凸塊44而被耦合至結構50。在某些實施例中，結構50可為主機板(motherboard)。基板2的第一表面18上的墊22的間距無需與基板2的第二表面20上的墊24的間距相同。如圖1中所示，在基板2的第一表面18上的墊22的間距係小於第二表面20上的墊24的間距。
某些實施例係有關包含嵌入式矽穿孔晶粒之基板的製造方法。實施例可有關於具有核心的基板及無核心基板兩者的形成。可以使用各種適當的方法來製造此種基板。矽穿孔(TSV)晶粒，單獨地、或是位於介電層之內的一個矽穿孔(TSV)晶粒在某些實施例中用作為初始層，而其它層可以被形成在此初始層上。在其它實施例中，下層可 用作為初始層及位於其上的矽穿孔(TSV)晶粒。
圖2顯示無核心基板處理實施例中的操作，其中，使用包含例如Cu等金屬之暫時的核心材料52。在圖2中所示的無核心基板製造實施例中，介電質及金屬層可被累增於暫時核心52的相對側上，並且，暫時的核心稍後被移除以產生二個基板結構。如圖2所示，具有與圖1中的基板2相同的層結構之基板結構可以被形成於暫時的核心52之相對側上。在移除暫時的核心52之後，將會造成均包含嵌入式矽穿孔晶粒4之二個基板結構。
圖3顯示圖1的基板2的視圖，其包含介電層12，而包含矽穿孔(TSV)6的矽穿孔(TSV)晶粒4係位在介電層12中。矽穿孔(TSV)晶粒4係位於介電層12中的中央開口內。在某些實施例中，可使用結合的介電層12及矽穿孔(TSV)晶粒4作為初始層，而其它層被形成於初始層上以便製造多層基板。圖3的放大部份顯示介電層12與矽穿孔(TSV)晶粒4之間的介面，並且，顯示黏著劑35出現在它們之間。在某些實施例中，取決於例如使用的材料及介電層12形成方法的特徵，要在介電層12與矽穿孔(TSV)晶粒4之間形成適當的接合，並不一定需要黏著劑35。使用任何適當方法(包含但不限於遮罩、蝕刻、及沈積製程)，形成如圖3中所例舉般其周圍被介電層所圍繞之矽穿孔(TSV)晶粒4。舉例而言，形成介電層，然後，開口被形成在介電層中，並且矽穿孔(TSV)晶粒係位在開口之內。或者，可設置矽穿孔(TSV)晶粒，然 後介電層被沈積在晶粒周圍。
圖1-3顯示包含無核心基板的特徵。圖4顯示包含具有核心層127的基板102之實施例，其它層被形成在核心層127上。核心層127可以由任何適當的材料所形成，舉例而言，材料可為包含浸漬環氧樹脂材料之編織玻璃層的層疊多層結構。核心層127可包含多個延伸經過核心層127之電路徑129。設有矽穿孔106的矽穿孔晶粒104可位於核心層127上，且矽穿孔106中的導電材料係電耦合至核心層127中的電路徑129。矽穿孔晶粒104係位於介電層112之內。介電層110被形成在矽穿孔晶粒104上及介電層112上，並且，介電層108被形成在介電層110上。介電層114係位於與介電層112相對立的核心層127的側上，並且，介電層116係形成於介電層114上。
如圖4所示，基板包含在頂部介電層108上的第一表面118、在底部介電層116上的第二表面120，第二表面120包含形成於其上的接合墊124。訊號可以經由組成件而往返，包含例如從接合墊24經過介電層116中的穿孔126及佈線層128、經過介電層114中的穿孔130及佈線層132、經過核心127中的導電路徑129、經過介電層112中晶粒104的矽穿孔106、經過介電層110中的金屬佈線層134及穿孔136、以及經過介電層108中的佈線層138及穿孔140，以便到達接合墊122。
圖5顯示包含具有核心227的基板之實施例中，其中，矽穿孔晶粒204係位於核心227中而非如圖4中所示 般位於接鄰於核心的列中。如圖5所示，核心227及矽穿孔晶粒204係形成為具有相同的厚度，使得矽穿孔晶粒204可適配於核心227中的開口之內。由於含有矽穿孔晶粒204的層227是與圖5的介電層208、210、214、及216不同的核心層，而圖1中含有矽穿孔晶粒之層12是類似於或同於介電層8、10、14、及16，所以，圖5中的基板與圖1中所示的基板不同。訊號可行經基板，舉例而言，從穿孔126經過介電層216中的佈線層228、經過佈線層214中的穿孔230及佈線層232、經過核心層127中的矽穿孔206、經過介電層210中的佈線層234及穿孔236、經過佈線層238及穿孔240而至接合墊220。
實施例也可包含嵌入於基板內之一個以上的晶粒。舉例而言，圖6顯示實施例，其包含介電層308、310、312、314、及316，且具有矽穿孔306的一個以上的矽穿孔晶粒304係位於介電層314之內。替代地，各矽穿孔晶粒結構304可位於基板的不同介電層中。雖然圖6中顯示二個矽穿孔晶粒結構304，但是，更多的矽穿孔晶粒結構304也可以位於基板之中。
實施例提供與尺寸及製造容易度有關的一或更多個優點。首先，藉由將矽穿孔晶粒結構嵌入於基板中，可降低整體組成件的厚度。其次，藉由將矽穿孔晶粒結構嵌入於基板中，可在從嵌入式矽穿孔晶粒延伸至基板上及下表面之層中導出對裝置的接點，使得在表面處的接合墊具有的間距大於在嵌入式矽穿孔晶粒的表面處的接點。在某些實 施例中，矽穿孔晶粒的頂端部在接點之間具有25至50微米的接點間距。為了將另一裝置(舉例而言，記憶體裝置)附接至緊密接點間距的矽穿孔晶粒，使用習稱為熱壓縮接合(TCB)之複雜及昂貴的附接製程。但是，藉由將矽穿孔晶粒嵌入在基板中，在矽穿孔晶粒與基板表面之間的層用以將接點的間距分散開至增加的值，其致能使用較不複雜及較不昂貴的附接製程而將晶粒或裝置附接至基板。
圖7顯示依據某些實施例之用以形成嵌入式矽穿孔晶粒基板及包含基板之組成件的流程圖。框401提供矽穿孔晶粒。框403在矽穿孔晶粒上增建介電層及金屬層，並且將矽穿孔的間距分散開，使得在基板表面的接點具有較不濃密的間距而更容易附接至其它裝置。框405將銲球耦合至基板，以便用於後續附接至電路板(board)。框407將組成件(包含但不限於例如CPU(中央處理單元)或記憶體封裝組件等晶粒結構)附接至基板的頂表面。框409使用銲球連接而將基板(包含附接於其上的組成件)附接至電路板。
圖8顯示實施例，其包含依據某些實施例的記憶體裝置，其中，包含多個記憶體晶片的記憶體封裝組件被耦合至嵌入式矽穿孔晶粒基板。組成件包含經由銲材凸塊542而被耦合至多層基板502之多個記憶體晶粒結構548。下填充也出現在晶粒結構548之間以及下晶粒結構548與基板502之間。多層基板502包含入式矽穿孔晶粒504。基 板502接著經由銲材凸塊544而耦合至電路板550。
應瞭解到，在此處所述的實施例的範圍之內，可以作很多改變。舉例而言，雖然將矽穿孔晶粒說明成矽晶粒結構，但是，穿孔也可以延伸通過其它材料，舉例而言，其它材料包含但不限於砷化鎵。延伸穿過半導體的這些穿孔稱為半導體穿孔。矽穿孔是延伸穿過矽的半導體穿孔的實例。結果，如此處所述的實施例可以應用至不是由矽所形成的晶粒結構。此處使用的晶粒一詞意指由不同製程操作轉換成所需電子裝置之工件。晶粒通常係切割自晶圓，而晶圓係由半導體、非半導體、或是半導體及非半導體材料的組合所製成。
包含如上述實施例所述般形成的結構之組成件可被應用在各種電子組件中。圖9顯示電子系統環境的一個實例，其中，具體實施上述實施例的態樣。其它實施例不需要包含圖9中所指的所有特徵，可以包含圖9中未指明的替代特徵。
圖9的系統600可包含在封裝基板685中的至少一中央處理單元(CPU)683(也稱為微處理器)。在某些實施例中，CPU 683(由虛線指示以表示其被嵌入於基板685中)可為例如上述實施例中所述的嵌入式矽穿孔晶粒，嵌入式矽穿孔晶粒被耦合至印刷電路板687(舉例而言，主機板)。記憶體689a係位於基板685上以形成例如如上所述及圖8中所示的組成件。各式各樣的其它系統組件也可包含根據例如上述所述的實施例而形成的結構。 藉由在基板685上設置各式各樣的組件(例如，記憶體689a)，可降低整個系統的尺寸。
系統600可又包含額外的記憶體689b及也被配置在主機板687上的一或更多個控制器691a、691b、...、691n。主機板687可為具有多個導線的單層或多層板，多個導線提供介於封裝基板685中的電路與安裝至主機板687之其它組件之間的通訊。替代地，一或更多個各式各樣的組件可以被配置在例如子卡或是擴充卡等其它卡上。組件也可被安裝於插座中或是被直接連接至印刷電路板或全部整合在相同的封裝組件中。也可包含顯示器695。
任何適當的操作系統及各種應用程式執行於CPU 683中並且存在於記憶體689a、689b中。根據習知的快取技術，可快取存在於記憶體689a、689b中的內容。在記憶體689a、689b中的程式及資料可被交換至儲存器693中，作為記憶體管理操作的一部份。系統600可包含任何適當的計算裝置，包含但不限於主電腦、伺服器、個人電腦、工作站、膝上型電腦、手持電腦、筆記型電腦、平板電腦、電子書閱讀器、手持遊戲裝置、手持娛樂裝置(舉例而言，MP3(動畫專家群組層-3)音頻播放器)、PDA(個人數位助理)電話裝置(無線或有線)、網路設備、虛擬化裝置、儲存控制器、網路控制器、路由器、等等。
控制器691a、691b、...691n可包含系統控制器、週邊控制器、記憶體控制器、集線器控制器、I/O(輸入/輸出)匯流排控制器、視頻控制器、網路控制器、儲存控制 器、通訊控制器的其中之一或更多個系統。舉例而言，儲存控制器根據儲存協定層而控制對儲存器693之資料讀取及寫入。層的儲存協定可為多個已知的儲存協定中的任何協定。依據習知的快取技術，可快取寫至或讀自儲存器693的資料。網路控制器可包含一或更多個協定層以便在網路697上對遠端裝置傳送及接收網路封包。網路697可包括區域網路(LAN)、網際網路、廣域網路(WAN)、儲存區域網路(SAN)、等等。實施例可被配置成透過無線網路或連接而發送及接收資料。在某些實施例中，網路控制器及各種協定層採用經過未屏蔽之雙絞線電纜的乙太網路協定、符記環協定、光纖通道協定、等等、或是任何其它適當的網路通訊協定。
此處使用之例如「第一」、「第二」等詞不一定代表任何特定的次序、數量、或重要性，但是用以區別一個元件與另一個元件。例如「頂部」、「底部」、「上」、「下」等詞僅作為說明之用且不被解釋為限定。可以用各種位置及方向來製造、使用及含有實施例。
在前述的實施方式中，為了使揭示流暢而將各種特點分組在一起。本揭示的方法不應解釋為所主張的發明實施例要求比各申請專利範圍請求項所記載的特點還多的特徵。相反地，後附的申請專利範圍反應發明標的在於比單一揭示的實施例的所有特點更少的特點。因此，後附的申請專利範圍於此一併列入實施方式，以各申請專利範圍基於它自己分別的較佳實施例。
雖然在上述及附圖中說明某些舉例說明的實施例，但是，要瞭解這些實施例僅為說明之用而非限定性，並且，由於具有此技藝中一般技術者瞭解修改，所以，實施例不限於所示及說明之特定結構及配置。
2‧‧‧基板
4‧‧‧晶粒
6‧‧‧矽穿孔
8‧‧‧介電層
10‧‧‧介電層
12‧‧‧介電層
14‧‧‧介電層
16‧‧‧介電層
18‧‧‧第一表面
20‧‧‧第二表面
22‧‧‧接合墊
24‧‧‧接合墊
26‧‧‧穿孔
28‧‧‧佈線層
30‧‧‧穿孔
32‧‧‧佈線層
34‧‧‧佈線層
35‧‧‧黏著劑
36‧‧‧穿孔
38‧‧‧佈線層
40‧‧‧穿孔
42‧‧‧凸塊
44‧‧‧凸塊
48‧‧‧組件
50‧‧‧結構
52‧‧‧暫時的核心
102‧‧‧基板
104‧‧‧矽穿孔晶粒
106‧‧‧穿孔
108‧‧‧介電層
110‧‧‧介電層
112‧‧‧介電層
114‧‧‧介電層
116‧‧‧介電層
118‧‧‧第一表面
120‧‧‧第二表面
122‧‧‧接合墊
124‧‧‧接合墊
126‧‧‧穿孔
127‧‧‧核心層
128‧‧‧佈線層
129‧‧‧電路徑
130‧‧‧穿孔
132‧‧‧佈線層
134‧‧‧佈線層
136‧‧‧穿孔
138‧‧‧佈線層
140‧‧‧穿孔
204‧‧‧矽穿孔晶粒
206‧‧‧穿孔
208‧‧‧介電層
210‧‧‧介電層
212‧‧‧介電層
214‧‧‧介電層
216‧‧‧介電層
220‧‧‧墊
226‧‧‧穿孔
227‧‧‧核心
228‧‧‧佈線層
230‧‧‧穿孔
232‧‧‧佈線層
234‧‧‧佈線層
236‧‧‧穿孔
238‧‧‧佈線層
240‧‧‧穿孔
304‧‧‧矽穿孔晶粒
308‧‧‧介電層
310‧‧‧介電層
312‧‧‧介電層
314‧‧‧介電層
316‧‧‧介電層
502‧‧‧多層基板
504‧‧‧矽穿孔晶粒
542‧‧‧銲材凸塊
544‧‧‧銲材凸塊
548‧‧‧晶粒結構
550‧‧‧電路板
600‧‧‧系統
683‧‧‧中央處理單元
685‧‧‧基板
687‧‧‧印刷電路板
689a‧‧‧記憶體
689b‧‧‧記憶體
691a‧‧‧控制器
693‧‧‧儲存器
695‧‧‧顯示器
697‧‧‧網路
將參考未依比例繪製的附圖，以舉例方式說明實施例。
圖1顯示依據某些實施例之嵌入於基板中的TSV晶粒的視圖。
圖2顯示依據某些實施例之用於形成含有嵌入式TSV晶粒的形底之無核心基板形成製程期間的視圖。
圖3顯示依據某些實施例之嵌入於基板中的TSV晶粒的視圖，包含顯示晶粒與晶粒位於其中之基板的介電層之間的介面的放大部份。
圖4顯示依據某些實施例之位於核心上及嵌入於基板中的TSV晶粒的視圖。
圖5顯示依據某些實施例之嵌入於基板中的核心中的TSV晶粒的視圖。
圖6顯示依據某些實施例之均嵌入於基板中的第一TSV晶粒與第二TSV晶粒的視圖。
圖7顯示依據某些實施例之用於形成包含嵌入式TSV晶粒之電子組成件的操作流程圖。
圖8顯示依據某些實施例之包含具有嵌入式TSV晶粒 之基板及位於基板上的記憶體之組成件的實例。
圖9顯示可見到實施例的應用之電子系統配置。
2‧‧‧基板
4‧‧‧晶粒
6‧‧‧矽穿孔
8‧‧‧介電層
10‧‧‧介電層
12‧‧‧介電層
14‧‧‧介電層
16‧‧‧介電層
18‧‧‧第一表面
20‧‧‧第二表面
22‧‧‧接合墊
24‧‧‧接合墊
26‧‧‧穿孔
28‧‧‧佈線層
30‧‧‧穿孔
32‧‧‧佈線層
34‧‧‧佈線層
36‧‧‧穿孔
38‧‧‧佈線層
40‧‧‧穿孔
42‧‧‧凸塊
44‧‧‧凸塊
48‧‧‧組件
50‧‧‧結構

Claims (18)

  1. 一種電子裝置，包括：多層基板，包括多個介電層及金屬層，該多層基板包含第一側及第二側；半導體晶粒，係嵌入於該基板中，該晶粒包含從該晶粒的第一端延伸至第二端的多個半導體穿孔；該多個半導體穿孔，係電耦合至由該多個金屬層所界定的多個導電路徑，該多個導電路徑包含從該晶粒的該第一端延伸至該基板的該第一側上的多個墊之路徑、以及從該晶粒的該第二端延伸至該基板的該第二側上的多個墊之路徑；額外的半導體晶粒，係嵌入於該基板中，該額外的晶粒包含從該額外的晶粒的第一端延伸至第二端的多個半導體穿孔；該額外的晶粒的多個半導體穿孔，係電耦合至由該多個金屬層所界定之額外的多個導電路徑，該多個導電路徑包含從該額外晶粒之該第一端延伸至該基板之該第一側上之額外墊的路徑、以及從該額外晶粒的該第二端延伸至該基板之該第二側上之額外墊的路徑；其中，在該晶粒中的該多個半導體穿孔具有小於該基板的該第一側上的該等墊之間距的間距，其中，在該晶粒中的該多個半導體穿孔具有小於該基板的該第二側上的該等墊之間距的間距，其中，該額外晶粒中之該等半導體穿孔具有小於該基 板之該第一側上的該等額外墊之間距的間距，並且其中，該額外半導體晶粒中之該半導體穿孔具有小於該基板之該第二側上的該等額外墊之間距的間距。
  2. 如申請專利範圍第1項之電子裝置，其中，該晶粒係設置成使得該多個介電層及金屬層係位於該晶粒與該基板的該第一側之間。
  3. 如申請專利範圍第1項之電子裝置，其中，該基板包括無核心基板。
  4. 如申請專利範圍第1項之電子裝置，其中，該晶粒係位於介電層之內。
  5. 如申請專利範圍第1項之電子裝置，其中，該晶粒包含被介電層所圍繞的外側邊緣。
  6. 如申請專利範圍第5項之電子裝置，又包括位於該晶粒的該外側邊緣與該介電層之間的黏著劑。
  7. 如申請專利範圍第1項之電子裝置，其中，該基板包含核心，該核心包括不同於該介電及金屬層之成分的成分。
  8. 如申請專利範圍第1項之電子裝置，又包括嵌入於該基板中的額外晶粒，該額外晶粒包含多個半導體穿孔。
  9. 如申請專利範圍第1項之電子裝置，其中，該基板之該第二表面上的該等墊的該間距係大於該基板之該第一表面上的該等墊的該間距。
  10. 如申請專利範圍第1項之電子裝置，其中，該半導體晶粒包括矽。
  11. 一種電子裝置，包括：多層基板，包括多個介電層及金屬層，該多層基板包含第一側及第二側；半導體晶粒，係嵌入於該基板中，該晶粒包含從該晶粒的第一端延伸至第二端的多個半導體穿孔；該多個半導體穿孔，係電耦合至由該金屬層所界定的多個導電路徑，該多個導電路徑包含從該半導體晶粒的該第一端延伸至該基板之該第一側上的多個墊的路徑、以及從該半導體晶粒的該第二端延伸至該基板之該第二側上的多個墊的路徑；其中，在該半導體晶粒中的該多個半導體穿孔具有小於該基板的該第一側上之該等墊的間距之間距；組件，係耦合至該基板的該第一側上的該等墊，該組件包含半導體晶粒；及電路板，係耦合至該基板的該第二側上的該等墊；其中，該基板係位於該組件與該電路板之間，其中，該組件包括記憶體結構。
  12. 如申請專利範圍第11項之電子裝置，其中，該組件包括多個半導體晶粒結構。
  13. 如申請專利範圍第11項之電子裝置，其中，該半導體晶粒包括矽。
  14. 一種電子裝置製造方法，包括：將包含多個半導體穿孔的半導體晶粒嵌入於多層基板內，該多個半導體穿孔具有間距；以及 形成從該多個半導體穿孔延伸至該基板的第一及第二表面上的多個墊之佈線路徑，其中，該基板的該第一表面上的該等墊具有形成為大於該多個半導體穿孔之間距的間距，且其中，該基板的該第二表面上的該等墊具有形成為大於該多個半導體穿孔之間距的間距。
  15. 如申請專利範圍第14項之方法，其中，將半導體晶粒嵌入於多層基板內包含將介電層定位成延伸於該晶粒之周邊的周圍。
  16. 如申請專利範圍第15項之方法，又包括將黏著劑定位於該半導體晶粒的外側邊緣與該介電層之間。
  17. 如申請專利範圍第14項之方法，又包括將組件耦合至該多層基板的該第一表面上。
  18. 如申請專利範圍第17項之方法，其中，該組件包括記憶體組件。
TW101146178A 2011-12-27 2012-12-07 電子裝置及電子裝置製造方法 TWI506745B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2011006291A MY165677A (en) 2011-12-27 2011-12-27 Embedded through-silicon-via

Publications (2)

Publication Number Publication Date
TW201342550A TW201342550A (zh) 2013-10-16
TWI506745B true TWI506745B (zh) 2015-11-01

Family

ID=48698594

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101146178A TWI506745B (zh) 2011-12-27 2012-12-07 電子裝置及電子裝置製造方法

Country Status (3)

Country Link
MY (1) MY165677A (zh)
TW (1) TWI506745B (zh)
WO (1) WO2013101849A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170077389A1 (en) * 2014-06-16 2017-03-16 Intel Corporation Embedded memory in interconnect stack on silicon die
KR20160090705A (ko) * 2015-01-22 2016-08-01 에스케이하이닉스 주식회사 패키지 기판 및 이를 이용한 반도체 패키지
CN111682003B (zh) 2019-03-11 2024-04-19 奥特斯奥地利科技与系统技术有限公司 包括具有竖向贯通连接件的部件的部件承载件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200843061A (en) * 2007-04-27 2008-11-01 Taiwan Semiconductor Mfg Semiconductor package structure
TW200847351A (en) * 2007-05-25 2008-12-01 Nepes Corp Wafer level system in package and fabrication method thereof
KR20100030151A (ko) * 2008-09-09 2010-03-18 삼성전기주식회사 전자소자 내장 인쇄회로기판
TW201110309A (en) * 2009-04-06 2011-03-16 Wen-Kun Yang Stacking package structure with chip embedded inside and die having through silicon via and method of the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388207B1 (en) * 2000-12-29 2002-05-14 Intel Corporation Electronic assembly with trench structures and methods of manufacture
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US7049208B2 (en) * 2004-10-11 2006-05-23 Intel Corporation Method of manufacturing of thin based substrate
KR100872583B1 (ko) * 2007-07-12 2008-12-08 삼성전기주식회사 인쇄회로기판 제조방법 및 인터포저 기판
US20100155931A1 (en) * 2008-12-22 2010-06-24 Qualcomm Incorporated Embedded Through Silicon Stack 3-D Die In A Package Substrate
KR101084910B1 (ko) * 2009-10-12 2011-11-17 삼성전기주식회사 전자부품 내장형 인쇄회로기판 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200843061A (en) * 2007-04-27 2008-11-01 Taiwan Semiconductor Mfg Semiconductor package structure
TW200847351A (en) * 2007-05-25 2008-12-01 Nepes Corp Wafer level system in package and fabrication method thereof
KR20100030151A (ko) * 2008-09-09 2010-03-18 삼성전기주식회사 전자소자 내장 인쇄회로기판
TW201110309A (en) * 2009-04-06 2011-03-16 Wen-Kun Yang Stacking package structure with chip embedded inside and die having through silicon via and method of the same

Also Published As

Publication number Publication date
TW201342550A (zh) 2013-10-16
WO2013101849A1 (en) 2013-07-04
MY165677A (en) 2018-04-18

Similar Documents

Publication Publication Date Title
US9748177B2 (en) Embedded structures for package-on-package architecture
JP4581768B2 (ja) 半導体装置の製造方法
US9391025B2 (en) Reliable microstrip routing for electronics components
US10658279B2 (en) High density package interconnects
TWI418003B (zh) 嵌埋電子元件之封裝結構及其製法
US8127979B1 (en) Electrolytic depositon and via filling in coreless substrate processing
TWI514486B (zh) 致能無凸塊增層式（ｂｂｕｌ）封裝體上之封裝體疊加（ｐｏｐ）墊表面修整層之技術
CN106057769B (zh) 用于交替的封装功能的微电子衬底
US20120049366A1 (en) Package structure having through-silicon-via (tsv) chip embedded therein and fabrication method thereof
TWI723436B (zh) 包括核心層的嵌入式跡線襯底（ets）中的高密度互連
CN104051379A (zh) 具有超薄介电层的无焊内建层（bbul）半导体封装
JP2018523919A (ja) 複数のダイを含むパッケージオンパッケージ（ｐｏｐ）構造
JP2005294451A (ja) 半導体集積回路の製造方法および半導体集積回路ならびに半導体集積回路装置
TWI533424B (zh) 封裝載板
TWI506745B (zh) 電子裝置及電子裝置製造方法
US20120161312A1 (en) Non-solder metal bumps to reduce package height
TWI354338B (en) Carrier structure for semiconductor component and
US20120077054A1 (en) Electrolytic gold or gold palladium surface finish application in coreless substrate processing
CN102751248A (zh) 嵌埋穿孔芯片的封装结构及其制法
JP2008305952A (ja) 高密度細線実装構造及びその製造方法
EP2120262A1 (en) Structure of packaging substrate and method for making the same