JP2012216812A - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP2012216812A
JP2012216812A JP2012071513A JP2012071513A JP2012216812A JP 2012216812 A JP2012216812 A JP 2012216812A JP 2012071513 A JP2012071513 A JP 2012071513A JP 2012071513 A JP2012071513 A JP 2012071513A JP 2012216812 A JP2012216812 A JP 2012216812A
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Prior art keywords
film
silicon oxide
semiconductor substrate
semiconductor device
oxide film
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Japanese (ja)
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JP2012216812A5 (https=
Inventor
Yuta Nishioka
裕太 西岡
Satoshi Sugiyama
智 杉山
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Micron Memory Japan Ltd
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Elpida Memory Inc
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Priority to JP2012071513A priority Critical patent/JP2012216812A/ja
Publication of JP2012216812A publication Critical patent/JP2012216812A/ja
Publication of JP2012216812A5 publication Critical patent/JP2012216812A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2012071513A 2011-03-31 2012-03-27 半導体装置及びその製造方法 Withdrawn JP2012216812A (ja)

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JP2012071513A JP2012216812A (ja) 2011-03-31 2012-03-27 半導体装置及びその製造方法

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JP2011079612 2011-03-31
JP2011079612 2011-03-31
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JP2012216812A5 JP2012216812A5 (https=) 2015-05-07

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016171256A (ja) * 2015-03-13 2016-09-23 株式会社東芝 半導体装置、および、半導体装置の製造方法
KR20170030478A (ko) * 2014-07-08 2017-03-17 인텔 코포레이션 스루-바디 비아 라이너 퇴적
US9601411B2 (en) 2014-04-25 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure

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JP5581106B2 (ja) * 2009-04-27 2014-08-27 株式会社半導体エネルギー研究所 半導体装置の作製方法
US20130270712A1 (en) * 2012-04-16 2013-10-17 Hsin-Yu Chen Through silicon via structure and method of fabricating the same
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US8772126B2 (en) * 2012-08-10 2014-07-08 Infineon Technologies Ag Method of manufacturing a semiconductor device including grinding from a back surface and semiconductor device
DE102012219769B4 (de) * 2012-10-29 2020-06-25 Robert Bosch Gmbh Verfahren zum Herstellen einer elektrischen Durchkontaktierung in einem Substrat
US10270003B2 (en) * 2012-12-04 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for CMOS sensor packaging
JP5982312B2 (ja) * 2013-03-22 2016-08-31 株式会社東芝 半導体装置
KR20140131786A (ko) * 2013-05-06 2014-11-14 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US9252047B2 (en) * 2014-01-23 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd Interconnect arrangement with stress-reducing structure and method of fabricating the same
US10147906B2 (en) * 2014-02-06 2018-12-04 Emagin Corporation High efficacy seal for organic light emitting diode displays
US9443872B2 (en) 2014-03-07 2016-09-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10315915B2 (en) * 2015-07-02 2019-06-11 Kionix, Inc. Electronic systems with through-substrate interconnects and MEMS device
JP6917700B2 (ja) 2015-12-02 2021-08-11 株式会社半導体エネルギー研究所 半導体装置
US9875934B2 (en) * 2016-02-26 2018-01-23 Infineon Technologies Ag Semiconductor device and a method for forming a semiconductor device
EP4117029B1 (en) 2021-05-08 2024-01-24 Changxin Memory Technologies, Inc. Semiconductor structure and preparation method therefor

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JPH09260484A (ja) * 1996-03-25 1997-10-03 Toshiba Corp 半導体装置の製造方法
KR100230392B1 (ko) * 1996-12-05 1999-11-15 윤종용 반도체 소자의 콘택 플러그 형성방법
JP3676185B2 (ja) * 2000-04-14 2005-07-27 シャープ株式会社 半導体装置
JP2002313757A (ja) * 2001-04-17 2002-10-25 Hitachi Ltd 半導体集積回路装置の製造方法
US7470584B2 (en) * 2005-01-21 2008-12-30 Taiwan Semiconductor Manufacturing Co., Ltd. TEOS deposition method
JP5563186B2 (ja) 2007-03-30 2014-07-30 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP5656341B2 (ja) 2007-10-29 2015-01-21 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置およびその製造方法
JP5596919B2 (ja) * 2008-11-26 2014-09-24 キヤノン株式会社 半導体装置の製造方法
JP2011228419A (ja) * 2010-04-19 2011-11-10 Renesas Electronics Corp 半導体集積回路装置および半導体集積回路装置の製造方法
US20120015113A1 (en) * 2010-07-13 2012-01-19 Applied Materials, Inc. Methods for forming low stress dielectric films
US8525343B2 (en) * 2010-09-28 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Device with through-silicon via (TSV) and method of forming the same
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601411B2 (en) 2014-04-25 2017-03-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
KR101791730B1 (ko) * 2014-04-25 2017-10-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 구조 및 그 제조 방법
KR20170030478A (ko) * 2014-07-08 2017-03-17 인텔 코포레이션 스루-바디 비아 라이너 퇴적
JP2017521858A (ja) * 2014-07-08 2017-08-03 インテル・コーポレーション 本体貫通ビアライナの堆積
KR102327422B1 (ko) 2014-07-08 2021-11-17 인텔 코포레이션 스루-바디 비아 라이너 퇴적
JP2016171256A (ja) * 2015-03-13 2016-09-23 株式会社東芝 半導体装置、および、半導体装置の製造方法

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