JP2012134472A - 半導体装置およびその作製方法 - Google Patents
半導体装置およびその作製方法 Download PDFInfo
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- JP2012134472A JP2012134472A JP2011259843A JP2011259843A JP2012134472A JP 2012134472 A JP2012134472 A JP 2012134472A JP 2011259843 A JP2011259843 A JP 2011259843A JP 2011259843 A JP2011259843 A JP 2011259843A JP 2012134472 A JP2012134472 A JP 2012134472A
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- oxide semiconductor
- layer
- semiconductor layer
- insulating layer
- nitrogen
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
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Classifications
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02513—Microstructure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
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- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract
【解決手段】酸化物半導体層と該酸化物半導体層と接する絶縁膜(ゲート絶縁層)との界面状態を良好とするために、酸化物半導体層の界面近傍に窒素を添加する。具体的には酸化物半導体層に窒素の濃度勾配を作り、窒素を多く含む領域をゲート絶縁層との界面に設ける。この窒素の添加によって、酸化物半導体層の界面近傍に結晶性の高い領域を形成でき、安定した界面状態を得ることができる。
【選択図】図1
Description
本実施の形態では、酸化物半導体層と当該酸化物半導体層の一部と接する絶縁層との界面状態が良好なトップゲート型トランジスタの作製方法の一例を図1を用いて説明する。
本実施の形態では、酸化物半導体層と当該酸化物半導体層の一部と接する絶縁層との界面状態が良好なボトムゲート型トランジスタの作製方法の一例について図2を用いて説明する。
本実施の形態では、酸化物半導体層と当該酸化物半導体層の一部と接する絶縁層との界面状態が良好なボトムゲート型トランジスタの作製方法の一例について図8を用いて説明する。
本実施の形態では、同一基板上に少なくとも駆動回路の一部と、画素部に配置するトランジスタを有する表示装置を作製する例について以下に説明する。
本明細書に開示する半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ等のカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。上記実施の形態で説明した表示装置を具備する電子機器の例について説明する。
第1の結晶型および第2の結晶型である六方晶系の結晶構造について説明する。
次に、窒素濃度の高い酸化物半導体膜について説明する。窒素濃度の高い酸化物半導体膜はc軸配向し、且つウルツ鉱型の結晶を含む。特に、窒素濃度の高い酸化物半導体膜は酸化物半導体膜に比べて結晶性が高く、結晶化し易い材料を用いる。
101 下地絶縁層
102 酸化物半導体層
102a 酸化物半導体層
102b 酸化物半導体層
103 ソース電極層
104 ドレイン電極層
105 ゲート絶縁層
106 ゲート電極層
111 トランジスタ
112 界面近傍領域
200 基板
201 ゲート電極層
202 ゲート絶縁層
202a ゲート絶縁層
202b ゲート絶縁層
203 酸化物半導体層
203a 酸化物半導体層
203b 酸化物半導体層
203c 酸化物半導体層
203d 酸化物半導体層
204 ソース電極層
205 ドレイン電極層
206 保護絶縁層
207 酸化物半導体層
211 トランジスタ
212 界面近傍領域
213 トランジスタ
214 界面近傍領域
300 基板
301 ゲート電極層
302 ゲート絶縁層
302a ゲート絶縁層
302b ゲート絶縁層
303 酸化物半導体層
303a 酸化物半導体層
303b 酸化物半導体層
303c 酸化物半導体層
303d 酸化物半導体層
304 ソース電極層
305 ドレイン電極層
306 保護絶縁層
313 トランジスタ
314 界面近傍領域
400 基板
402 絶縁表面
402a 絶縁表面
402b 絶縁表面
430 半導体膜
431 酸化物半導体膜
432 酸化物半導体膜
602 ゲート配線
603 ゲート配線
616 ドレイン電極層
628 トランジスタ
629 トランジスタ
650 ℃以上
651 液晶素子
652 液晶素子
690 容量配線
3001 本体
3002 筐体
3003a 表示部
3003b 表示部
3004 キーボードボタン
5001 表示部
5002 ヒンジ
5003 表示パネル
5004 操作ボタン
5005 携帯電話機
5006 タッチ入力ボタン
5300 基板
5301 画素部
5302 走査線駆動回路
5303 走査線駆動回路
5304 信号線駆動回路
6400 画素
6401 スイッチング用トランジスタ
6402 駆動用トランジスタ
6403 容量素子
6404 発光素子
6405 信号線
6406 走査線
6407 電源線
6408 共通電極
7001 発光素子駆動用トランジスタ
7002 発光素子
7003 第1の電極
7004 EL層
7005 電極
7009 隔壁
7010 基板
7011 発光素子駆動用トランジスタ
7012 発光素子
7014 EL層
7015 電極
7016 遮蔽膜
7017 第1の電極
7019 隔壁
7020 基板
7021 発光素子駆動用トランジスタ
7022 発光素子
7024 EL層
7025 電極
7027 第1の電極
7029 隔壁
7030 ゲート絶縁層
7031 ゲート絶縁層
7032 絶縁層
7033 カラーフィルタ層
7034 オーバーコート層
7035 保護絶縁層
7040 ゲート絶縁層
7041 ゲート絶縁層
7042 絶縁層
7052 保護絶縁層
7053 平坦化絶縁層
7055 絶縁層
9600 テレビジョン装置
9601 筐体
9602 記憶媒体再生録画部
9603 表示部
9604 外部接続端子
9605 スタンド
9606 外部メモリ
Claims (10)
- ゲート電極層と、
該ゲート電極層と接する第1の絶縁層と、
該第1の絶縁層に接する酸化物半導体層と、
該酸化物半導体層に接する第2の絶縁層とを有し、
前記酸化物半導体層は、前記第1の絶縁層との界面に窒素濃度のピークを有し、
前記第1の絶縁層は、窒素を含み、その窒素濃度のピークは酸化物半導体層との界面であることを特徴とする半導体装置。 - 請求項1において、前記酸化物半導体層は、前記第1の絶縁層に近いほど高くなる窒素濃度の濃度勾配を有し、且つ、前記第2の絶縁層に近いほど高くなる酸素濃度の濃度勾配を有することを特徴とする半導体装置。
- 請求項1または請求項2において、前記酸化物半導体層のうち、前記第1の絶縁層との界面近傍の領域は他の領域に比べて結晶性が高いことを特徴とする半導体装置。
- 請求項1乃至3のいずれか一において、前記第1の絶縁層と前記酸化物半導体層の界面近傍の窒素濃度は、5×1019/cm3以上7原子%未満であることを特徴とする半導体装置。
- 請求項1乃至4のいずれか一において、前記第2の絶縁層と前記酸化物半導体層の界面近傍の窒素濃度は、1×1017/cm3以上5×1019/cm3未満であることを特徴とする半導体装置。
- 請求項1乃至5のいずれか一において、前記酸化物半導体層は、前記第2の絶縁層との界面に酸素濃度のピークを有し、
前記第2の絶縁層は、酸素を含み、その酸素濃度のピークは酸化物半導体層との界面であることを特徴とする半導体装置。 - 酸化物半導体層を形成し、
前記酸化物半導体層上にソース電極層及びドレイン電極層を形成し、
減圧下で加熱を行った後、N2またはN2Oガスを用いてプラズマ処理を行って窒素を酸化物半導体層の一部に添加し、
前記プラズマ処理を行った後、大気に触れることなく、前記酸化物半導体層、ソース電極層、及びドレイン電極層上にゲート絶縁層を形成し、
前記ゲート絶縁層を介して前記酸化物半導体層の窒素が添加された領域と重なる位置にゲート電極層を形成することを特徴とする半導体装置の作製方法。 - ゲート電極層を形成し、
前記ゲート電極層上にゲート絶縁層を形成し、
N2またはN2Oガスを用いてプラズマ処理を行って窒素をゲート絶縁層の一部に添加し、
前記ゲート絶縁層を介して前記ゲート電極層と重なる位置に酸化物半導体層を形成し、
前記酸化物半導体層上にソース電極層及びドレイン電極層を形成し、
減圧下で加熱を行った後、酸素プラズマ処理を行って酸素を酸化物半導体層の一部に添加し、
酸素を含む雰囲気下でスパッタ法により、前記酸化物半導体層、ソース電極層、及びドレイン電極層を覆う絶縁層を形成することを特徴とする半導体装置の作製方法。 - 請求項7または請求項8において、N2またはN2Oガスを用いる前記プラズマ処理は、スパッタ装置で行うことを特徴とする半導体装置の作製方法。
- 請求項7または請求項8において、N2またはN2Oガスを用いる前記プラズマ処理は、プラズマCVD装置で行うことを特徴とする半導体装置の作製方法。
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KR20120059414A (ko) | 2012-06-08 |
TWI642196B (zh) | 2018-11-21 |
US20140353663A1 (en) | 2014-12-04 |
US9029937B2 (en) | 2015-05-12 |
JP5964037B2 (ja) | 2016-08-03 |
TW201244108A (en) | 2012-11-01 |
KR101923427B1 (ko) | 2019-02-22 |
JP2016197736A (ja) | 2016-11-24 |
JP6267281B2 (ja) | 2018-01-24 |
US20120132906A1 (en) | 2012-05-31 |
US8816425B2 (en) | 2014-08-26 |
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