JP2011510428A5 - - Google Patents

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Publication number
JP2011510428A5
JP2011510428A5 JP2010543040A JP2010543040A JP2011510428A5 JP 2011510428 A5 JP2011510428 A5 JP 2011510428A5 JP 2010543040 A JP2010543040 A JP 2010543040A JP 2010543040 A JP2010543040 A JP 2010543040A JP 2011510428 A5 JP2011510428 A5 JP 2011510428A5
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Japan
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storage unit
data
page
programming
index
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JP2010543040A
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Japanese (ja)
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JP2011510428A (ja
JP5351176B2 (ja
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Priority claimed from KR1020080006501A external-priority patent/KR101368694B1/ko
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JP2010543040A 2008-01-22 2008-08-04 メモリプログラミング装置および方法 Active JP5351176B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR1020080006501A KR101368694B1 (ko) 2008-01-22 2008-01-22 메모리 프로그래밍 장치 및 방법
KR10-2008-0006501 2008-01-22
PCT/KR2008/004530 WO2009093786A1 (en) 2008-01-22 2008-08-04 Apparatus and method of memory programming

Publications (3)

Publication Number Publication Date
JP2011510428A JP2011510428A (ja) 2011-03-31
JP2011510428A5 true JP2011510428A5 (enExample) 2013-06-27
JP5351176B2 JP5351176B2 (ja) 2013-11-27

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Family Applications (1)

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JP2010543040A Active JP5351176B2 (ja) 2008-01-22 2008-08-04 メモリプログラミング装置および方法

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US (2) US7738293B2 (enExample)
JP (1) JP5351176B2 (enExample)
KR (1) KR101368694B1 (enExample)
WO (1) WO2009093786A1 (enExample)

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US8767459B1 (en) * 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
JP2012048791A (ja) 2010-08-27 2012-03-08 Toshiba Corp 多値不揮発性半導体メモリシステム
KR101200125B1 (ko) * 2010-12-20 2012-11-12 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR101320686B1 (ko) * 2011-11-17 2013-10-18 한국과학기술원 메모리의 오류 정정 장치 및 방법
KR20140072637A (ko) * 2012-12-05 2014-06-13 삼성전자주식회사 비휘발성 메모리 장치 및 메모리 컨트롤러의 동작 방법
US9190159B2 (en) 2013-03-15 2015-11-17 Kabushiki Kaisha Toshiba Semiconductor memory device
JP6262063B2 (ja) 2014-03-18 2018-01-17 東芝メモリ株式会社 不揮発性メモリおよび書き込み方法
US9607703B2 (en) 2014-09-08 2017-03-28 Kabushiki Kaisha Toshiba Memory system
KR102128406B1 (ko) 2014-09-26 2020-07-10 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
KR102298607B1 (ko) * 2015-02-17 2021-09-06 삼성전자주식회사 저항성 메모리 시스템 및 저항성 메모리 시스템의 동작 방법
US9224492B1 (en) * 2015-02-17 2015-12-29 Phison Electronics Corp. Memory management method, memory storage device and memory controlling circuit unit
US9679652B2 (en) * 2015-05-04 2017-06-13 Phison Electronics Corp. Threshold based multi-level cell programming for reliability improvement
CN105700960B (zh) * 2016-01-13 2018-01-19 广东欧珀移动通信有限公司 一种网络定位进程的启停方法、装置及移动终端
KR20180131023A (ko) * 2017-05-31 2018-12-10 에스케이하이닉스 주식회사 반도체 메모리 시스템 및 그것의 동작 방법
US11568938B2 (en) * 2020-11-03 2023-01-31 Western Digital Technologies, Inc. QLC data programming
US11861195B2 (en) 2021-03-15 2024-01-02 Western Digital Technologies, Inc. TLC data programming with hybrid parity

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JP5367210B2 (ja) * 2006-01-20 2013-12-11 株式会社東芝 半導体記憶装置
JP2008010046A (ja) * 2006-06-28 2008-01-17 Toshiba Corp 不揮発性半導体記憶装置
JP2009104729A (ja) * 2007-10-24 2009-05-14 Toshiba Corp 不揮発性半導体記憶装置

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