KR101368694B1 - 메모리 프로그래밍 장치 및 방법 - Google Patents

메모리 프로그래밍 장치 및 방법 Download PDF

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Publication number
KR101368694B1
KR101368694B1 KR1020080006501A KR20080006501A KR101368694B1 KR 101368694 B1 KR101368694 B1 KR 101368694B1 KR 1020080006501 A KR1020080006501 A KR 1020080006501A KR 20080006501 A KR20080006501 A KR 20080006501A KR 101368694 B1 KR101368694 B1 KR 101368694B1
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South Korea
Prior art keywords
storage unit
data
programming
index
unit
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English (en)
Korean (ko)
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KR20090080634A (ko
Inventor
조경래
공준진
송승환
박윤동
김종한
김재홍
이영환
은희석
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삼성전자주식회사
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Priority to KR1020080006501A priority Critical patent/KR101368694B1/ko
Priority to US12/213,944 priority patent/US7738293B2/en
Priority to PCT/KR2008/004530 priority patent/WO2009093786A1/en
Priority to JP2010543040A priority patent/JP5351176B2/ja
Publication of KR20090080634A publication Critical patent/KR20090080634A/ko
Priority to US12/801,532 priority patent/US8279668B2/en
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Publication of KR101368694B1 publication Critical patent/KR101368694B1/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
KR1020080006501A 2008-01-22 2008-01-22 메모리 프로그래밍 장치 및 방법 Active KR101368694B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020080006501A KR101368694B1 (ko) 2008-01-22 2008-01-22 메모리 프로그래밍 장치 및 방법
US12/213,944 US7738293B2 (en) 2008-01-22 2008-06-26 Apparatus and method of memory programming
PCT/KR2008/004530 WO2009093786A1 (en) 2008-01-22 2008-08-04 Apparatus and method of memory programming
JP2010543040A JP5351176B2 (ja) 2008-01-22 2008-08-04 メモリプログラミング装置および方法
US12/801,532 US8279668B2 (en) 2008-01-22 2010-06-14 Apparatus and method of memory programming

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080006501A KR101368694B1 (ko) 2008-01-22 2008-01-22 메모리 프로그래밍 장치 및 방법

Publications (2)

Publication Number Publication Date
KR20090080634A KR20090080634A (ko) 2009-07-27
KR101368694B1 true KR101368694B1 (ko) 2014-03-03

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KR1020080006501A Active KR101368694B1 (ko) 2008-01-22 2008-01-22 메모리 프로그래밍 장치 및 방법

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Country Link
US (2) US7738293B2 (enExample)
JP (1) JP5351176B2 (enExample)
KR (1) KR101368694B1 (enExample)
WO (1) WO2009093786A1 (enExample)

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US8645794B1 (en) * 2010-07-31 2014-02-04 Apple Inc. Data storage in analog memory cells using a non-integer number of bits per cell
JP2012048791A (ja) * 2010-08-27 2012-03-08 Toshiba Corp 多値不揮発性半導体メモリシステム
KR101200125B1 (ko) * 2010-12-20 2012-11-12 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그 동작 방법
KR101320686B1 (ko) * 2011-11-17 2013-10-18 한국과학기술원 메모리의 오류 정정 장치 및 방법
KR20140072637A (ko) * 2012-12-05 2014-06-13 삼성전자주식회사 비휘발성 메모리 장치 및 메모리 컨트롤러의 동작 방법
US9190159B2 (en) 2013-03-15 2015-11-17 Kabushiki Kaisha Toshiba Semiconductor memory device
JP6262063B2 (ja) 2014-03-18 2018-01-17 東芝メモリ株式会社 不揮発性メモリおよび書き込み方法
US9607703B2 (en) 2014-09-08 2017-03-28 Kabushiki Kaisha Toshiba Memory system
KR102128406B1 (ko) 2014-09-26 2020-07-10 삼성전자주식회사 스토리지 장치 및 스토리지 장치의 동작 방법
US9224492B1 (en) * 2015-02-17 2015-12-29 Phison Electronics Corp. Memory management method, memory storage device and memory controlling circuit unit
KR102298607B1 (ko) * 2015-02-17 2021-09-06 삼성전자주식회사 저항성 메모리 시스템 및 저항성 메모리 시스템의 동작 방법
US9679652B2 (en) * 2015-05-04 2017-06-13 Phison Electronics Corp. Threshold based multi-level cell programming for reliability improvement
CN105700960B (zh) * 2016-01-13 2018-01-19 广东欧珀移动通信有限公司 一种网络定位进程的启停方法、装置及移动终端
KR20180131023A (ko) * 2017-05-31 2018-12-10 에스케이하이닉스 주식회사 반도체 메모리 시스템 및 그것의 동작 방법
US11568938B2 (en) * 2020-11-03 2023-01-31 Western Digital Technologies, Inc. QLC data programming
US11861195B2 (en) 2021-03-15 2024-01-02 Western Digital Technologies, Inc. TLC data programming with hybrid parity

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US6275961B1 (en) 1996-02-27 2001-08-14 Micron Technology, Inc. Circuit and method for performing tests on memory array cells using external sense amplifier reference current
US6700809B1 (en) 2002-02-01 2004-03-02 Netlogic Microsystems, Inc. Entry relocation in a content addressable memory device
US20040225947A1 (en) 2002-05-20 2004-11-11 Guterman Daniel C. Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
JP2007510253A (ja) 2003-10-29 2007-04-19 サイファン・セミコンダクターズ・リミテッド 不揮発性メモリアレイの読み取り誤り検出のための方法、回路、及びシステム

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US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
JP2000020409A (ja) 1998-07-07 2000-01-21 Seiko Epson Corp 半導体記憶装置
DE69831155D1 (de) * 1998-10-29 2005-09-15 St Microelectronics Srl Verfahren und Vorrichtung zur Prüfung von nichtprogrammierten Speicherzellen in einem Mehrpegelspeicher
US6407944B1 (en) 1998-12-29 2002-06-18 Samsung Electronics Co., Ltd. Method for protecting an over-erasure of redundant memory cells during test for high-density nonvolatile memory semiconductor devices
JP2000222890A (ja) * 1999-01-28 2000-08-11 Matsushita Electric Ind Co Ltd 多ビット同時書込方式と半導体記憶装置
US6111787A (en) * 1999-10-19 2000-08-29 Advanced Micro Devices, Inc. Address transistion detect timing architecture for a simultaneous operation flash memory device
FR2810438B1 (fr) * 2000-06-19 2002-09-06 St Microelectronics Sa Circuit de detection d'usure
JP3833970B2 (ja) * 2002-06-07 2006-10-18 株式会社東芝 不揮発性半導体メモリ
US6781877B2 (en) * 2002-09-06 2004-08-24 Sandisk Corporation Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells
JP3935139B2 (ja) * 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
KR100546348B1 (ko) 2003-07-23 2006-01-26 삼성전자주식회사 플래시 메모리 시스템 및 그 데이터 저장 방법
JP2005100527A (ja) * 2003-09-25 2005-04-14 Matsushita Electric Ind Co Ltd 半導体不揮発性記憶装置
KR100632947B1 (ko) 2004-07-20 2006-10-12 삼성전자주식회사 불 휘발성 메모리 장치 및 그것의 프로그램 방법
JP4261462B2 (ja) * 2004-11-05 2009-04-30 株式会社東芝 不揮発性メモリシステム
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JP4874566B2 (ja) * 2005-04-11 2012-02-15 株式会社東芝 半導体記憶装置
JP4268609B2 (ja) * 2005-04-12 2009-05-27 シャープ株式会社 半導体記憶装置及び電子機器
JP2007042222A (ja) * 2005-08-04 2007-02-15 Renesas Technology Corp 半導体装置
JP4991131B2 (ja) * 2005-08-12 2012-08-01 株式会社東芝 半導体記憶装置
KR101016432B1 (ko) * 2005-11-10 2011-02-21 샌디스크 코포레이션 타이밍 정보를 이용한 리버스 커플링 효과
JP2007157234A (ja) * 2005-12-05 2007-06-21 Matsushita Electric Ind Co Ltd メモリシステム
JP4658812B2 (ja) * 2006-01-13 2011-03-23 シャープ株式会社 不揮発性半導体記憶装置及びその書き込み方法
JP5367210B2 (ja) * 2006-01-20 2013-12-11 株式会社東芝 半導体記憶装置
JP2008010046A (ja) * 2006-06-28 2008-01-17 Toshiba Corp 不揮発性半導体記憶装置
JP2009104729A (ja) * 2007-10-24 2009-05-14 Toshiba Corp 不揮発性半導体記憶装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6275961B1 (en) 1996-02-27 2001-08-14 Micron Technology, Inc. Circuit and method for performing tests on memory array cells using external sense amplifier reference current
US6700809B1 (en) 2002-02-01 2004-03-02 Netlogic Microsystems, Inc. Entry relocation in a content addressable memory device
US20040225947A1 (en) 2002-05-20 2004-11-11 Guterman Daniel C. Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data
JP2007510253A (ja) 2003-10-29 2007-04-19 サイファン・セミコンダクターズ・リミテッド 不揮発性メモリアレイの読み取り誤り検出のための方法、回路、及びシステム

Also Published As

Publication number Publication date
JP2011510428A (ja) 2011-03-31
JP5351176B2 (ja) 2013-11-27
KR20090080634A (ko) 2009-07-27
US20090185417A1 (en) 2009-07-23
US8279668B2 (en) 2012-10-02
US20100254189A1 (en) 2010-10-07
US7738293B2 (en) 2010-06-15
WO2009093786A1 (en) 2009-07-30

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