JP2011146687A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2011146687A JP2011146687A JP2010251092A JP2010251092A JP2011146687A JP 2011146687 A JP2011146687 A JP 2011146687A JP 2010251092 A JP2010251092 A JP 2010251092A JP 2010251092 A JP2010251092 A JP 2010251092A JP 2011146687 A JP2011146687 A JP 2011146687A
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- H01L2924/1203—Rectifying Diode
- H01L2924/12036—PN diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
Abstract
【解決手段】シリコンからなるベース基板B4であって、絶縁分離された複数個のベース半導体領域Bsが上面の表層部の所定領域R1に形成されてなるベース基板B4と、シリコンからなるキャップ基板C4であって、ベース基板B4の所定領域R1において、下面がベース基板B4の上面に貼り合わされるキャップ基板C4とを有してなる半導体装置100において、下面が所定のベース半導体領域Bsに接続し、キャップ基板C4を貫通するようにして、上面がキャップ基板C4の上面まで伸びる、金属40で構成された引き出し電極De1が、当該引き出し電極De1の周りにおいて、キャップ基板C4との間に溝35を有するように形成されてなる半導体装置100とする。
【選択図】図1
Description
酸化シリコン(SiO2)からなる絶縁層32aを形成する。
B4〜B7 ベース基板
C4〜C11 キャップ基板
De1〜De9 引き出し電極
40 金属
35,35a,35b,36,36a,36b,37a〜37c,38 溝
Cs,Cs1〜Cs5,Csa〜Csc 部分領域
Claims (19)
- シリコンからなるベース基板であって、絶縁分離された複数個のベース半導体領域が上面の表層部の所定領域に形成されてなるベース基板と、
前記ベース基板の所定領域において、下面が前記ベース基板の上面に貼り合わされるキャップ基板とを有してなる半導体装置において、
下面が所定の前記ベース半導体領域に接続し、前記キャップ基板を貫通するようにして、上面が前記キャップ基板の上面側まで伸びる、金属で構成された引き出し電極が、当該引き出し電極の周りにおいて、前記キャップ基板との間に溝を有するように形成されてなり、
前記引き出し電極の上面で、外部に電気接続されることを特徴とする半導体装置。 - 前記キャップ基板が、シリコンからなることを特徴とする請求項1に記載の半導体装置。
- 前記キャップ基板が、絶縁分離された複数の部分領域に分割されてなり、
前記引き出し電極が、所定の前記部分領域と、該部分領域の周りに形成された前記金属とで構成されてなることを特徴とする請求項2に記載の半導体装置。 - 前記部分領域の周りに形成された前記金属が、該部分領域の上面を覆うように形成されてなることを特徴とする請求項3に記載の半導体装置。
- 前記キャップ基板が、単結晶シリコンからなることを特徴とする請求項2乃至4のいずれか一項に記載の半導体装置。
- 前記キャップ基板が、絶縁分離された複数の部分領域に分割されてなり、
前記複数の部分領域のうち、所定の部分領域に、IC回路が形成されてなることを特徴とする請求項5に記載の半導体装置。 - 前記引き出し電極の上面が、前記キャップ基板の上面より上にあることを特徴とする請求項1乃至6のいずれか一項に記載に記載の半導体装置。
- 前記引き出し電極の上面が、該引き出し電極の下面より大きな面積であることを特徴とする請求項7に記載に記載の半導体装置。
- 前記溝の下方に、絶縁層が形成され、
前記溝が、前記ベース基板に達していないことを特徴とする請求項1乃至8のいずれか一項に記載の半導体装置。 - 前記ベース基板の所定領域において、貼り合わされた前記ベース基板と前記キャップ基板の間の空間が、密封されていることを特徴とする請求項1乃至9のいずれか一項に記載の半導体装置。
- 前記ベース基板が、埋め込み酸化膜を有するSOI基板からなり、
前記ベース半導体領域が、前記埋め込み酸化膜に達するトレンチにより周囲から絶縁分離された、SOI層からなる領域であることを特徴とする請求項1乃至10のいずれか一項に記載の半導体装置。 - 前記半導体装置が、力学量センサ素子を有してなり、
前記複数個のベース半導体領域のうち、
少なくとも一個のベース半導体領域が、前記埋め込み酸化膜の一部を犠牲層エッチングすることにより、変位可能に形成された可動電極を有する可動半導体領域であり、
少なくとももう一個のベース半導体領域が、前記可動電極と対向する固定電極を有する固定半導体領域であり、
前記可動電極と固定電極の対向する面の間に静電容量が形成され、
前記可動半導体領域と前記固定半導体領域に、それぞれ、前記引き出し電極が接続され、
前記可動電極が、印加される力学量に応じて前記対向面に対して垂直方向に変位し、
前記可動電極と固定電極の間の距離変化に伴う前記静電容量の変化を測定して、前記印加される力学量を検出することを特徴とする請求項11に記載の半導体装置。 - 前記力学量が、加速度または角速度であることを特徴とする請求項12に記載の半導体装置。
- 前記ベース基板が、単結晶シリコン基板からなり、
前記ベース半導体領域が、PN接合分離により絶縁分離された不純物拡散領域であることを特徴とする請求項1乃至10のいずれか一項に記載の半導体装置。 - 前記半導体装置が、圧力センサ素子を有してなり、
前記複数個のベース半導体領域のうち、
少なくとも一個のベース半導体領域が、前記単結晶シリコン基板の上面側にあるメンブレンに形成された前記不純物拡散領域であり、
前記メンブレンが、印加される圧力に応じて変位し、該変位に伴う前記不純物拡散領域の抵抗値の変化を測定して、前記印加される圧力を検出することを特徴とする請求項14に記載の半導体装置。 - 請求項1に記載の半導体装置の製造方法であって、
前記ベース基板を準備するベース基板準備工程と、
前記キャップ基板を準備するキャップ基板準備工程と、
前記ベース基板と前記キャップ基板を位置決めして積層し、前記ベース基板の上面と前記キャップ基板の下面を貼り合わせる基板貼り合わせ工程と、
前記溝を有するようにして前記引き出し電極を形成する引き出し電極形成工程とを有してなることを特徴とする半導体装置の製造方法。 - 前記基板貼り合わせ工程の後、前記キャップ基板に所定の前記ベース半導体領域に達するトレンチを形成するトレンチ形成工程を有してなり、
前記引き出し電極形成工程において、
前記トレンチに前記金属を埋め込んで前記引き出し電極を形成し、前記トレンチの周りが前記溝となるようにすることを特徴とする請求項16に記載の半導体装置の製造方法。 - 前記キャップ基板準備工程において、
前記引き出し電極形成工程の一部を実施して、前記引き出し電極を前記キャップ基板に連結された状態で形成し、
前記基板貼り合わせ工程において、
前記引き出し電極の下面を所定の前記ベース半導体領域に接続し、
前記基板貼り合わせ工程の後、前記溝を形成することを特徴とする請求項16に記載の半導体装置の製造方法。 - 前記キャップ基板準備工程において、
前記キャップ基板となる1次キャップ基板に、前記溝となる1次溝を形成し、
前記引き出し電極形成工程の一部を実施して、前記1次溝の側壁に前記金属を形成して、前記引き出し電極となる1次引き出し電極を形成し、
前記基板貼り合わせ工程において、
前記1次溝の開口部が前記ベース基板の上面と対向するようにして、前記ベース基板と前記1次キャップ基板を貼り合わせ、
前記基板貼り合わせ工程の後、貼り合わせ面と反対側から前記1次キャップ基板を研削して、1次キャップ基板を前記キャップ基板とすると共に、前記1次引き出し電極と前記1次溝をそれぞれ前記引き出し電極と前記溝とすることを特徴とする請求項16に記載の半導体装置の製造方法。
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US20110147859A1 (en) | 2011-06-23 |
US20140048922A1 (en) | 2014-02-20 |
JP5115618B2 (ja) | 2013-01-09 |
US8941229B2 (en) | 2015-01-27 |
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