US20120235251A1 - Wafer level packaging of mems devices - Google Patents

Wafer level packaging of mems devices Download PDF

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Publication number
US20120235251A1
US20120235251A1 US13/367,271 US201213367271A US2012235251A1 US 20120235251 A1 US20120235251 A1 US 20120235251A1 US 201213367271 A US201213367271 A US 201213367271A US 2012235251 A1 US2012235251 A1 US 2012235251A1
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layer
mems
substrate
mems device
conductive
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US13/367,271
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Michael J. Daneman
Steven S. Nasiri
Martin Lim
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InvenSense Inc
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InvenSense Inc
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Priority to US13/367,271 priority Critical patent/US20120235251A1/en
Assigned to INVENSENSE, INC. reassignment INVENSENSE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: DANEMAN, MICHAEL J., LIM, MARTIN, NASIRI, STEVEN S.
Priority to PCT/US2012/028946 priority patent/WO2012125651A2/en
Priority to US13/455,494 priority patent/US8384134B2/en
Publication of US20120235251A1 publication Critical patent/US20120235251A1/en
Abandoned legal-status Critical Current

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    • AHUMAN NECESSITIES
    • A45HAND OR TRAVELLING ARTICLES
    • A45DHAIRDRESSING OR SHAVING EQUIPMENT; EQUIPMENT FOR COSMETICS OR COSMETIC TREATMENTS, e.g. FOR MANICURING OR PEDICURING
    • A45D27/00Shaving accessories
    • A45D27/42Shaving masks
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/07Integrating an electronic processing unit with a micromechanical structure
    • B81C2203/0785Transfer and j oin technology, i.e. forming the electronic processing unit and the micromechanical structure on separate substrates and joining the substrates
    • B81C2203/0792Forming interconnections between the electronic processing unit and the micromechanical structure

Definitions

  • the present invention relates generally to semiconductor devices, and more particularly to packaging of MEMS devices.
  • Wafer-level packaging of semiconductor devices is a relatively new but widely used technology that allows semi-conductor and MEMS devices to be packaged on a wafer scale with solder balls attached directly to the die (typically through a stress-relief layer). This technology yields the smallest possible package size for any given device while at the same time reducing packaging cost by packaging an entire wafer of die in a batch process.
  • the most common wafer-level packaging technologies (ex. Shellcase, uBGA, WAVE, and others) typically make direct contact to the CMOS wafer metallization, but cannot easily contact the top-layer of the MEMS since it is typically electrically isolated from the CMOS. In cases where the MEMS handle or cap wafer or a metal layer deposited onto the MEMS handle or cap wafer must be electrically contacted, the current wafer-level packaging technologies cannot be directly applied.
  • a MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being bonded to the MEMS substrate.
  • the MEMS device includes one or more conductive features on the back surface of the CMOS substrate and electrical connections between the one or more metallization layers and the one or more conductive features.
  • FIG. 1 is a diagram of a semiconductor device in accordance with an embodiment.
  • FIG. 2A is a flow chart of a packaging process in accordance with the present invention.
  • FIG. 2B is a diagram which illustrates building up a wafer level package utilizing the process of FIG. 2A .
  • the present invention relates generally to semiconductor devices, and more particularly to the packaging of MEMS devices.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
  • Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art.
  • the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • a MEMS device often requires a MEMS handle electrical contact. This contact can either be used for RF shielding of the device or to make electrical contact to a MEMS handle wafer.
  • a method and system in accordance with the present invention enables wafer-level packaging (WLP) also known as wafer-level chip scale packaging (WLCSP), of such MEMS devices using CMOS-side contact based on a Shellcase or Through Silicon Via (TSV) process, or any other wafer-level packaging process providing a CMOS-side electrical contact, while still providing a MEMS handle-side electrical connection.
  • WLP wafer-level packaging
  • WLCSP wafer-level chip scale packaging
  • TSV Through Silicon Via
  • the structure and process for wafer-level packaging of MEMS devices comprises:
  • a MEMS device wafer comprising a CMOS substrate bonded to a MEMS substrate, the MEMS substrate comprising a handle wafer with cavities bonded to a patterned electrically conductive Device Layer with an insulating layer positioned between the two wafers.
  • a top metallization layer electrically connected to the Device Layer comprising:
  • the conducting layer may also make electrical contact to the Handle Wafer, thereby electrically connecting the Handle Wafer to the portion of the Device Wafer.
  • One or more openings in the back-side of the CMOS substrate exposing one or more metal interconnection layer.
  • a conductive layer coating the insulating layer on the back-side of the CMOS substrate and on sidewalls of the one or more openings and providing physical and electrical contact to the one or more metal interconnection layers.
  • FIG. 1 is a diagram of a semiconductor device 100 in accordance with an embodiment before processing.
  • the semiconductor device 100 comprises a MEMS handle 102 ; a silicon oxide layer 103 , a MEMS device layer 104 , and a CMOS wafer 106 .
  • the handle wafer 102 includes etched cavities and is coated by, for example, a thin silicon oxide layer and fusion bonded to a MEMS device layer 104 .
  • the MEMS device layer 104 is patterned to define the desired moveable or stationary structure.
  • FIG. 2A is a flow chart of a packaging process in accordance with the present invention.
  • FIG. 2B is a diagram which illustrates building up a wafer level package utilizing the process of FIG. 2A .
  • both sides of the device are ground down to the desired size, using step 202 .
  • wedge shaped cuts are made in the non-functional region of the MEMS so as to cut completely through the handle wafer 102 and silicon oxide layer 103 and cut partially into the device layer 104 , using step 204 , leaving a wedge-shaped opening 108 in the device 100 .
  • the wedge-shaped opening can be created using a wet or dry etching of the handle wafer 102 and silicon oxide layer 103 .
  • the required wedge angle depends on the conformality of the metal deposition system used for the following metal deposition.
  • a conductive metallization layer 110 is blanket deposited onto the MEMS side of the device 100 , using step 206 .
  • the metallization (for example, aluminum or copper) layer may be sputter deposited, evaporated, or deposited through plasma or thermally enhanced chemical vapor deposition (CVD).
  • the metallization layer 110 covers the top surface of the semiconductor device 100 as well as the side-walls of the wedge-shaped openings 108 , thereby making a physical and electrical contact to the device layer 104 . Due to the high doping of the device layer 104 , an ohmic contact will be formed to the metallization layer 110 . In some embodiments an additional anneal may be required to enhance diffusion of metallization into silicon to enhance electrical contact. In an alternate embodiment, the metallization layer 110 may comprise any electrically conductive metal or semi-conductor.
  • TSV through-silicon-via
  • the TSV process begins with an opening 112 being etched in the back of the CMOS substrate 106 stopping on one of the CMOS metallization layers, using step 208 .
  • the CMOS substrate 106 metallization layer 107 may be any one of the existing CMOS metallization layers.
  • the sidewalls of the opening 112 are then electrically passivated by depositing an insulating film 109 (ex. silicon oxide, silicon nitride, polymer), using step 210 .
  • the insulating film 109 will also deposit on the bottom surface of the opening 112 , covering the previously exposed CMOS metallization layer 107 .
  • the CMOS metallization layer 107 is then once again exposed by an etching or saw dicing process such that the insulating film 109 on the sidewalls of the opening is not removed. This etching or saw dicing process may expose the surface, edges, or both of the CMOS metallization layer 107 .
  • a conductive interconnection layer, 114 (typically a metal layer composed of Aluminum or Copper) is deposited onto the back surface of the CMOS substrate 106 and into the passivated openings 112 so as to create electrical contact to the CMOS metallization layer 107 .
  • the interconnection layer 114 is then patterned so as to create individual isolated contacts.
  • a polymer stress-relief layer 116 would optionally be deposited on top of the interconnection layer 114 to reduce stress on the silicon die caused by board-level assembly, using step 212 .
  • the stress-relief layer 116 is patterned so as to create vias to the interconnection layer 114 .
  • a conductive redistribution layer 118 is deposited and patterned on top of the stress-relief layer 116 , using step 214 .
  • solder balls 120 are defined on top of the redistribution layer 118 to facilitate soldering the packaged die to a printed circuit board, using step 216 .
  • the die may be packaged using Shellcase wedge-dicing type wafer level packaging process.
  • the die may be packaged using any available packaging technology using wire bonding including but not limited to a Leadless Chip Carrier (LCC), a Quad Flat No Leads (QFN) or a Multichip module.
  • LCC Leadless Chip Carrier
  • QFN Quad Flat No Leads
  • Multichip module a Multichip module
  • a conductive layer may be any metal or semi-conductor and may be deposited using sputtering, Chemical Vapor Deposition (CVD), Plasma-Enhance Chemical Vapor Deposition (PECVD), Molecular Vapor Deposition (MVD), or any other thin film deposition method with sufficient conformality.
  • CVD Chemical Vapor Deposition
  • PECVD Plasma-Enhance Chemical Vapor Deposition
  • MMD Molecular Vapor Deposition

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Micromachines (AREA)

Abstract

A MEMS device is disclosed. The MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being bonded to the MEMS substrate. The MEMS device includes one or more conductive features on the back surface of the CMOS substrate and electrical connections between the one or more metallization layers and the one or more conductive features.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • Under 35 USC 119(e), this application claims priority to U.S. provisional application Ser. No. 61/452,545 filed on Mar. 14, 2011.
  • FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor devices, and more particularly to packaging of MEMS devices.
  • BACKGROUND OF THE INVENTION
  • Wafer-level packaging of semiconductor devices is a relatively new but widely used technology that allows semi-conductor and MEMS devices to be packaged on a wafer scale with solder balls attached directly to the die (typically through a stress-relief layer). This technology yields the smallest possible package size for any given device while at the same time reducing packaging cost by packaging an entire wafer of die in a batch process. The most common wafer-level packaging technologies (ex. Shellcase, uBGA, WAVE, and others) typically make direct contact to the CMOS wafer metallization, but cannot easily contact the top-layer of the MEMS since it is typically electrically isolated from the CMOS. In cases where the MEMS handle or cap wafer or a metal layer deposited onto the MEMS handle or cap wafer must be electrically contacted, the current wafer-level packaging technologies cannot be directly applied.
  • Accordingly, what is desired is a system and method which would overcome the above-identified issues. The method and system should be easy to implement, cost-effective, and adaptable to existing systems. The present invention addresses such a need.
  • SUMMARY OF THE INVENTION
  • A MEMS device is disclosed. The MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being bonded to the MEMS substrate. The MEMS device includes one or more conductive features on the back surface of the CMOS substrate and electrical connections between the one or more metallization layers and the one or more conductive features.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a diagram of a semiconductor device in accordance with an embodiment.
  • FIG. 2A is a flow chart of a packaging process in accordance with the present invention.
  • FIG. 2B is a diagram which illustrates building up a wafer level package utilizing the process of FIG. 2A.
  • DETAILED DESCRIPTION
  • The present invention relates generally to semiconductor devices, and more particularly to the packaging of MEMS devices. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • A MEMS device often requires a MEMS handle electrical contact. This contact can either be used for RF shielding of the device or to make electrical contact to a MEMS handle wafer. A method and system in accordance with the present invention enables wafer-level packaging (WLP) also known as wafer-level chip scale packaging (WLCSP), of such MEMS devices using CMOS-side contact based on a Shellcase or Through Silicon Via (TSV) process, or any other wafer-level packaging process providing a CMOS-side electrical contact, while still providing a MEMS handle-side electrical connection.
  • The structure and process for wafer-level packaging of MEMS devices comprises:
  • 1. A MEMS device wafer comprising a CMOS substrate bonded to a MEMS substrate, the MEMS substrate comprising a handle wafer with cavities bonded to a patterned electrically conductive Device Layer with an insulating layer positioned between the two wafers.
  • 2. A top metallization layer electrically connected to the Device Layer comprising:
  • (a) A wedge-shaped opening penetrating completely through the Handle Wafer and insulating layers, and partially penetrating into the Device Wafer.
  • (b) A conducting layer deposited onto the MEMS substrate such that the conducting layer covers the sidewalls of the wedge-shaped opening including making physical contact to a portion of the Device Layer thereby electrically connecting the conductive layer to the portion of the Device layer. Optionally, the conducting layer may also make electrical contact to the Handle Wafer, thereby electrically connecting the Handle Wafer to the portion of the Device Wafer.
  • 3. One or more openings in the back-side of the CMOS substrate exposing one or more metal interconnection layer.
  • 4. An insulating layer coating the sidewalls of the one or more openings and the back-side of the CMOS substrate.
  • 5. A conductive layer coating the insulating layer on the back-side of the CMOS substrate and on sidewalls of the one or more openings and providing physical and electrical contact to the one or more metal interconnection layers.
  • 6. One or more solder-balls connected to the conductive layer.
  • In the preferred embodiment a MEMS bonded device wafer would comprise a standard CMOS wafer with an Aluminum or Copper top metallization layer eutecticly bonded to a MEMS wafer. To describe the features of the invention in more detail refer now to the following description in connection with the accompanying Figures. FIG. 1 is a diagram of a semiconductor device 100 in accordance with an embodiment before processing. The semiconductor device 100 comprises a MEMS handle 102; a silicon oxide layer 103, a MEMS device layer 104, and a CMOS wafer 106.
  • The handle wafer 102 includes etched cavities and is coated by, for example, a thin silicon oxide layer and fusion bonded to a MEMS device layer 104. The MEMS device layer 104 is patterned to define the desired moveable or stationary structure.
  • FIG. 2A is a flow chart of a packaging process in accordance with the present invention. FIG. 2B is a diagram which illustrates building up a wafer level package utilizing the process of FIG. 2A.
  • Referring now to FIGS. 2A and 2B together, initially both sides of the device (CMOS side 106 and MEMS handle 102), are ground down to the desired size, using step 202.
  • Thereafter, wedge shaped cuts are made in the non-functional region of the MEMS so as to cut completely through the handle wafer 102 and silicon oxide layer 103 and cut partially into the device layer 104, using step 204, leaving a wedge-shaped opening 108 in the device 100. In an alternate embodiment, the wedge-shaped opening can be created using a wet or dry etching of the handle wafer 102 and silicon oxide layer 103. The required wedge angle depends on the conformality of the metal deposition system used for the following metal deposition.
  • Next, a conductive metallization layer 110 is blanket deposited onto the MEMS side of the device 100, using step 206. The metallization (for example, aluminum or copper) layer may be sputter deposited, evaporated, or deposited through plasma or thermally enhanced chemical vapor deposition (CVD).
  • The metallization layer 110 covers the top surface of the semiconductor device 100 as well as the side-walls of the wedge-shaped openings 108, thereby making a physical and electrical contact to the device layer 104. Due to the high doping of the device layer 104, an ohmic contact will be formed to the metallization layer 110. In some embodiments an additional anneal may be required to enhance diffusion of metallization into silicon to enhance electrical contact. In an alternate embodiment, the metallization layer 110 may comprise any electrically conductive metal or semi-conductor.
  • Next the device is packaged using a through-silicon-via (TSV) wafer level packaging process.
  • The TSV process begins with an opening 112 being etched in the back of the CMOS substrate 106 stopping on one of the CMOS metallization layers, using step 208. The CMOS substrate 106 metallization layer 107 may be any one of the existing CMOS metallization layers. The sidewalls of the opening 112 are then electrically passivated by depositing an insulating film 109(ex. silicon oxide, silicon nitride, polymer), using step 210. Typically the insulating film 109 will also deposit on the bottom surface of the opening 112, covering the previously exposed CMOS metallization layer 107.
  • The CMOS metallization layer 107 is then once again exposed by an etching or saw dicing process such that the insulating film 109 on the sidewalls of the opening is not removed. This etching or saw dicing process may expose the surface, edges, or both of the CMOS metallization layer 107. A conductive interconnection layer, 114, (typically a metal layer composed of Aluminum or Copper) is deposited onto the back surface of the CMOS substrate 106 and into the passivated openings 112 so as to create electrical contact to the CMOS metallization layer 107.
  • The interconnection layer 114 is then patterned so as to create individual isolated contacts. A polymer stress-relief layer 116 would optionally be deposited on top of the interconnection layer 114 to reduce stress on the silicon die caused by board-level assembly, using step 212. The stress-relief layer 116 is patterned so as to create vias to the interconnection layer 114. Then a conductive redistribution layer 118 is deposited and patterned on top of the stress-relief layer 116, using step 214. Finally, solder balls 120 are defined on top of the redistribution layer 118 to facilitate soldering the packaged die to a printed circuit board, using step 216.
  • In a first alternate embodiment, the die may be packaged using Shellcase wedge-dicing type wafer level packaging process.
  • In a second alternate embodiment, the die may be packaged using any available packaging technology using wire bonding including but not limited to a Leadless Chip Carrier (LCC), a Quad Flat No Leads (QFN) or a Multichip module.
  • In a third alternate embodiment, the openings in the handle-wafer side of the MEMS may be etched rather than saw-diced. Furthermore, a conductive layer may be any metal or semi-conductor and may be deposited using sputtering, Chemical Vapor Deposition (CVD), Plasma-Enhance Chemical Vapor Deposition (PECVD), Molecular Vapor Deposition (MVD), or any other thin film deposition method with sufficient conformality.
  • Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims (21)

1. A MEMS device comprising:
a MEMS substrate;
a CMOS substrate having a front surface, a back surface and one or more metallization layers; the front surface being bonded to the MEMS substrate;
one or more conductive features on the back surface of the CMOS substrate; and
electrical connections between the one or more metallization layers and the one or more conductive features.
2. The MEMS device of claim 1, wherein the conductive features are solder balls.
3. The MEMS device of claim 1, wherein the conductive features include a second conductive redistribution layer
4. The MEMS device of claim 3, wherein a stress relief layer is formed beneath the second conductive redistribution layer
5. The MEMS device of claim 3, wherein the conductive features are solder balls.
6. The MEMS device of claim 1, wherein the electrical connections comprise
one or more openings in the back-surface of the CMOS substrate exposing the one or more metallization layers;
a second insulating layer coating the sidewalls of the one or more openings in the back surface of the CMOS substrate; and
a conductive layer coating the insulating layer on the back surface of the CMOS substrate and on sidewalls of the one or more openings and providing physical and electrical contact to the one of more metallization layers.
7. The MEMS device of claim 1, wherein the MEMS substrate comprises
a handle wafer bonded to a patterned electrically conductive device layer with an insulating layer positioned between the two wafers
8. The MEMS device of claim 7 further comprising
an opening penetrating completely through the handle wafer and the insulating layer, and exposing a device layer; and
a second conductive layer deposited onto the MEMS substrate such that the second conductive layer at least partially covers the surface of the MEMS substrate and the sidewalls of the opening include making physical contact to the device layer, wherein the conductive layer is electrically connected to the device layer.
9. A MEMS device comprising:
a MEMS substrate, wherein the MEMS substrate includes a handle wafer bonded to a patterned electrically conductive device layer with an insulating layer positioned between the two wafers;
an opening penetrating completely through the handle wafer and the insulating layer, and exposing the device layer; and
a conductive layer deposited onto the MEMS substrate such that the conductive layer at least partially covers the surface of the MEMS substrate and the sidewalls of the opening including making physical contact to the device layer thereby electrically connecting the conductive layer to the device layer.
10. The MEMS device of claim 9, wherein the opening has sloped sidewalls.
11. The MEMS device of claim 10, wherein a CMOS substrate is bonded to the MEMS substrate.
12. The MEMS device of claim 11, wherein one or more openings in the back-side of the CMOS substrate exposing one or more metal interconnection layer.
13. The MEMS device wafer of claim 12, wherein a second insulating layer coats the sloped sidewalls of the one or more openings in the back-side of the CMOS substrate.
14. The MEMS device wafer of claim 13, wherein the conductive layer coats the insulating layer on the back-side of the CMOS substrate and on sidewalls of the one or more openings and provides physical and electrical contact to the one of more metal interconnection layers.
15. The MEMS device wafer of claim 9, wherein one or more solder-balls are connected to the conductive layer.
16. A MEMS device comprising:
a MEMS substrate, wherein the MEMS substrate includes a top layer connected to an electrically conductive bottom layer;
an opening penetrating completely through the top layer, and exposing the bottom layer; and
a second electrically conductive layer deposited onto the MEMS substrate such that the second electrically conductive layer at least partially covers the surface and the sidewalls of the opening including making physical contact to the bottom layer, wherein the second electrically conductive layer is electrically connected to the bottom layer.
17. The MEMS device of claim 16, wherein the opening has sloped sidewalls.
18. The MEMS device of claim 16, wherein a CMOS substrate is bonded to the MEMS substrate.
19. The MEMS device of claim 18, wherein one or more openings in the back-side of the CMOS substrate exposing one or more metal interconnection layer.
20. The MEMS device of claim 19, wherein a third electrically conductive layer coats the insulating layer on the back-side of the CMOS substrate and on sidewalls of the one or more openings and provides physical and electrical contact to the one of more metal interconnection layers.
21. The MEMS device wafer of claim 20, wherein one or more solder-balls are connected to the third conductive layer.
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US13/455,494 US8384134B2 (en) 2011-03-14 2012-04-25 MEMS device including an electrical interconnect through a substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014200512A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014200507A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014200500A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014202808A1 (en) 2014-02-17 2015-08-20 Robert Bosch Gmbh Method for eutectic bonding of two carrier devices
DE102014212314A1 (en) 2014-06-26 2015-12-31 Robert Bosch Gmbh Micromechanical sensor device
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DE102022205829A1 (en) 2022-06-08 2023-12-14 Robert Bosch Gesellschaft mit beschränkter Haftung Manufacturing method for a micromechanical sensor device and corresponding micromechanical sensor device

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015042700A1 (en) 2013-09-24 2015-04-02 Motion Engine Inc. Mems components and method of wafer-level manufacturing thereof
JP6339669B2 (en) 2013-07-08 2018-06-06 モーション・エンジン・インコーポレーテッド MEMS device and method of manufacturing
EP3028007A4 (en) 2013-08-02 2017-07-12 Motion Engine Inc. Mems motion sensor and method of manufacturing
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WO2015154173A1 (en) 2014-04-10 2015-10-15 Motion Engine Inc. Mems pressure sensor
WO2015184531A1 (en) 2014-06-02 2015-12-10 Motion Engine Inc. Multi-mass mems motion sensor
CA3004760A1 (en) 2014-12-09 2016-06-16 Motion Engine Inc. 3d mems magnetometer and associated methods
CA3220839A1 (en) 2015-01-15 2016-07-21 Motion Engine Inc. 3d mems device with hermetic cavity
US10605823B2 (en) 2016-02-25 2020-03-31 m.Cube, Inc. Multiple MEMS device and methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080061029A1 (en) * 2006-08-09 2008-03-13 Shouliang Lai Method for Plasma Etching of Positively Sloped Structures
US20120080761A1 (en) * 2010-10-05 2012-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor having a high aspect ratio via
US20120098122A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging of micro-electro-mechanical systems (mems) and complementary metal-oxide-semiconductor (cmos) substrates

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US6544898B2 (en) * 2001-06-25 2003-04-08 Adc Telecommunications, Inc. Method for improved die release of a semiconductor device from a wafer
US7104129B2 (en) * 2004-02-02 2006-09-12 Invensense Inc. Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US7442570B2 (en) * 2005-03-18 2008-10-28 Invensence Inc. Method of fabrication of a AL/GE bonding in a wafer packaging environment and a product produced therefrom
US7767484B2 (en) * 2006-05-31 2010-08-03 Georgia Tech Research Corporation Method for sealing and backside releasing of microelectromechanical systems
US8264307B2 (en) * 2007-05-09 2012-09-11 Innovative Micro Technology Dual substrate MEMS plate switch and method of manufacture
US7677099B2 (en) * 2007-11-05 2010-03-16 Invensense Inc. Integrated microelectromechanical systems (MEMS) vibrating mass Z-axis rate sensor
US8697545B2 (en) * 2007-12-28 2014-04-15 The Royal Institution For The Advancement Of Learning/Mcgill University Direct contact heat control of micro structures
US10040681B2 (en) * 2009-08-28 2018-08-07 Miradia Inc. Method and system for MEMS devices
JP5115618B2 (en) * 2009-12-17 2013-01-09 株式会社デンソー Semiconductor device
US8507358B2 (en) * 2010-08-27 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Composite wafer semiconductor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080061029A1 (en) * 2006-08-09 2008-03-13 Shouliang Lai Method for Plasma Etching of Positively Sloped Structures
US20120080761A1 (en) * 2010-10-05 2012-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor having a high aspect ratio via
US20120098122A1 (en) * 2010-10-21 2012-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level packaging of micro-electro-mechanical systems (mems) and complementary metal-oxide-semiconductor (cmos) substrates

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160327446A1 (en) * 2014-01-14 2016-11-10 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014200507A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014200500A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
WO2015106854A1 (en) 2014-01-14 2015-07-23 Robert Bosch Gmbh Micromechanical presssure sensor and corresponding production method
DE102014200512A1 (en) 2014-01-14 2015-07-16 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
US9958348B2 (en) * 2014-01-14 2018-05-01 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
US9709451B2 (en) 2014-01-14 2017-07-18 Robert Bosch Gmbh Micromechanical pressure sensor device and corresponding manufacturing method
DE102014202808A1 (en) 2014-02-17 2015-08-20 Robert Bosch Gmbh Method for eutectic bonding of two carrier devices
US9650236B2 (en) 2014-06-26 2017-05-16 Robert Bosch Gmbh Micromechanical sensor device
DE102014212314A1 (en) 2014-06-26 2015-12-31 Robert Bosch Gmbh Micromechanical sensor device
DE102014224559A1 (en) 2014-12-01 2016-06-02 Robert Bosch Gmbh Micromechanical sensor device and corresponding manufacturing method
US9725309B2 (en) 2014-12-01 2017-08-08 Robert Bosch Gmbh Micromechanical sensor device and corresponding manufacturing method
DE102014226436A1 (en) 2014-12-18 2016-06-23 Robert Bosch Gmbh Micromechanical sensor device and corresponding manufacturing method
DE102016216207A1 (en) 2016-08-29 2018-03-01 Robert Bosch Gmbh Method for producing a micromechanical sensor
WO2018041444A1 (en) 2016-08-29 2018-03-08 Robert Bosch Gmbh Method for producing a micromechanical sensor
US11111137B2 (en) 2016-08-29 2021-09-07 Robert Bosch Gmbh Method for manufacturing a micromechanical sensor
DE102020214547A1 (en) 2020-11-18 2022-05-19 Robert Bosch Gesellschaft mit beschränkter Haftung Micromechanical device and method of manufacture
DE102022205829A1 (en) 2022-06-08 2023-12-14 Robert Bosch Gesellschaft mit beschränkter Haftung Manufacturing method for a micromechanical sensor device and corresponding micromechanical sensor device

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