WO2022218610A1 - Semiconductor device with sealed through-substrate via and method for producing thereof - Google Patents

Semiconductor device with sealed through-substrate via and method for producing thereof Download PDF

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Publication number
WO2022218610A1
WO2022218610A1 PCT/EP2022/056006 EP2022056006W WO2022218610A1 WO 2022218610 A1 WO2022218610 A1 WO 2022218610A1 EP 2022056006 W EP2022056006 W EP 2022056006W WO 2022218610 A1 WO2022218610 A1 WO 2022218610A1
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WIPO (PCT)
Prior art keywords
layer
substrate
via hole
rear surface
semiconductor device
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PCT/EP2022/056006
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French (fr)
Inventor
Peter JERABEK
Georg PARTEDER
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Ams-Osram Ag
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Publication of WO2022218610A1 publication Critical patent/WO2022218610A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the present invention relates to a semiconductor device, a sensor device comprising a semiconductor device and a method for producing a semiconductor device.
  • the semiconductor device comprises a sealed through-substrate-via.
  • TSVs through-substrate-vias
  • a TSV is an electric interconnection through a semiconductor substrate. It comprises a via hole penetrating the substrate and a metallization arranged in the via hole.
  • a TSV can be produced by first forming a metal layer in an intermetal dielectric on a main surface of the substrate. Then, a via hole is etched from a rear surface through the substrate, until the intermetal dielectric is reached. An insulating layer is arranged on a sidewall and a bottom of the via hole. The insulation layer and the intermetal dielectric are removed from the bottom of the via hole by an anisotropic etching step, such that the insulation layer remains on the sidewall to cover the semiconductor material. After that etching step, the metal layer is exposed at the bottom of the via hole. A metallization can be applied in the via hole, such that it contacts the metal layer and forms an electric interconnection. Conventionally, the metallization completely fills the via hole.
  • the via hole is completely filled by a copper metallization.
  • this approach comes with several drawbacks: On the one side, as the via hole is completely filled by the metallization, the material consumption is high, leading to high production costs. On the other side, the semiconductor device is prone to stress- induced cracks, e.g. due to differences in the coefficients of thermal extension. Moreover, in some cases, e.g. for CMOS fabrication, a copper metallization may be undesired due to contamination reasons.
  • a metallization layer is applied, that only covers the sidewall and the bottom of the via hole. This means that the remaining via hole remains void.
  • the metallization layer may comprise tungsten, which can be deposited by chemical vapour deposition, CVD, in a conformal way.
  • an object to be achieved is to provide an improved concept for TSV technology.
  • the reliability of a TSV is enhanced and further processing after forming the TSV is facilitated. This object is achieved with the subject-matter of the independent claims. Further developments and embodiments are described in dependent claims.
  • a semiconductor device comprises a substrate with a rear surface and a main surface.
  • a metal layer is arranged on or above the main surface of the substrate.
  • the semiconductor device further comprises a through-substrate-via, TSV, comprising a via hole, an insulation layer and a metallization layer.
  • the via hole reaches from the rear surface of the substrate to the metal layer.
  • the insulation layer is arranged on a sidewall of the via hole between the substrate and the metallization layer.
  • the metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate. A thickness of the insulation layer increases towards the rear surface of the substrate, such that the via hole is narrowed.
  • the via hole is sealed by the metallization layer.
  • the via hole is sealed by a sealing layer. By sealing the via hole a cavity is formed.
  • the substrate has a main plane of extension.
  • the main surface and the rear surface of the substrate run in lateral directions, wherein lateral direction are parallel to the main plane of extension of the substrate.
  • the substrate may comprise a semiconductor material, e.g. silicon (Si).
  • the metal layer may especially be part of a wiring, which may comprise several metal layers, for instance.
  • the metal layer may comprise aluminum (Al).
  • the metal layer may be doped with copper (Cu) and/or silicon (Si).
  • the metal layer may form an AlSi or AlCu layer.
  • Metal layers of a wiring, which are embedded in an intermetal dielectric are conventionally provided with barrier layers, in particular in CMOS technology, in order to enhance the adhesion of the dielectric material to the metal layers and in order to prevent diffusion processes like electromigration.
  • the metal layer may be sandwiched between two barrier layers on top and bottom of the metal layer, respectively.
  • the barrier layers may comprise titanium (Ti) and/or titanium nitride (TiN).
  • the TSV reaches from the rear surface of the substrate to the metal layer. This means that the via hole of the TSV completely penetrates the substrate opposite the metal layer.
  • the TSV has a vertical extent from the rear surface of the substrate to the metal layer.
  • the vertical direction refers to a direction which runs perpendicular to the main plane of extension of the substrate.
  • the TSV is aligned with the metal layer.
  • a lateral extent of the TSV is smaller than a lateral extent of the metal layer.
  • the insulating layer is arranged on a sidewall of the via hole.
  • the substrate is electrically isolated from the metallization layer of the TSV.
  • the insulating layer comprises, for example, S1O 2 .
  • the insulating layer covers the sidewall of the via hole. A portion of the insulation layer may typically also cover the rear surface of the substrate outside the via hole. By means of the insulation layer short circuits are avoided.
  • the substrate can be at an electric potential that is different from an electric potential of the TSV.
  • the thickness of the insulation layer on the sidewall of the via hole increases towards the rear surface of the substrate.
  • the insulation layer is a non-conformal layer, i.e. its thickness is not uniform.
  • an opening of the via hole narrows.
  • a diameter of the opening after the deposition of the insulation layer could be at least 0.5 pm and at most 20 pm.
  • the diameter of the opening after the deposition of the insulation layer could be at least 1 pm and at most 10 pm.
  • the diameter of the opening after the deposition of the insulation layer could be up to 1 pm, 2 pm or 3 pm, respectively.
  • the diameter of the opening after the deposition of the insulation layer could be up to 4 pm, 10 pm or even 20 pm, respectively.
  • the metallization layer may comprise tungsten (W).
  • the metallization layer of the TSV may comprise a sidewall portion covering the insulation layer on the sidewall of the via hole. This means that the insulating layer separates the substrate from the metallization.
  • the metallization layer may further comprise a base portion covering the exposed metal layer, thus forming an electrical contact.
  • the metallization layer can be a conformal layer. Thus, it may have a uniform thickness.
  • the via hole may be sealed by means of the sealing layer.
  • the metallization layer is a non-conformal layer. This is especially true for such embodiments where the via hole is sealed by the metallization layer. In these cases, the metallization layer may be thicker at the rear surface of the substrate than at the bottom of the via hole.
  • the sidewall portion and the base portion of the metallization layer ensure a continuous metallization from the rear surface of the substrate to the metal layer.
  • the remaining via hole is void/ not filled. This can be beneficial in view of thermal and mechanical stress, and material consumption.
  • the via hole By sealing the via hole the via hole is closed. Thus, a cavity within the TSV is formed.
  • the cavity may be filled with air or gas.
  • the closed via hole leads to a higher structural stability. Moreover, the semiconductor device is protected against moisture, particles, dry etch reactants and other chemicals. If the via hole were open, particles and the like could deposit in the via hole and damage the metallization layer.
  • the semiconductor device further comprises an intermetal dielectric arranged on the main surface of substrate.
  • the intermetal dielectric can be an oxide, e.g. silicon oxide (S1O 2) ⁇
  • the metal layer is embedded in the intermetal dielectric.
  • the metallization layer forms a plug at the rear surface of the substrate that seals the via hole.
  • the sealing layer forms a plug that seals the via hole at the rear surface of the substrate. The plug closes the via hole, such that the structural stability is enhanced and the via hole is protected against moisture, particles, dry etch reactants and other chemicals.
  • a portion of the insulation layer is arranged on the rear surface of the substrate.
  • the substrate is electrically isolated.
  • a contact area can be arranged at the rear surface of the substrate.
  • a planar surface is formed by the portion of the insulation layer arranged on the rear surface of the substrate, the metallization layer and/or the sealing layer.
  • the planar surface spans the TSV.
  • the planar surface may be parallel to the rear surface of the substrate.
  • the metallization layer may form a circular area within the planar surface.
  • the sealing layer forms the plug sealing the via hole
  • the metallization layer forms a ring-shaped area within the planar surface.
  • the planar surface has the effect of leveling the topography caused by the via hole. As a result, further processing on the rear side of the semiconductor device is facilitated. In particular, it is possible to use standard lithography steps for further processing. No high viscosity photoresist is needed to cover the via hole. This reduces the production costs. One or more redistribution layers can be deposited on the planar surface by a CMOS backend process flow. Moreover, the use of standard steps for an under bump metallization is allowed .
  • the semiconductor device further comprises a redistribution layer.
  • the redistribution layer is electrically connected to the metallization layer and forms at least one contact area at the rear surface of the substrate .
  • the redistribution layer can be a planar layer deposited on the planar surface.
  • the redistribution layer can be patterned by standard lithography. Since, according to one embodiment, the metallization layer may be part of the planar surface, the redistribution layer is in direct contact with the metallization layer.
  • the redistribution layer overlaps the sidewall portion of the metallization layer.
  • the redistribution layer extends into the via hole so that at least part of the sidewall portion of the metallization layer is covered by it.
  • the via hole is sealed by the sealing layer, which may be a passivation layer in this case.
  • the redistribution layer may comprise aluminum (Al).
  • Al aluminum
  • the redistribution layer does not contain tungsten, since large-area surfaces consisting of tungsten exhibit high layer stress, which could lead to delamination or chipping. With the help of the redistribution layer electrical signals can be transmitted and/or redirected.
  • the semiconductor device can comprise further redistribution layers, such that the redistribution layer and the further redistribution layers form a wiring at the rear surface of the substrate.
  • the redistribution layer can be provided with an under bump metallization to which solder bumps can be applied.
  • the redistribution layer is covered by a passivation layer, apart from the contact area.
  • the passivation layer may comprise a dielectric material, for example, silicon oxide and/or silicon nitride (SiN). At least one opening in the passivation layer provides access to the contact area at the rear surface of the substrate. Thus, a solder bump, bond wire or the like can be applied.
  • the passivation layer protects the semiconductor device from physical damage like scratches and/or moisture induced damage.
  • the sealing layer comprises an oxide layer.
  • the sealing layer comprises a passivation layer.
  • the sealing layer may be a non-conformal oxide layer.
  • the oxide layer may have a non-uniform thickness, such that its thickness is high at the via hole opening, but small in the via hole.
  • the oxide layer forms a plug sealing the via hole.
  • the sealing layer is a passivation layer, it may be the same passivation layer that covers the redistribution layer. A portion of the passivation layer may be present in the via hole covering the metallization layer.
  • the via hole can be sealed with a few additional or typically already existing layers.
  • a sensor device that comprises the semiconductor device. This means that all features disclosed for the semiconductor device are also disclosed for and applicable to the sensor device and vice-versa.
  • the sensor device is an ambient light sensor. In another embodiment, the sensor device is a color sensor. In another embodiment, the sensor device is a proximity sensor. In another embodiment, the sensor device is a photon counting sensor. In another embodiment, the sensor device is a time-of-flight sensor. According to an aspect of the invention, the sensor device comprises a sensor behind an organic light emitting diode (OLED) display.
  • OLED organic light emitting diode
  • the mobile handset market will continue to follow the trend to ever higher screen-to-body ratios and ultimately to all screen, bezel-less smartphones.
  • sensor elements comprised by such devices have to be highly integrated, such that 3D-integration techniques are needed.
  • the sensor devices used comprise semiconductor devices with TSVs, through which electrical contacting from the rear surface is possible.
  • a terminal device, such as a smartphone can thus be designed to be very thin.
  • the front of the terminal device can, for example, be completely filled by a screen, e.g. an OLED display.
  • a method for producing a semiconductor device is provided. All features disclosed for the semiconductor device and the sensor device are also disclosed for the method for producing a semiconductor device and vice-versa.
  • the method comprises providing a substrate with a rear surface and a main surface.
  • the substrate may comprise a semiconductor material, e.g. silicon (Si).
  • the method further comprises arranging a metal layer on or above the main surface of substrate.
  • an intermetal dielectric is arranged on the main surface of the substrate, in which the metal layer is embedded.
  • the intermetal dielectric can be an oxide, e.g. silicon oxide (S1O 2) ⁇
  • the intermetal dielectric can be deposited on the substrate in one or more deposition steps, e.g. via chemical vapor deposition (CVD).
  • the metal layer may comprise aluminum (Al).
  • the metal layer may comprise barrier layers.
  • the barrier layers may comprise titanium (Ti) and/or titanium nitride (TiN).
  • the metal layer including the barrier layers may be deposited by sputter processes between two subsequent deposition steps for the intermetal dielectric. Patterning of the metal layer can be conducted by etching.
  • the method further comprises forming a through-substrate-via, TSV.
  • Forming the TSV comprises forming a via hole from the rear surface of the substrate to the metal layer. This can mean that the via hole is formed by removing the substrate opposite the metal layer.
  • the via hole can be formed by deep reactive-ion etching (DRIE) into the silicon substrate.
  • DRIE deep reactive-ion etching
  • the DRIE process can be controlled by time or by use of an etch stop layer.
  • the DRIE process is also called Bosch process. DRIE is a fast and efficient anisotropic etching technique.
  • the via hole may be extended by removing the intermetal dielectric up to the metal layer. This means that a further etching step removes the intermetal dielectric between the substrate and the metal layer.
  • the metal layer can be used as etch stop layer.
  • the further etching step exposes the metal layer.
  • Forming the TSV further comprises depositing an insulation layer on a sidewall of the via hole.
  • the insulation layer may be deposited after removing the intermetal dielectric up to the metal layer.
  • the insulating layer comprises, for example, SiCh.
  • the deposition of the insulating layer can be conducted by CVD.
  • the insulating layer covers the sidewall of the via hole. Portions of the insulation layer may typically also cover the bottom of the via hole, i.e. the metal layer, and the rear surface of the substrate outside the via hole.
  • the insulating layer is removed from the bottom of the via hole by an anisotropic etching step, such that the metal layer is exposed.
  • the insulating layer is deposited after removing the substrate opposite the metal layer and before removing the intermetal dielectric.
  • the insulation layer can be removed from the bottom of the via hole in the same anisotropic etching step that is also used for removing the intermetal dielectric.
  • the insulation layer is deposited such that a thickness of the insulation layer on the sidewall of the via hole increases towards the rear surface of the substrate.
  • the via hole is narrowed towards the rear surface. This can be achieved by a non-conformal deposition. It is also possible that more than one deposition steps are used to form the insulation layer.
  • the insulation layer By means of the insulation layer the substrate is electrically isolated and short circuits are avoided. By narrowing the via hole towards the rear surface, the via hole can be sealed in a subsequent deposition step.
  • Forming the TSV further comprises depositing a metallization layer.
  • the metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate.
  • the metallization layer may comprise more than one metal and may be applied as a sequence of metal layers, which may include titanium and/or tungsten layers, for instance.
  • a sidewall portion of the metallization layer covers the sidewall of the via hole and a base portion of the metallization layer covers the exposed metal layer.
  • the metallization is isolated from the substrate by the insulation layer. The metallization is in direct contact with the exposed metal layer.
  • Forming the TSV further comprises sealing the via hole by the metallization layer.
  • the via hole is sealed by the deposition of a sealing layer. By sealing the via hole a cavity is formed.
  • depositing the metallization layer comprises at least two deposition steps.
  • a first deposition step with enhanced gas flow a first portion of the metallization layer with conformal thickness is deposited.
  • a second deposition step with reduced gas flow a second portion of the metallization layer with non-conformal thickness is deposited.
  • the via hole is sealed by the second portion of the metallization layer.
  • the metallization layer forms a plug that seals the via hole.
  • the gas flow may comprise tungsten hexafluoride (WFe).
  • WFe tungsten hexafluoride
  • the WF 6 flow can be controlled to avoid tungsten deposition at the bottom of the TSV.
  • WF 6 could potentially react into hydrogen (3 ⁇ 4) and hydrogen fluoride (HF).
  • HF hydrogen fluoride
  • sealing the via hole comprises depositing a sealing layer, wherein the sealing layer is an oxide layer.
  • the oxide layer may comprise, for example, S1O 2 .
  • the deposition of the oxide layer may be a non-conformal deposition by means of a CVD process.
  • the oxide layer may have a non-uniform thickness, such that its thickness is high at the via hole opening, but small in the via hole.
  • the oxide layer forms a plug sealing the via hole.
  • the sealing layer is a passivation layer.
  • the passivation layer may comprise S1O 2 and/or SiN.
  • only a few additional deposition steps are required to close the via hole.
  • no additional depositions are necessary, since the deposition of a passivation layer is typically conducted anyway.
  • the method for producing the semiconductor device further comprises a planarizing step.
  • the planarizing step takes place after sealing the via hole.
  • a planar surface is formed by a portion of the insulation layer that is arranged on the rear surface of the substrate, the metallization layer and/or the sealing layer.
  • the planar surface spans the TSV.
  • the thickness of the metallization layer and/or the thickness of the sealing layer at the rear surface of the substrate is reduced.
  • the topography caused by the via hole is neutralized. Further processing on the rear side of the semiconductor device is facilitated.
  • the planarizing step comprises chemical mechanical polishing, CMP.
  • the planarizing step comprises tungsten CMP (W-CMP).
  • W-CMP tungsten CMP
  • the metallization layer typically tungsten
  • the planarizing step comprises CMP, no tungsten loss occurs at the bottom of the via hole, resulting in a more reliable TSV.
  • the method for producing the semiconductor device further comprises depositing a redistribution layer, such that the redistribution layer is electrically connected to the metallization layer and forms at least one contact area at the rear surface of the substrate.
  • the redistribution layer may comprise aluminum (Al) deposited by a sputter process. With the help of the redistribution layer electrical signals can be transmitted and/or redirected.
  • the redistribution layer can be provided with an under bump metallization to which solder bumps can be applied. Conventionally, the under bump metallization is provided by means of electroless nickel (Ni) plating.
  • Ni can diffuse into the aluminum of the redistribution layer causing undesired effects. Since, according to an embodiment, the via hole is closed and covered by a planar surface, also sputter processes can be used to apply the under bump metallization, resulting in a more reliable semiconductor device. Further embodiments of the method become apparent to the skilled reader from the embodiments of the semiconductor device described above.
  • Figure 1 shows an intermediate product of a method of producing a semiconductor device according to an embodiment.
  • Figures 2a-c show an exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
  • Figure 3a-c show another exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
  • Figure 4a-c show another exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
  • Figure 5 shows an embodiment of a sensor device comprising the semiconductor device.
  • FIG. 1 an intermediate product of a method of producing a semiconductor device according to an embodiment is shown.
  • the semiconductor device 1 is shown up-side-down, since the TSV 12 is usually fabricated by backside handling of a semiconductor wafer.
  • the semiconductor device 1 comprises a substrate 2 with a rear surface 2’' and a main surface 2'.
  • the substrate 2 has a main plane of extension.
  • the rear surface 2’’ and the main surface 2’ run in lateral directions x, y, wherein the lateral directions x, y are parallel to the main plane of extension of the substrate 2.
  • An intermetal dielectric 3 is arranged on the main surface 2’ of substrate 2. This means that in a vertical direction z the intermetal dielectric 3 is arranged above the substrate.
  • a metal layer 4 is arranged above the main surface 2’ of the substrate.
  • the metal layer 4 is embedded in the intermetal dielectric 3.
  • the metal layer 4 can be part of a wiring of the semiconductor device 1.
  • Figure 1 shows only one metal layer 4 by way of example. However, the semiconductor device 1 can comprise further metal layers.
  • a via hole 5 reaches from the rear surface 2’’ of the substrate 2 to the metal layer 4.
  • the via hole 5 penetrates the substrate 2 and the intermetal dielectric 3 that is arranged between the substrate and the metal layer 4.
  • An insulation layer 6 is arranged on a sidewall 7 of the via hole 5 formed by the substrate 2 and the intermetal dielectric 3. A portion 6' of the insulation layer 6 also covers the rear surface 2’’ of the substrate 2 outside the via hole 5. A thickness of the insulation layer 6 on the sidewall 7 increases towards the rear surface 2’’ of the substrate, such that the via hole is narrowed.
  • the via hole 5 may be at least partially formed be deep reactive ion etching (DRIE).
  • the insulation layer 6 may be formed by a non- conformal deposition of an oxide, in particular silicon oxide. Thus, an overhang of the insulation layer 6 is formed at the rear surface 2’’ of the substrate 2, that narrows the opening of the via hole 5.
  • a diameter d of the opening is indicated in Fig. 1. The diameter d may differ from one embodiment to another embodiment. For example, the diameter d may be between 0.5 pm and 20 pm.
  • the intermediate product of the semiconductor device shown in Fig. 1 represents the starting point for the process steps described below. This means that each of the processes according to Figs. 2a-c, Figs. 3a-c and Figs. 4a-c relies on the intermediate product shown in Fig. 1.
  • a metallization layer 8 is deposited.
  • the metallization layer 8 comprises a base portion 8' that is in direct contact with the metal layer 4.
  • the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2.
  • the metallization layer 8 comprises a sidewall portion 8''.
  • the sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5.
  • the base portion 8' and the sidewall portion 8'' of the metallization layer 8 form a continuous layer.
  • the metallization layer forms a plug 9 that seals the via hole 5.
  • a cavity 10 is formed.
  • Depositing the metallization layer 8 may comprise at least two deposition steps, wherein in a first deposition step with enhanced gas flow a first portion of the metallization layer
  • a second deposition step with reduced gas flow a second portion of the metallization layer 8 with non-conformal thickness is deposited, such that the via hole is sealed by the second portion.
  • the second portion may mainly form the plug 9.
  • parts of the metallization layer 8 may be deposited on the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 outside the cavity 10. These parts can be removed in a subsequent planarizing step as described in the following.
  • Fig. 2b shows the semiconductor device 1 according to Fig. 2a after the planarizing step.
  • the planarizing step may comprise chemical mechanical polishing, CMP, in particular tungsten CMP, W-CMP.
  • the plug 9 formed by the metallization layer 8.
  • the plug 9 may form a circular area within the planar surface 11.
  • a functional through-substrate-via, TSV 12 is formed.
  • Fig. 2c shows the semiconductor device 1 according to Fig. 2b after further processing steps.
  • the semiconductor device 1 according to Fig. 2c comprises a redistribution layer 13, which may be deposited by means of a sputter process.
  • the redistribution layer 13 shown in Fig. 2c is a planar layer that is arranged on the planar surface 11.
  • the redistribution layer 13 is electrically connected to the metallization layer 8, in particular to the plug 9, and forms at least one contact area 14 at the rear surface 2’’ of the substrate 2.
  • the redistribution layer 13 may be structured by means of conventional photolithography, as no high viscosity photoresist is needed for processing at the planar surface 11. As shown in Fig.
  • the redistribution layer 13 is covered by a passivation layer 15, apart from the contact area 14. At least one opening in the passivation layer 15 provides access to the contact area 14. In places, the passivation layer 15 may further cover the portion 6' of the insulation layer 6 that is arranged at the rear surface 2’’ of the substrate 2.
  • Figs. 3a-c further steps of a method of producing a semiconductor device 1 according to another embodiment are shown. That embodiment may use the intermediate product shown in Fig. 1, or a similar intermediate product. Dimensions may differ between the embodiment according to Figs. 2a-c and the embodiment according to Figs. 3a-c. In particular, the diameter d of the opening of the via hole 5 after the deposition of the insulation layer 6 may differ.
  • a metallization layer 8 is deposited.
  • the metallization layer 8 comprises a base portion 8' that is in direct contact with the exposed metal layer 4.
  • the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2.
  • the metallization layer 8 comprises a sidewall portion 8''.
  • the sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5.
  • a further portion of the metallization layer 8 may be deposited on the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 outside the via hole 5.
  • the base portion 8', the sidewall portion 8’’ and the further portion of the metallization layer 8 may form a continuous layer with uniform thickness.
  • a functional TSV 12 is formed as the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2 and is isolated from the substrate 2, a functional TSV 12 is formed.
  • a sealing layer 16 which may be an oxide layer 16 in this case, is deposited.
  • the deposition of the sealing layer 16 may be a non-conformal deposition. This means that the sealing layer 16 has a non- uniform thickness, such that its thickness is high at the opening of the via hole 5, but small in the via hole 5. However, portions of the sealing layer 16 may also be present in the via hole 5.
  • the sealing layer 16 seals the via hole 5 by forming a plug 9. Thus, a cavity 10 of the TSV 12 is formed.
  • Parts of the sealing layer 16 may be deposited on the further portion of the metallization layer 8 that is arranged at the rear surface 2’’ of the substrate 2 outside the via hole 5. Thus, the sealing layer 16 may completely cover the metallization layer 8.
  • Fig. 3b shows the semiconductor device 1 according to Fig. 3a after a planarizing step.
  • the planarizing step may comprise chemical mechanical polishing, CMP.
  • CMP chemical mechanical polishing
  • Fig. 3c shows the semiconductor device 1 according to Fig. 3b after further processing steps.
  • the semiconductor device 1 according to Fig. 3c comprises a redistribution layer 13 and a passivation 15, correspondingly to the embodiment of Fig. 2c.
  • a redistribution layer 13 and a passivation 15 correspondingly to the embodiment of Fig. 2c.
  • a metallization layer 8 is deposited.
  • the metallization layer 8 comprises a base portion 8' that is in direct contact with the exposed metal layer 4.
  • the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2.
  • the metallization layer 8 comprises a sidewall portion 8''. The sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5.
  • the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 is exposed and the metallization layer 8 is confined to the via hole.
  • the base portion 8' and the sidewall portion 8’’ may form a continuous layer with mainly uniform thickness.
  • the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2 and is isolated from the substrate 2, a functional TSV 12 is formed.
  • a redistribution layer 13 is applied, as shown in Fig. 4b.
  • the redistribution layer 13 covers at least in places the portion 6' of the insulation layer 6 that is arranged at the rear surface 2’’ of the substrate 2.
  • the redistribution layer 13 extends into the via hole 5, such that it at least overlaps the metallization layer 8. In particular, the redistribution layer 13 overlaps with an upper part of the sidewall portion 8’’ of the metallization layer 8 near the via hole opening. Thus, the redistribution layer 13 is electrically connected to the metallization layer 8.
  • the redistribution layer 13 may be deposited by a sputter process. The sputter process results in non-conformal deposition, so that the thickness of the redistribution layer 13 decreases with increasing depth of the via hole 5.
  • a passivation layer 15 is deposited.
  • the passivation layer 15 covers the redistribution layer 13, apart from a contact area 14. This means that at least one opening in the passivation layer 15 provides access to redistribution layer 13. Apart from the contact area 14, the passivation layer 15 may cover the entire rear surface 2’'.
  • the passivation layer 15 functions as sealing layer 15 that seals the via hole 5.
  • the passivation layer 15 forms a plug 9, such that a cavity 10 is formed.
  • portions of the passivation layer 15 may also be present inside the cavity 10 covering the base portion 8' and the sidewall portion 8 of the metallization 8.
  • the passivation layer 15 spans the TSV 12.
  • no planar surface 11 may be formed, but the surface may be recessed at the TSV 12, as shown in Fig. 4c.
  • a sensor device 17 comprising the semiconductor device 1 is shown schematically.
  • the sensor device 17 can be an ambient light sensor, a color sensor, a proximity sensor, a photon counting sensor, and a time-of-flight sensor.
  • the sensor device can be behind an organic light emitting diode display (not shown).

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Abstract

A semiconductor device (1) comprises a substrate (2). A metal layer (4) is arranged on or above a main surface (2') of the substrate (2). The semiconductor device (1) further comprises a through-substrate-via (12), TSV. A via hole (5) of the TSV (12) reaches from a rear surface (2'') of the substrate (2) to the metal layer (4). An insulation layer (6) is arranged on a sidewall (7) of the via hole (5) between the substrate (2) and a metallization layer (8) of the TSV (12), the metallization layer (8) being configured to electrically contact the metal layer (4) from the rear surface (2'') of the substrate (2). A thickness of the insulation layer (6) increases towards the rear surface (2''), such that the via hole (5) is narrowed and is sealed by the metallization layer (8) and/or by a sealing layer (15, 16), thus forming a cavity (10).

Description

Description
SEMICONDUCTOR DEVICE WITH SEALED THROUGH-SUBSTRATE VIA AND METHOD FOR PRODUCING THEREOF
The present invention relates to a semiconductor device, a sensor device comprising a semiconductor device and a method for producing a semiconductor device. The semiconductor device comprises a sealed through-substrate-via.
BACKGROUND OF THE INVENTION
For three-dimensional integration of semiconductor devices through-substrate-vias (TSVs) are used. A TSV is an electric interconnection through a semiconductor substrate. It comprises a via hole penetrating the substrate and a metallization arranged in the via hole.
A TSV can be produced by first forming a metal layer in an intermetal dielectric on a main surface of the substrate. Then, a via hole is etched from a rear surface through the substrate, until the intermetal dielectric is reached. An insulating layer is arranged on a sidewall and a bottom of the via hole. The insulation layer and the intermetal dielectric are removed from the bottom of the via hole by an anisotropic etching step, such that the insulation layer remains on the sidewall to cover the semiconductor material. After that etching step, the metal layer is exposed at the bottom of the via hole. A metallization can be applied in the via hole, such that it contacts the metal layer and forms an electric interconnection. Conventionally, the metallization completely fills the via hole. For example, the via hole is completely filled by a copper metallization. However, this approach comes with several drawbacks: On the one side, as the via hole is completely filled by the metallization, the material consumption is high, leading to high production costs. On the other side, the semiconductor device is prone to stress- induced cracks, e.g. due to differences in the coefficients of thermal extension. Moreover, in some cases, e.g. for CMOS fabrication, a copper metallization may be undesired due to contamination reasons.
According to another approach, a metallization layer is applied, that only covers the sidewall and the bottom of the via hole. This means that the remaining via hole remains void. The metallization layer may comprise tungsten, which can be deposited by chemical vapour deposition, CVD, in a conformal way. Though the above-mentioned drawbacks are overcome by this approach, other issues arise: Due to the open TSV, the semiconductor device is vulnerable to particles, plasma reactants, wet chemicals and moisture during fabrication. Moreover, careful handling is necessary to avoid micro cracks at the bottom of the TSV. Due to the topography dedicated lithography steps are required for further processing.
Therefore, an object to be achieved is to provide an improved concept for TSV technology. According to the improved concept, the reliability of a TSV is enhanced and further processing after forming the TSV is facilitated. This object is achieved with the subject-matter of the independent claims. Further developments and embodiments are described in dependent claims.
SUMMARY OF THE INVENTION
In an embodiment, a semiconductor device comprises a substrate with a rear surface and a main surface. A metal layer is arranged on or above the main surface of the substrate. The semiconductor device further comprises a through-substrate-via, TSV, comprising a via hole, an insulation layer and a metallization layer. The via hole reaches from the rear surface of the substrate to the metal layer. The insulation layer is arranged on a sidewall of the via hole between the substrate and the metallization layer. The metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate. A thickness of the insulation layer increases towards the rear surface of the substrate, such that the via hole is narrowed.
According to at least one embodiment, the via hole is sealed by the metallization layer. Alternatively or additionally, the via hole is sealed by a sealing layer. By sealing the via hole a cavity is formed.
The substrate has a main plane of extension. The main surface and the rear surface of the substrate run in lateral directions, wherein lateral direction are parallel to the main plane of extension of the substrate. The substrate may comprise a semiconductor material, e.g. silicon (Si).
Circuits and other electrical components can be integrated in the substrate. For example, a CMOS circuit and/or sensor elements are arranged in the substrate. The metal layer may especially be part of a wiring, which may comprise several metal layers, for instance. The metal layer may comprise aluminum (Al). The metal layer may be doped with copper (Cu) and/or silicon (Si). Thus, the metal layer may form an AlSi or AlCu layer. Metal layers of a wiring, which are embedded in an intermetal dielectric, are conventionally provided with barrier layers, in particular in CMOS technology, in order to enhance the adhesion of the dielectric material to the metal layers and in order to prevent diffusion processes like electromigration. Thus, the metal layer may be sandwiched between two barrier layers on top and bottom of the metal layer, respectively. The barrier layers may comprise titanium (Ti) and/or titanium nitride (TiN).
The TSV reaches from the rear surface of the substrate to the metal layer. This means that the via hole of the TSV completely penetrates the substrate opposite the metal layer. Thus, the TSV has a vertical extent from the rear surface of the substrate to the metal layer. The vertical direction refers to a direction which runs perpendicular to the main plane of extension of the substrate. The TSV is aligned with the metal layer. A lateral extent of the TSV is smaller than a lateral extent of the metal layer.
The insulating layer is arranged on a sidewall of the via hole. Thus, the substrate is electrically isolated from the metallization layer of the TSV. The insulating layer comprises, for example, S1O2. The insulating layer covers the sidewall of the via hole. A portion of the insulation layer may typically also cover the rear surface of the substrate outside the via hole. By means of the insulation layer short circuits are avoided. The substrate can be at an electric potential that is different from an electric potential of the TSV.
The thickness of the insulation layer on the sidewall of the via hole increases towards the rear surface of the substrate. In other words, the insulation layer is a non-conformal layer, i.e. its thickness is not uniform. Thus, an opening of the via hole narrows. A diameter of the opening after the deposition of the insulation layer could be at least 0.5 pm and at most 20 pm. Alternatively, the diameter of the opening after the deposition of the insulation layer could be at least 1 pm and at most 10 pm.
For example, in an embodiment, where the via hole is sealed by the metallization layer, the diameter of the opening after the deposition of the insulation layer could be up to 1 pm, 2 pm or 3 pm, respectively. On the other side, in an embodiment, where the via hole is sealed by a dedicated sealing layer, the diameter of the opening after the deposition of the insulation layer could be up to 4 pm, 10 pm or even 20 pm, respectively. By means of the narrowing sealing the via hole in a subsequent deposition step is facilitated .
The metallization layer may comprise tungsten (W). The metallization layer of the TSV may comprise a sidewall portion covering the insulation layer on the sidewall of the via hole. This means that the insulating layer separates the substrate from the metallization. The metallization layer may further comprise a base portion covering the exposed metal layer, thus forming an electrical contact. The metallization layer can be a conformal layer. Thus, it may have a uniform thickness. In this case, the via hole may be sealed by means of the sealing layer. However, it is also possible that the metallization layer is a non-conformal layer. This is especially true for such embodiments where the via hole is sealed by the metallization layer. In these cases, the metallization layer may be thicker at the rear surface of the substrate than at the bottom of the via hole.
The sidewall portion and the base portion of the metallization layer ensure a continuous metallization from the rear surface of the substrate to the metal layer. The remaining via hole is void/ not filled. This can be beneficial in view of thermal and mechanical stress, and material consumption.
By sealing the via hole the via hole is closed. Thus, a cavity within the TSV is formed. The cavity may be filled with air or gas. The closed via hole leads to a higher structural stability. Moreover, the semiconductor device is protected against moisture, particles, dry etch reactants and other chemicals. If the via hole were open, particles and the like could deposit in the via hole and damage the metallization layer.
In an embodiment, the semiconductor device further comprises an intermetal dielectric arranged on the main surface of substrate. This can mean that in a vertical direction, the intermetal dielectric is arranged above the substrate. The intermetal dielectric can be an oxide, e.g. silicon oxide (S1O2) · The metal layer is embedded in the intermetal dielectric. By means of the intermetal dielectric a wiring for circuit and sensor components can be provided. In an embodiment, the metallization layer forms a plug at the rear surface of the substrate that seals the via hole. Alternatively, the sealing layer forms a plug that seals the via hole at the rear surface of the substrate. The plug closes the via hole, such that the structural stability is enhanced and the via hole is protected against moisture, particles, dry etch reactants and other chemicals.
In an embodiment, a portion of the insulation layer is arranged on the rear surface of the substrate. By means of the insulation layer the substrate is electrically isolated. Thus, a contact area can be arranged at the rear surface of the substrate.
In an embodiment, a planar surface is formed by the portion of the insulation layer arranged on the rear surface of the substrate, the metallization layer and/or the sealing layer. The planar surface spans the TSV.
The planar surface may be parallel to the rear surface of the substrate. In the embodiment, where the metallization layer forms the plug sealing the via hole, the metallization layer may form a circular area within the planar surface. Alternatively, when the sealing layer forms the plug sealing the via hole, the metallization layer forms a ring-shaped area within the planar surface.
The planar surface has the effect of leveling the topography caused by the via hole. As a result, further processing on the rear side of the semiconductor device is facilitated. In particular, it is possible to use standard lithography steps for further processing. No high viscosity photoresist is needed to cover the via hole. This reduces the production costs. One or more redistribution layers can be deposited on the planar surface by a CMOS backend process flow. Moreover, the use of standard steps for an under bump metallization is allowed .
In an embodiment, the semiconductor device further comprises a redistribution layer. The redistribution layer is electrically connected to the metallization layer and forms at least one contact area at the rear surface of the substrate .
The redistribution layer can be a planar layer deposited on the planar surface. The redistribution layer can be patterned by standard lithography. Since, according to one embodiment, the metallization layer may be part of the planar surface, the redistribution layer is in direct contact with the metallization layer.
According to another embodiment, the redistribution layer overlaps the sidewall portion of the metallization layer.
This may mean that the redistribution layer extends into the via hole so that at least part of the sidewall portion of the metallization layer is covered by it. In this embodiment, the via hole is sealed by the sealing layer, which may be a passivation layer in this case.
The redistribution layer may comprise aluminum (Al). Advantageously, the redistribution layer does not contain tungsten, since large-area surfaces consisting of tungsten exhibit high layer stress, which could lead to delamination or chipping. With the help of the redistribution layer electrical signals can be transmitted and/or redirected. The semiconductor device can comprise further redistribution layers, such that the redistribution layer and the further redistribution layers form a wiring at the rear surface of the substrate. Moreover, the redistribution layer can be provided with an under bump metallization to which solder bumps can be applied.
In an embodiment, the redistribution layer is covered by a passivation layer, apart from the contact area. The passivation layer may comprise a dielectric material, for example, silicon oxide and/or silicon nitride (SiN). At least one opening in the passivation layer provides access to the contact area at the rear surface of the substrate. Thus, a solder bump, bond wire or the like can be applied. The passivation layer protects the semiconductor device from physical damage like scratches and/or moisture induced damage.
In an embodiment, the sealing layer comprises an oxide layer. Alternatively, the sealing layer comprises a passivation layer. If the sealing layer is an oxide layer, it may be a non-conformal oxide layer. Thus, the oxide layer may have a non-uniform thickness, such that its thickness is high at the via hole opening, but small in the via hole. Thus, the oxide layer forms a plug sealing the via hole. If the sealing layer is a passivation layer, it may be the same passivation layer that covers the redistribution layer. A portion of the passivation layer may be present in the via hole covering the metallization layer. Advantageously, the via hole can be sealed with a few additional or typically already existing layers.
Furthermore, a sensor device is provided that comprises the semiconductor device. This means that all features disclosed for the semiconductor device are also disclosed for and applicable to the sensor device and vice-versa.
In an embodiment, the sensor device is an ambient light sensor. In another embodiment, the sensor device is a color sensor. In another embodiment, the sensor device is a proximity sensor. In another embodiment, the sensor device is a photon counting sensor. In another embodiment, the sensor device is a time-of-flight sensor. According to an aspect of the invention, the sensor device comprises a sensor behind an organic light emitting diode (OLED) display.
The mobile handset market will continue to follow the trend to ever higher screen-to-body ratios and ultimately to all screen, bezel-less smartphones. For that purpose, sensor elements comprised by such devices have to be highly integrated, such that 3D-integration techniques are needed. Advantageously, the sensor devices used comprise semiconductor devices with TSVs, through which electrical contacting from the rear surface is possible. A terminal device, such as a smartphone, can thus be designed to be very thin. The front of the terminal device can, for example, be completely filled by a screen, e.g. an OLED display.
Furthermore, a method for producing a semiconductor device is provided. All features disclosed for the semiconductor device and the sensor device are also disclosed for the method for producing a semiconductor device and vice-versa.
According to at least one embodiment, the method comprises providing a substrate with a rear surface and a main surface. The substrate may comprise a semiconductor material, e.g. silicon (Si). The method further comprises arranging a metal layer on or above the main surface of substrate. For example, an intermetal dielectric is arranged on the main surface of the substrate, in which the metal layer is embedded. The intermetal dielectric can be an oxide, e.g. silicon oxide (S1O2) · The intermetal dielectric can be deposited on the substrate in one or more deposition steps, e.g. via chemical vapor deposition (CVD). The metal layer may comprise aluminum (Al). Besides, the metal layer may comprise barrier layers. The barrier layers may comprise titanium (Ti) and/or titanium nitride (TiN). The metal layer including the barrier layers may be deposited by sputter processes between two subsequent deposition steps for the intermetal dielectric. Patterning of the metal layer can be conducted by etching.
The method further comprises forming a through-substrate-via, TSV. Forming the TSV comprises forming a via hole from the rear surface of the substrate to the metal layer. This can mean that the via hole is formed by removing the substrate opposite the metal layer. The via hole can be formed by deep reactive-ion etching (DRIE) into the silicon substrate. The DRIE process can be controlled by time or by use of an etch stop layer. The DRIE process is also called Bosch process. DRIE is a fast and efficient anisotropic etching technique.
The via hole may be extended by removing the intermetal dielectric up to the metal layer. This means that a further etching step removes the intermetal dielectric between the substrate and the metal layer. For the second etching step, the metal layer can be used as etch stop layer. The further etching step exposes the metal layer. Forming the TSV further comprises depositing an insulation layer on a sidewall of the via hole. The insulation layer may be deposited after removing the intermetal dielectric up to the metal layer. The insulating layer comprises, for example, SiCh. The deposition of the insulating layer can be conducted by CVD. The insulating layer covers the sidewall of the via hole. Portions of the insulation layer may typically also cover the bottom of the via hole, i.e. the metal layer, and the rear surface of the substrate outside the via hole. After the deposition, the insulating layer is removed from the bottom of the via hole by an anisotropic etching step, such that the metal layer is exposed.
In an alternative embodiment, the insulating layer is deposited after removing the substrate opposite the metal layer and before removing the intermetal dielectric. In this embodiment, the insulation layer can be removed from the bottom of the via hole in the same anisotropic etching step that is also used for removing the intermetal dielectric.
The insulation layer is deposited such that a thickness of the insulation layer on the sidewall of the via hole increases towards the rear surface of the substrate. Thus, the via hole is narrowed towards the rear surface. This can be achieved by a non-conformal deposition. It is also possible that more than one deposition steps are used to form the insulation layer. By means of the insulation layer the substrate is electrically isolated and short circuits are avoided. By narrowing the via hole towards the rear surface, the via hole can be sealed in a subsequent deposition step.
Forming the TSV further comprises depositing a metallization layer. The metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate. The metallization layer may comprise more than one metal and may be applied as a sequence of metal layers, which may include titanium and/or tungsten layers, for instance. A sidewall portion of the metallization layer covers the sidewall of the via hole and a base portion of the metallization layer covers the exposed metal layer. The metallization is isolated from the substrate by the insulation layer. The metallization is in direct contact with the exposed metal layer.
Forming the TSV further comprises sealing the via hole by the metallization layer. Alternatively or additionally, the via hole is sealed by the deposition of a sealing layer. By sealing the via hole a cavity is formed.
In an embodiment, depositing the metallization layer comprises at least two deposition steps. In a first deposition step with enhanced gas flow a first portion of the metallization layer with conformal thickness is deposited. In a second deposition step with reduced gas flow a second portion of the metallization layer with non-conformal thickness is deposited. The via hole is sealed by the second portion of the metallization layer. Thus, the metallization layer forms a plug that seals the via hole.
The gas flow may comprise tungsten hexafluoride (WFe). Advantageously, the WF6 flow can be controlled to avoid tungsten deposition at the bottom of the TSV. As a consequence, only low amount of process gases reach the TSV bottom. WF6 could potentially react into hydrogen (¾) and hydrogen fluoride (HF). Thus, after the sealing process steps only HF and ¾ can remain inside the TSV due to the deposition processes. Though it has been found that the metallization layer (typically tungsten) is very robust against HF, the HF concentration in the via hole can be reduced by controlling the gas flow.
In an embodiment, sealing the via hole comprises depositing a sealing layer, wherein the sealing layer is an oxide layer. The oxide layer may comprise, for example, S1O2. The deposition of the oxide layer may be a non-conformal deposition by means of a CVD process. Thus, the oxide layer may have a non-uniform thickness, such that its thickness is high at the via hole opening, but small in the via hole.
Thus, the oxide layer forms a plug sealing the via hole. Alternatively, the sealing layer is a passivation layer. The passivation layer may comprise S1O2 and/or SiN. Advantageously, only a few additional deposition steps are required to close the via hole. Alternatively, no additional depositions are necessary, since the deposition of a passivation layer is typically conducted anyway.
In an embodiment, the method for producing the semiconductor device further comprises a planarizing step. The planarizing step takes place after sealing the via hole. By the planarizing step a planar surface is formed by a portion of the insulation layer that is arranged on the rear surface of the substrate, the metallization layer and/or the sealing layer. The planar surface spans the TSV.
By means of the planarizing step the thickness of the metallization layer and/or the thickness of the sealing layer at the rear surface of the substrate is reduced. Advantageously, the topography caused by the via hole is neutralized. Further processing on the rear side of the semiconductor device is facilitated.
In an embodiment, the planarizing step comprises chemical mechanical polishing, CMP. In particular, the planarizing step comprises tungsten CMP (W-CMP). Conventionally, the metallization layer (typically tungsten) is removed from the rear surface of the substrate by means of an etching step. However, this procedure also attacks the metallization layer at the bottom of the TSV. Since, according to the disclosure, the TSV is sealed and the planarizing step comprises CMP, no tungsten loss occurs at the bottom of the via hole, resulting in a more reliable TSV.
In an embodiment, the method for producing the semiconductor device further comprises depositing a redistribution layer, such that the redistribution layer is electrically connected to the metallization layer and forms at least one contact area at the rear surface of the substrate.
The redistribution layer may comprise aluminum (Al) deposited by a sputter process. With the help of the redistribution layer electrical signals can be transmitted and/or redirected. The redistribution layer can be provided with an under bump metallization to which solder bumps can be applied. Conventionally, the under bump metallization is provided by means of electroless nickel (Ni) plating.
However, Ni can diffuse into the aluminum of the redistribution layer causing undesired effects. Since, according to an embodiment, the via hole is closed and covered by a planar surface, also sputter processes can be used to apply the under bump metallization, resulting in a more reliable semiconductor device. Further embodiments of the method become apparent to the skilled reader from the embodiments of the semiconductor device described above.
BRIEF DESCRIPTION OF THE DRAWINGS
The following description of figures may further illustrate and explain aspects of the improved semiconductor device and the method of producing the same. Components and parts of the semiconductor device that are functionally identical or have an identical effect are denoted by identical reference symbols. Identical or effectively identical components and parts might be described only with respect to the figures where they occur first. Their description is not necessarily repeated in successive figures.
Figure 1 shows an intermediate product of a method of producing a semiconductor device according to an embodiment.
Figures 2a-c show an exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
Figure 3a-c show another exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
Figure 4a-c show another exemplary embodiment of a method of producing a semiconductor device based on the intermediate product of Fig. 1.
Figure 5 shows an embodiment of a sensor device comprising the semiconductor device.
In Figure 1 an intermediate product of a method of producing a semiconductor device according to an embodiment is shown. The semiconductor device 1 is shown up-side-down, since the TSV 12 is usually fabricated by backside handling of a semiconductor wafer.
The semiconductor device 1 comprises a substrate 2 with a rear surface 2’' and a main surface 2'. The substrate 2 has a main plane of extension. The rear surface 2’’ and the main surface 2’ run in lateral directions x, y, wherein the lateral directions x, y are parallel to the main plane of extension of the substrate 2.
An intermetal dielectric 3 is arranged on the main surface 2’ of substrate 2. This means that in a vertical direction z the intermetal dielectric 3 is arranged above the substrate.
A metal layer 4 is arranged above the main surface 2’ of the substrate. The metal layer 4 is embedded in the intermetal dielectric 3. The metal layer 4 can be part of a wiring of the semiconductor device 1. Figure 1 shows only one metal layer 4 by way of example. However, the semiconductor device 1 can comprise further metal layers.
A via hole 5 reaches from the rear surface 2’’ of the substrate 2 to the metal layer 4. The via hole 5 penetrates the substrate 2 and the intermetal dielectric 3 that is arranged between the substrate and the metal layer 4.
An insulation layer 6 is arranged on a sidewall 7 of the via hole 5 formed by the substrate 2 and the intermetal dielectric 3. A portion 6' of the insulation layer 6 also covers the rear surface 2’’ of the substrate 2 outside the via hole 5. A thickness of the insulation layer 6 on the sidewall 7 increases towards the rear surface 2’’ of the substrate, such that the via hole is narrowed. The via hole 5 may be at least partially formed be deep reactive ion etching (DRIE). The insulation layer 6 may be formed by a non- conformal deposition of an oxide, in particular silicon oxide. Thus, an overhang of the insulation layer 6 is formed at the rear surface 2’’ of the substrate 2, that narrows the opening of the via hole 5. A diameter d of the opening is indicated in Fig. 1. The diameter d may differ from one embodiment to another embodiment. For example, the diameter d may be between 0.5 pm and 20 pm.
The intermediate product of the semiconductor device shown in Fig. 1 represents the starting point for the process steps described below. This means that each of the processes according to Figs. 2a-c, Figs. 3a-c and Figs. 4a-c relies on the intermediate product shown in Fig. 1.
In Figs. 2a-c further steps of a method of producing a semiconductor device according to one embodiment are shown. According to Fig. 2a, a metallization layer 8 is deposited. The metallization layer 8 comprises a base portion 8' that is in direct contact with the metal layer 4. Thus, the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2. Moreover, the metallization layer 8 comprises a sidewall portion 8''. The sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5. The base portion 8' and the sidewall portion 8'' of the metallization layer 8 form a continuous layer. At the rear surface 2’’ of the substrate 2 the metallization layer forms a plug 9 that seals the via hole 5. Thus, a cavity 10 is formed.
Depositing the metallization layer 8 may comprise at least two deposition steps, wherein in a first deposition step with enhanced gas flow a first portion of the metallization layer
8 with conformal thickness is deposited, such that mainly the base portion 8' and the sidewall portion 8'' of the metallization layer 8 is formed. In a second deposition step with reduced gas flow a second portion of the metallization layer 8 with non-conformal thickness is deposited, such that the via hole is sealed by the second portion. The second portion may mainly form the plug 9.
By the above-mentioned deposition steps parts of the metallization layer 8 may be deposited on the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 outside the cavity 10. These parts can be removed in a subsequent planarizing step as described in the following.
Fig. 2b shows the semiconductor device 1 according to Fig. 2a after the planarizing step. The planarizing step may comprise chemical mechanical polishing, CMP, in particular tungsten CMP, W-CMP. By means of the planarizing step the metallization layer 8 at the rear surface 2’’ of the substrate 2 outside the cavity 10 is removed/milled until the portion 6' of the insulation 6 is exposed. Thus, a planar surface 11 is formed by the portion 6' of the insulation layer 6 and the metallization layer 8, in particular the plug
9 formed by the metallization layer 8. In a plan view, the plug 9 may form a circular area within the planar surface 11. By means of the metallization layer 8, that electrically contacts the metal layer 4 and is isolated from the substrate 2, a functional through-substrate-via, TSV 12, is formed.
Fig. 2c shows the semiconductor device 1 according to Fig. 2b after further processing steps. The semiconductor device 1 according to Fig. 2c comprises a redistribution layer 13, which may be deposited by means of a sputter process. The redistribution layer 13 shown in Fig. 2c is a planar layer that is arranged on the planar surface 11. The redistribution layer 13 is electrically connected to the metallization layer 8, in particular to the plug 9, and forms at least one contact area 14 at the rear surface 2’’ of the substrate 2. The redistribution layer 13 may be structured by means of conventional photolithography, as no high viscosity photoresist is needed for processing at the planar surface 11. As shown in Fig. 2c, the redistribution layer 13 is covered by a passivation layer 15, apart from the contact area 14. At least one opening in the passivation layer 15 provides access to the contact area 14. In places, the passivation layer 15 may further cover the portion 6' of the insulation layer 6 that is arranged at the rear surface 2’’ of the substrate 2.
In Figs. 3a-c further steps of a method of producing a semiconductor device 1 according to another embodiment are shown. That embodiment may use the intermediate product shown in Fig. 1, or a similar intermediate product. Dimensions may differ between the embodiment according to Figs. 2a-c and the embodiment according to Figs. 3a-c. In particular, the diameter d of the opening of the via hole 5 after the deposition of the insulation layer 6 may differ. According to Fig. 3a, a metallization layer 8 is deposited. The metallization layer 8 comprises a base portion 8' that is in direct contact with the exposed metal layer 4. Thus, the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2. Moreover, the metallization layer 8 comprises a sidewall portion 8''. The sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5. A further portion of the metallization layer 8 may be deposited on the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 outside the via hole 5. The base portion 8', the sidewall portion 8’’ and the further portion of the metallization layer 8 may form a continuous layer with uniform thickness. As the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2 and is isolated from the substrate 2, a functional TSV 12 is formed.
Furthermore, a sealing layer 16, which may be an oxide layer 16 in this case, is deposited. As shown in Fig. 3a, the deposition of the sealing layer 16 may be a non-conformal deposition. This means that the sealing layer 16 has a non- uniform thickness, such that its thickness is high at the opening of the via hole 5, but small in the via hole 5. However, portions of the sealing layer 16 may also be present in the via hole 5. The sealing layer 16 seals the via hole 5 by forming a plug 9. Thus, a cavity 10 of the TSV 12 is formed.
Parts of the sealing layer 16 may be deposited on the further portion of the metallization layer 8 that is arranged at the rear surface 2’’ of the substrate 2 outside the via hole 5. Thus, the sealing layer 16 may completely cover the metallization layer 8.
Fig. 3b shows the semiconductor device 1 according to Fig. 3a after a planarizing step. The planarizing step may comprise chemical mechanical polishing, CMP. By means of the planarizing step these parts of the sealing layer 16 and the metallization layer 8 are removed, that are arranged on the portion 6 of the insulation layer 6 outside the via hole 5. The parts of the sealing layer 16 and the metallization layer 8 are removed/ milled until the portion 6 of the insulation 6 is exposed. Thus, a planar surface 11 is formed by the portion 6 of the insulation layer 6, the metallization layer 8, and the sealing layer 16 forming the plug 9. In a plan view, the metallization layer 8 forms a ring-shaped area within the planar surface 11.
Fig. 3c shows the semiconductor device 1 according to Fig. 3b after further processing steps. The semiconductor device 1 according to Fig. 3c comprises a redistribution layer 13 and a passivation 15, correspondingly to the embodiment of Fig. 2c. Thus, for further explanation it is referred to the above-mentioned description.
In Figs. 4a-c further steps of a method of producing a semiconductor device 1 according to another embodiment are shown. Again, that embodiment may also rely on the intermediate product shown in Fig. 1, or a similar intermediate product. However, dimensions, in particular the diameter d of the opening of the via hole 5 after the deposition of the insulation layer 6, may differ. According to Fig. 4a, a metallization layer 8 is deposited. The metallization layer 8 comprises a base portion 8' that is in direct contact with the exposed metal layer 4. Thus, the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2. Moreover, the metallization layer 8 comprises a sidewall portion 8''. The sidewall portion 8'' covers the insulation layer 6 on the sidewall 7 of the via hole 5.
A further portion (not shown) of the metallization layer 8, that may be deposited on the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 outside the via hole 5, can be removed by means of an etching step. Thus, the portion 6' of the insulation layer 6 at the rear surface 2’’ of the substrate 2 is exposed and the metallization layer 8 is confined to the via hole. The base portion 8' and the sidewall portion 8’’ may form a continuous layer with mainly uniform thickness. As the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2’’ of the substrate 2 and is isolated from the substrate 2, a functional TSV 12 is formed.
In a next step, a redistribution layer 13 is applied, as shown in Fig. 4b. The redistribution layer 13 covers at least in places the portion 6' of the insulation layer 6 that is arranged at the rear surface 2’’ of the substrate 2.
Moreover, the redistribution layer 13 extends into the via hole 5, such that it at least overlaps the metallization layer 8. In particular, the redistribution layer 13 overlaps with an upper part of the sidewall portion 8’’ of the metallization layer 8 near the via hole opening. Thus, the redistribution layer 13 is electrically connected to the metallization layer 8. The redistribution layer 13 may be deposited by a sputter process. The sputter process results in non-conformal deposition, so that the thickness of the redistribution layer 13 decreases with increasing depth of the via hole 5.
In a next step according to Fig. 4c, a passivation layer 15 is deposited. The passivation layer 15 covers the redistribution layer 13, apart from a contact area 14. This means that at least one opening in the passivation layer 15 provides access to redistribution layer 13. Apart from the contact area 14, the passivation layer 15 may cover the entire rear surface 2’'.
Moreover, according to that embodiment, the passivation layer 15 functions as sealing layer 15 that seals the via hole 5. Thus, the passivation layer 15 forms a plug 9, such that a cavity 10 is formed. As the passivation layer 15 is typically deposited by means of a chemical vapor deposition, portions of the passivation layer 15 may also be present inside the cavity 10 covering the base portion 8' and the sidewall portion 8 of the metallization 8. The passivation layer 15 spans the TSV 12. However, according to this embodiment, no planar surface 11 may be formed, but the surface may be recessed at the TSV 12, as shown in Fig. 4c.
In Figure 5 a sensor device 17 comprising the semiconductor device 1 is shown schematically. The sensor device 17 can be an ambient light sensor, a color sensor, a proximity sensor, a photon counting sensor, and a time-of-flight sensor. The sensor device can be behind an organic light emitting diode display (not shown). The embodiments of the semiconductor device 1 and the method of producing the semiconductor device 1 disclosed herein have been discussed for the purpose of familiarizing the reader with novel aspects of the idea. Although preferred embodiments have been shown and described, many changes, modifications, equivalents and substitutions of the disclosed concepts may be made by one having skill in the art without unnecessarily departing from the scope of the claims.
It will be appreciated that the disclosure is not limited to the disclosed embodiments and to what has been particularly shown and described hereinabove. Rather, features recited in separate dependent claims or in the description may advantageously be combined. Furthermore, the scope of the disclosure includes those variations and modifications, which will be apparent to those skilled in the art and fall within the scope of the appended claims.
The term "comprising", insofar it was used in the claims or in the description, does not exclude other elements or steps of a corresponding feature or procedure. In case that the terms "a" or "an" were used in conjunction with features, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.
This patent application claims the priority of German patent application 102021109045.8, the disclosure content of which is hereby incorporated by reference. Reference symbols
1 semiconductor device
2 substrate
2 main surface of substrate
2 rear surface of substrate
3 intermetal dielectric
4 metal layer
5 via hole
6 insulation layer
6 portion of the insulation layer
7 sidewall of via hole
8 metallization layer
8 base portion of metallization layer
8 sidewall portion of metallization layer
9 plug
10 cavity 11 planar surface 12 through-substrate-via
13 redistribution layer
14 contact area
15 passivation layer, sealing layer
16 oxide layer, sealing layer 17 sensor device d diameter x, y lateral directions z vertical direction

Claims

Claims
1. Semiconductor device (1), comprising: a substrate (2) with a rear surface (2,f) and a main surface (2'), a metal layer (4) arranged on or above the main surface (2') of the substrate (2), and a through-substrate-via (12), TSV, comprising a via hole (5), an insulation layer (6) and a metallization layer (8), the via hole (5) reaching from the rear surface (2,f) of the substrate (2) to the metal layer (4), the insulation layer (6) being arranged on a sidewall (7) of the via hole (5) between the substrate (2) and the metallization layer (8), the metallization layer (8) being configured to electrically contact the metal layer (4) from the rear surface (2,f) of the substrate (2), wherein a thickness of the insulation layer (6) increases towards the rear surface (2,f) of the substrate (2), such that the via hole (5) is narrowed and is sealed by the metallization layer (8) and/or by a sealing layer (15,
16), thus forming a cavity (10).
2. Semiconductor device (1) according to the preceding claim, further comprising an intermetal dielectric (3) arranged on the main surface (2') of substrate (2), wherein the metal layer (4) is embedded in the intermetal dielectric (3).
3. Semiconductor device (1) according to the preceding claim, wherein at the rear surface (2,f) of the substrate (2) the metallization layer (8) or the sealing layer (15, 16) forms a plug (9) that seals the via hole (5).
4. Semiconductor device (1) according to one of the preceding claims, wherein a portion (6') of the insulation layer (6) is arranged on the rear surface (2,f) of the substrate (2).
5. Semiconductor device (1) according to the preceding claim, wherein a planar surface (11) is formed by the portion of the insulation layer (6') arranged on the rear surface (2,f) of the substrate (2), the metallization layer (8) and/or the sealing layer (15, 16), the planar surface (11) spanning the TSV (12).
6. Semiconductor device (1) according to one of the preceding claims, further comprising a redistribution layer (13), the redistribution layer (13) being electrically connected to the metallization layer (8) and forming at least one contact area
(14) at the rear surface (2,f) of the substrate (2).
7. Semiconductor device (1) according to the preceding claim, wherein apart from the contact area (14) the redistribution layer (13) is covered by a passivation layer (15).
8. Semiconductor device (1) according to one of the preceding claims, wherein the sealing layer (15, 16) comprises one of an oxide layer (16) and a passivation layer (15).
9. Sensor device (17) comprising the semiconductor device (1) according to one of the preceding claims, wherein the sensor device (17) is in particular one of an ambient light sensor, a color sensor, a proximity sensor, a photon counting sensor and a time-of-flight sensor behind an organic light emitting diode display.
10. Method for producing a semiconductor device (1), the method comprising: providing a substrate (2) with a rear surface (2,f) and a main surface (2'), arranging a metal layer (4) on or above the main surface (2') of substrate (2), forming a through-substrate-via (12), TSV, comprising
- forming a via hole (5) from the rear surface (2,f) of the substrate (2) to the metal layer (4),
- depositing an insulation layer (6) on a sidewall (7) of the via hole (5), a thickness of the insulation layer (6) increasing towards the rear surface (2,f) of the substrate (2), such that the via hole (5) is narrowed,
- depositing a metallization layer (8), the metallization layer (8) being configured to electrically contact the metal layer (4) from the rear surface (2,f) of the substrate (2),
- sealing the via hole (5) by the metallization layer (8) and/or by a sealing layer (15, 16), thus forming a cavity (10).
11. Method according to the preceding claim, wherein depositing the metallization layer (8) comprises at least two deposition steps, wherein in a first deposition step with enhanced gas flow a first portion of the metallization layer (8) with conformal thickness is deposited, and wherein in a second deposition step with reduced gas flow a second portion of the metallization layer (8) with non-conformal thickness is deposited, such that the via hole (5) is sealed by the second portion.
12. Method according to claim 10, wherein sealing the via hole (5) comprises depositing the sealing layer (15, 16), that is one of an oxide layer (16) and a passivation layer (15).
13. Method according to one of the preceding claims, further comprising a planarizing step after sealing the via hole (5), such that a planar surface (11) is formed by a portion (6') of the insulation layer (6) arranged on the rear surface (2,f) of the substrate (2), the metallization layer (8) and/or the sealing layer (15, 16), the planar surface (11) spanning the TSV (12).
14. Method according to the preceding claim, wherein the planarizing step comprises chemical mechanical polishing,
CMP.
15. Method according to one of the preceding claims, further comprising depositing a redistribution layer (13), such that the redistribution layer (13) is electrically connected to the metallization layer (8) and forms at least one contact area (14) at the rear surface (2,f) of the substrate (2).
PCT/EP2022/056006 2021-04-12 2022-03-09 Semiconductor device with sealed through-substrate via and method for producing thereof WO2022218610A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115621197A (en) * 2022-11-22 2023-01-17 湖北三维半导体集成创新中心有限责任公司 Through silicon via interconnected cavity structure and forming method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090302480A1 (en) * 2008-06-06 2009-12-10 Albert Birner Through Substrate Via Semiconductor Components
US20150214134A1 (en) * 2014-01-30 2015-07-30 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method
US20200083273A1 (en) * 2016-12-26 2020-03-12 Sony Semiconductor Solutions Corporation Semiconductor device, method of manufacturing semiconductor device, and solid-state image sensor
EP3790046A1 (en) * 2019-09-03 2021-03-10 Ams Ag Through-substrate via and method for manufacturing a through-substrate via

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5600919B2 (en) * 2009-10-06 2014-10-08 セイコーエプソン株式会社 Semiconductor device
US9455178B2 (en) * 2014-03-14 2016-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US9502293B2 (en) * 2014-11-18 2016-11-22 Globalfoundries Inc. Self-aligned via process flow
US10541204B2 (en) * 2015-10-20 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnection structure and method of forming the same
US10157777B2 (en) * 2016-05-12 2018-12-18 Globalfoundries Inc. Air gap over transistor gate and related method
US20180012791A1 (en) * 2016-07-06 2018-01-11 Globalfoundries Inc. Interconnects with inner sacrificial spacers
US10923565B2 (en) * 2018-09-27 2021-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Self-aligned contact air gap formation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090302480A1 (en) * 2008-06-06 2009-12-10 Albert Birner Through Substrate Via Semiconductor Components
US20150214134A1 (en) * 2014-01-30 2015-07-30 Kabushiki Kaisha Toshiba Semiconductor device and semiconductor device manufacturing method
US20200083273A1 (en) * 2016-12-26 2020-03-12 Sony Semiconductor Solutions Corporation Semiconductor device, method of manufacturing semiconductor device, and solid-state image sensor
EP3790046A1 (en) * 2019-09-03 2021-03-10 Ams Ag Through-substrate via and method for manufacturing a through-substrate via

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115621197A (en) * 2022-11-22 2023-01-17 湖北三维半导体集成创新中心有限责任公司 Through silicon via interconnected cavity structure and forming method thereof

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