TWI836378B - Semiconductor device with sealed tsv and method for producing thereof - Google Patents

Abstract

A semiconductor device (1) comprises a substrate (2). A metal layer (4) is arranged on or above a main surface (2’) of the substrate (2). The semiconductor device (1) further comprises a through-substrate-via (12), TSV. A via hole (5) of the TSV (12) reaches from a rear surface (2”) of the substrate (2) to the metal layer (4). An insulation layer (6) is arranged on a sidewall (7) of the via hole (5) between the substrate (2) and a metallization layer (8) of the TSV (12), the metallization layer (8) being configured to electrically contact the metal layer (4) from the rear surface (2”) of the substrate (2). A thickness of the insulation layer (6) increases towards the rear surface (2”), such that the via hole (5) is narrowed and is sealed by the metallization layer (8) and/or by a sealing layer (15, 16), thus forming a cavity (10).

Description

Semiconductor device with sealed TSV and manufacturing method thereof

The present invention relates to a semiconductor device, a sensor device including a semiconductor device, and a method for manufacturing a semiconductor device. The semiconductor device includes a sealed substrate through hole.

For three-dimensional integration of semiconductor devices, through-substrate-vias (TSVs) are used. TSV is an electrical interconnection through a semiconductor substrate. It includes a through hole penetrating the substrate and a metallization layer disposed in the through hole.

TSVs are made by first forming a metal layer in a dielectric insulating layer on the main surface of the substrate. A through hole is then etched from the rear surface through the substrate until the dielectric insulating layer is reached. The insulating layer is disposed on the sidewalls and bottom of the through hole. The insulating layer and the dielectric insulating layer are removed from the bottom of the through hole by an anisotropic etching step, so that the insulating layer remains on the sidewalls to cover the semiconductor material. After the etching step, the metal layer is exposed at the bottom of the through hole. Metal can be plated in the through hole to contact the metal layer and form an electrical connection.

Typically, this plated metal completely fills the through hole. For example, the via hole is completely filled with copper plating. However, this method will have the following disadvantages: on the one hand, since the plated metal completely fills the through hole, the material cost is high, resulting in high production cost. On the other hand, semiconductor devices are prone to stress-induced Cracks, for example, caused by differences in thermal expansion coefficients. Additionally, in some cases, such as in complementary metal oxide semiconductor (CMOS) manufacturing, copper plating may not be desirable due to contamination reasons.

According to another approach, a metallization layer is used that covers only the sidewalls and the bottom of the via. This means that the rest of the via remains empty. The metallization layer may include tungsten, which can be deposited in a conformal manner by chemical vapor deposition (CVD). Although the above-mentioned disadvantages are overcome by this approach, other problems also arise: Due to the open TSV, the semiconductor device is susceptible to particles, plasma reactants, wet chemicals and moisture during the manufacturing process. In addition, careful handling must be performed to avoid microcracks at the bottom of the TSV. Due to its shape, a dedicated etching step is further required.

Therefore, one object to be achieved by the present invention is to provide an improved concept of TSV technology. According to this improved concept, the reliability of the TSV can be enhanced and further processing after the TSV is formed is facilitated.

This purpose is achieved through the main content of the independent request. Further developments and embodiments thereof are described in dependent claims.

In one embodiment, a semiconductor device includes a substrate having a back surface and a major surface. The metal layer is disposed on or above the main surface of the substrate. The semiconductor device also includes a through-substrate-via (TSV), which includes a through hole, an insulating layer and a metallization layer. The vias touch the metal layer from the back surface of the substrate. The insulating layer is disposed on the sidewall of the through hole between the substrate and the metallization layer. The metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate. The thickness of the insulating layer increases toward the rear surface of the substrate, causing the vias to become narrower.

According to at least one embodiment, the through hole is sealed by a metallization layer. Alternatively or additionally, the through hole is sealed by a sealing layer. By sealing the through hole, a cavity is formed.

The base plate has a main extension surface. The main surface and the rear surface of the substrate extend in a transverse direction, wherein the transverse direction is parallel to the main extension surface of the substrate. The substrate may include a semiconductor material, such as silicon (Si). Circuits and other electronic components can be integrated into the substrate. For example, CMOS circuits and/or sensor elements are configured in the substrate.

The metal layer may in particular be part of the wiring, for example the wiring may comprise a number of metal layers. The metal layer may include aluminum (Al). The metal layer may be doped with copper (Cu) and/or silicon (Si). Therefore, the metal layer may form an AlSi or AlCu layer. The metal layer of the wiring embedded in the dielectric insulation layer is usually provided with a barrier layer, especially in CMOS technology, to enhance the adhesion of the dielectric material to the metal layer and prevent diffusion processes such as electromigration. Therefore, the metal layer can be sandwiched between two barrier layers located on top and bottom of the metal layer respectively. The barrier layer may include titanium (Ti) and/or titanium nitride (TiN).

TSV touches the metal layer from the rear surface of the substrate. This means that the through hole of the TSV completely penetrates the substrate opposite to the metal layer. Therefore, the TSV has a vertical extension from the rear surface of the substrate to the metal layer. The vertical direction refers to the direction extending perpendicular to the main extension surface of the substrate. The TSV is aligned with the metal layer. The lateral extension of the TSV is smaller than the lateral extension of the metal layer.

The insulating layer is arranged on the sidewall of the through hole. Therefore, the substrate is electrically isolated from the metallization layer of the TSV. The insulating layer includes SiO ₂ , for example. The insulating layer covers the sidewalls of the through hole. A portion of the insulating layer may also typically cover the rear surface of the substrate outside the via. Short circuits can be avoided by the insulation layer. The substrate may be at a different potential than the TSV.

The thickness of the insulating layer on the side wall of the through hole increases toward the rear surface of the substrate. In other words, the insulating layer is a non-conformal layer, i.e., its thickness is uneven. Therefore, the opening of the through hole becomes narrower. The opening diameter after the insulating layer is deposited can be greater than 0.5μm and less than 20μm. Alternatively, the opening diameter after the insulating layer is deposited can be greater than 1μm and less than 10μm.

For example, in embodiments where the via is sealed by a metallization layer, the diameter of the opening after deposition of the insulating layer may reach 1 μm, 2 μm or 3 μm, respectively. On the other hand, in embodiments where the vias are sealed by a dedicated sealing layer, the diameter of the opening after deposition of the insulating layer can reach 4 μm, 10 μm or even 20 μm respectively. By narrowing the opening, it is easier to seal the via in subsequent deposition steps.

The metallization layer may include tungsten (W). The metallization layer of the TSV may include a sidewall portion that covers the insulating layer on the sidewall of the through hole. This means that the insulating layer separates the substrate from the metallization layer. The metallization layer may also include a base portion that covers the exposed metal layer to form an electrical contact.

The metallization layer may be a conformal layer. Therefore, it can have a uniform thickness. In this case, the via can be sealed by a sealing layer. However, the metallization layer can also be a non-conformal layer. This is especially true for embodiments where the via is sealed by a metallization layer. In these cases, the metallization layer on the rear surface of the substrate can be thicker than the metallization layer on the bottom of the via.

The side walls and base of the metallization layer ensure continuous metallization from the rear surface of the substrate to the metal layer. The rest of the through hole is empty/unfilled. This is advantageous in view of thermal and mechanical stresses as well as material consumption.

By sealing the via, the via is closed. Thus, a cavity is formed inside the TSV. The cavity can be filled with air or a gas. The closed via leads to a higher structural stability. In addition, the semiconductor device is protected from moisture, particles, dry etching reactants and other chemicals. If the via is open, particles etc. may be deposited in the via and damage the metallization layer.

In one embodiment, the semiconductor device further includes a dielectric insulation layer disposed on the main surface of the substrate. This can mean that in the vertical direction, the dielectric insulation layer is arranged above the substrate. The dielectric insulating layer may be an oxide, such as silicon oxide (SiO ₂ ). The metal layer is embedded in the dielectric insulation layer. Through the dielectric insulation layer, wiring for circuitry and sensor components can be provided.

In one embodiment, the metallization layer forms a plug on the rear surface of the substrate, which seals the via. Alternatively, the sealing layer forms a plug that seals the via on the rear surface of the substrate. The plug seals the via, thereby enhancing structural stability and protecting the via from moisture, particles, dry etch reagents and other chemicals.

In one embodiment, a portion of the insulating layer is disposed on the rear surface of the substrate. The substrates are electrically isolated by the insulating layer. Therefore, the contact area can be arranged on the rear surface of the substrate.

In one embodiment, the planar surface is formed by a portion of an insulating layer, a metallization layer, and/or a sealing layer disposed on a rear surface of the substrate. The planar surface spans the TSV.

The flat surface can be parallel to the back surface of the substrate. In embodiments where the metallization layer forms a plug that seals the via, the metallization layer may form a circular area within the flat surface. Alternatively, the metallization layer forms an annular region within the flat surface while the sealing layer forms a plug that seals the via.

The flat surface has the effect of leveling the contours caused by the vias. Therefore, it is beneficial for further processing of the semiconductor device on the back side. In particular, standard lithography steps can be used for further processing. No high viscosity photoresist is required to cover the vias. This reduces production costs. One or more redistribution layers can be deposited on the flat surface by CMOS back-end processes. In addition, standard steps for under bump metallization can be used.

In one embodiment, the semiconductor device further includes a redistribution layer. The redistribution layer is electrically connected to the metallization layer and forms at least one contact area on the rear surface of the substrate.

The redistribution layer can be a planar layer deposited on a planar surface. The redistribution layer can be patterned by standard photolithography. According to one embodiment, since the metallization layer can be part of the planar surface, the redistribution layer is in direct contact with the metallization layer.

According to another embodiment, the redistribution layer overlaps the sidewall portion of the metallization layer. This means that the redistribution layer extends into the via such that at least part of the sidewall portion of the metallization layer is covered by the redistribution layer. In this embodiment, the through hole is sealed by a sealing layer, where the sealing layer may be a passivation layer.

The redistribution layer may include aluminum (Al). Preferably, the redistribution layer does not contain tungsten, as large surface areas of tungsten may exhibit high layer stresses, which may lead to delamination or cracking. Electrical signals may be transmitted and/or redirected by means of the redistribution layer. The semiconductor device may include an additional redistribution layer such that the redistribution layer and the additional redistribution layer form a wiring on a rear surface of the substrate. In addition, the redistribution layer may be provided with an underbump metal, and solder bumps may be applied to the underbump metal.

In one embodiment, the redistribution layer is covered by a passivation layer except for the contact areas. The passivation layer may include dielectric materials, such as silicon oxide and/or silicon nitride (SiN). At least one opening in the passivation layer provides access to the contact area of the rear surface of the substrate. Therefore, solder bumps, bonding wires, etc. can be applied. The passivation layer protects the semiconductor device from physical damage such as scratches and/or moisture-induced damage.

In one embodiment, the sealing layer includes an oxide layer. Alternatively, the sealing layer includes a passivation layer. If the sealing layer is an oxide layer, it may be a non-conformal oxide layer. Therefore, the oxide layer can have Has uneven thickness, making it thicker at the via opening and thinner in the via. Therefore, the oxide layer forms a plug that seals the via. If the sealing layer is a passivation layer, it can be the same passivation layer covering the redistribution layer. A portion of the passivation layer may be present in the via covering the metallization layer. Preferably, the vias can be sealed with some additional or generally existing layer.

Furthermore, a sensor device is provided including the semiconductor device. This means that all features disclosed in the semiconductor device are also disclosed in the sensor device, and all features are applicable to the sensor device and vice versa.

In one embodiment, the sensor device is an ambient light sensor. In another embodiment, the sensor device is a color sensor. In another embodiment, the sensor device is a proximity sensor. In another embodiment, the sensor device is a photon counting sensor. In another embodiment, the sensor device is a time-of-flight sensor. According to one aspect of the invention, a sensor arrangement includes a sensor located behind an organic light emitting diode (OLED) display.

The mobile phone market will continue to follow the trend towards higher screen-to-body ratios and eventually full-screen, bezel-less smartphones. To this end, the sensor elements contained in such devices must be highly integrated, thus requiring 3D integration technology. Preferably, the sensor device used includes a semiconductor device with TSVs through which electrical contact can be made from the rear surface. Therefore, terminal devices such as smartphones can be designed to be very thin. For example, the front side of the terminal device can be completely filled with a screen, for example an OLED display.

Furthermore, a method of manufacturing a semiconductor device is provided. All features disclosed in the semiconductor device and sensor device are also equivalent to those disclosed in the manufacturing method of the semiconductor device, and vice versa.

According to at least one embodiment, the manufacturing method includes providing a substrate having a rear surface and a main surface. The substrate may include a semiconductor material, such as silicon (Si).

The manufacturing method also includes configuring a metal layer on the main surface of the substrate or above the main surface of the substrate. For example, the dielectric insulating layer is configured on the main surface of the substrate, and the metal layer is embedded therein. The dielectric insulating layer can be an oxide, such as silicon oxide ( _SiO2 ). The dielectric insulating layer can be deposited on the substrate in one or more deposition steps, for example, by chemical vapor deposition (CVD). The metal layer can include aluminum (Al). In addition, the metal layer can include a barrier layer. The barrier layer can include titanium (Ti) and/or titanium nitride (TiN). Metal layers including barrier layers can be deposited by sputtering between two subsequent deposition steps of dielectric insulating layers. Patterning of the metal layers can be performed by etching.

The manufacturing method also includes forming through-substrate vias (TSVs). The step of forming the TSV includes forming vias from the rear surface of the substrate to the metal layer. This means that vias can be formed by removing the substrate opposite the metal layer. Vias can be formed in the silicon substrate by deep reactive-ion etching (DRIE). The DRIE process can be time-controlled or use an etch stop layer. The DRIE process is also called the Bosch process. DRIE is a fast and effective anisotropic etching technology.

The via can be extended to the metal layer by removing the dielectric insulation layer. This represents a further etching step to remove the dielectric insulating layer located between the substrate and the metal layer. For the second etching step, the metal layer can serve as an etch stop layer. Further etching steps expose the metal layer.

The step of forming the TSV also includes depositing an insulating layer on the sidewalls of the through hole. The insulating layer can be deposited after the dielectric insulating layer is removed to the metal layer. The insulating layer includes, for example, _SiO2 . The deposition of the insulating layer can be performed by CVD. The insulating layer covers the sidewalls of the through hole. Part of the insulating layer can also typically cover the bottom of the through hole (i.e., the metal layer) and the rear surface of the substrate outside the through hole. After deposition, the insulating layer is removed from the bottom of the through hole by an anisotropic etching step, thereby exposing the metal layer.

In an alternative embodiment, the insulating layer is deposited after removal of the substrate opposite the metal layer and before removal of the dielectric insulating layer. In this embodiment, the insulating layer may be removed from the bottom of the via in the same anisotropic etching step used to remove the dielectric insulating layer.

The insulating layer is deposited such that the thickness of the insulating layer on the side walls of the through hole increases towards the rear surface of the substrate. As a result, the through hole narrows towards the rear surface. This can be achieved by non-conformal deposition. It is also possible to form the insulating layer using more than one deposition step. By means of the insulating layer, the substrate is electrically isolated and short circuits are avoided. By narrowing the through hole towards the rear surface, the through hole can be sealed in a subsequent deposition step.

The step of forming the TSV also includes depositing a metallization layer. The metallization layer is configured to electrically contact the metal layer from the rear surface of the substrate. The metallization layer may include more than one metal and may be applied as a series of metal layers, for example, may include titanium and/or tungsten layers. The sidewall portion of the metallization layer covers the sidewall of the through hole, and the base of the metallization layer covers the exposed metal layer. The metallization layer is isolated from the substrate by an insulating layer. The metallization layer is in direct contact with the exposed metal layer.

The step of forming the TSV further includes sealing the through hole by a metallization layer. Alternatively or additionally, the through hole is sealed by deposition of a sealing layer. By sealing the through hole, a cavity is formed.

In one embodiment, the step of depositing a metallization layer includes at least two deposition steps. In a first deposition step with enhanced gas flow, a first portion of the metallization layer is deposited with a conformal thickness. In a second deposition step with reduced gas flow, a second portion of the metallization layer is deposited with a non-conformal thickness. The through hole is sealed by the second portion of the metallization layer. Thus, the metallization layer forms a plug that seals the through hole.

The gas stream may include tungsten hexafluoride (WF6). Preferably, the WF6 gas flow can be controlled to avoid tungsten deposition at the bottom of the TSV. Therefore, only a small amount of process gas reaches the bottom of the TSV. WF6 may react to produce hydrogen (H2) and hydrogen fluoride (HF). Therefore, after the sealing process step, only HF and H2 can remain within the TSV due to the deposition process. Although the metallization layer (usually tungsten) has been found to be very stable to HF, the HF concentration in the via can be reduced by controlling the gas flow.

In one embodiment, the step of sealing the through hole includes depositing a sealing layer, wherein the sealing layer is an oxide layer. The oxide layer may include, for example, SiO ₂ . The deposition of the oxide layer may be a non-conformal deposition by a CVD process. Thus, the oxide layer may have a non-uniform thickness, such that its thickness is thicker at the through hole opening and thinner in the through hole. Thus, the oxide layer forms a plug that seals the through hole. Alternatively, the sealing layer is a passivation layer. The passivation layer may include SiO ₂ and/or SiN. Preferably, only a few additional deposition steps are required to seal the through hole. Alternatively, no additional deposition is required, since the deposition of the passivation layer is usually performed anyway.

In one embodiment, the method of manufacturing a semiconductor device further includes a planarization step. A planarization step is performed after sealing the vias. Through the planarization step, the planar surface is formed by a portion of the insulating layer, the metallization layer and/or the sealing layer disposed on the rear surface of the substrate. A flat surface spans the TSV.

Through the planarization step, the thickness of the metallization layer and/or the thickness of the sealing layer located on the rear surface of the substrate is reduced. Preferably, the appearance undulations caused by the through holes are smoothed. This facilitates further processing on the back side of the semiconductor device.

In one embodiment, the planarization step includes chemical mechanical polishing (CMP). In particular, the planarization step includes tungsten chemical mechanical polishing (W- CMP). Conventionally, the metallization layer (usually tungsten) is removed from the back surface of the substrate by an etching step. However, this process also erodes the metallization layer on the bottom of the TSV. According to the present invention, since the TSV is sealed and the planarization step includes CMP, no tungsten loss occurs at the bottom of the via, resulting in a more reliable TSV.

In one embodiment, the method for manufacturing a semiconductor device further includes depositing a redistribution layer so that the redistribution layer is electrically connected to the metallization layer and at least one contact region is formed on the rear surface of the substrate.

The redistribution layer may include aluminum (Al) deposited by a sputtering process. Through the redistribution layer, electrical signals can be transmitted and/or redirected. The redistribution layer may be provided with an under-bump metal and solder bumps may be applied over the under-bump metal. Conventionally, bump bottom metal is provided by electroless nickel (Ni) plating. However, Ni will diffuse into the aluminum of the redistribution layer, causing adverse effects. According to one embodiment, since the vias are closed and covered by the flat surface, the sputtering process can also be applied to the under-bump metal, resulting in a more reliable semiconductor device.

From the above-described embodiments of the semiconductor device, other embodiments of the manufacturing method will be apparent to those of ordinary skill in the art.

1:Semiconductor device

2: Substrate

2’: Main surface of substrate

2”:Surface behind substrate

3: Dielectric insulation layer

4:Metal layer

5:Through hole

6: Insulating layer

6’: Part of the insulating layer

7: Side wall of through hole

8:Metalization layer

8’: Base of metallization layer

8”: Side wall of the metallization layer

9:Plug

10:Cavity

11: Flat surface

12: Substrate through hole

13: Redistribution layer

14: Contact area

15: Passivation layer, sealing layer

16: Oxidation layer, sealing layer

17: Sensor device

d: diameter

x, y: horizontal direction

z: vertical direction

The following description of the drawings may further illustrate and explain aspects of the improved semiconductor device and its manufacturing method. Components and parts of the semiconductor device that have the same function or have the same effect are represented by the same element number. Components and parts that are the same or have the same effect may be described only for the figure in which they first appear. It is not necessary to repeat their description in consecutive figures.

FIG1 shows an intermediate product of a method for manufacturing a semiconductor device according to an embodiment.

FIG. 2a to FIG. 2c show an exemplary embodiment of a method for manufacturing a semiconductor device based on the intermediate product of FIG. 1.

FIG. 3a to FIG. 3c show another exemplary embodiment of a method for manufacturing a semiconductor device based on the intermediate product of FIG. 1 .

Figures 4a to 4c show another exemplary embodiment of a method for manufacturing a semiconductor device based on the intermediate product of Figure 1.

FIG5 shows an embodiment of a sensor device including a semiconductor device.

In FIG. 1 , an intermediate product of a method of manufacturing a semiconductor device according to an embodiment is shown. Since TSV 12 is typically processed by back-side processing of semiconductor wafers, semiconductor device 1 is shown upside down.

The semiconductor device 1 includes a substrate 2 having a rear surface 2" and a main surface 2'. The substrate 2 has a main extending surface. The rear surface 2" and the main surface 2' extend in transverse directions x, y, wherein the transverse directions x, y are parallel to The main extension surface of the base plate 2.

The dielectric insulation layer 3 is disposed on the main surface 2' of the substrate 2. This means that in the vertical direction z, the dielectric insulating layer 3 is arranged above the substrate.

The metal layer 4 is arranged above the main surface 2' of the substrate. Metal layer 4 is embedded in dielectric insulation layer 3 . The metal layer 4 may be part of the wiring of the semiconductor device 1 . FIG. 1 shows a metal layer 4 by way of example only. However, the semiconductor device 1 may include additional metal layers.

The through hole 5 reaches the metal layer 4 from the rear surface 2" of the substrate 2. The through hole 5 penetrates the substrate 2 and the dielectric insulating layer 3 disposed between the substrate and the metal layer 4.

The insulating layer 6 is disposed on the sidewall 7 of the through hole 5 formed by the substrate 2 and the dielectric insulating layer 3. A portion 6' of the insulating layer 6 also covers the rear surface 2" of the substrate 2 outside the through hole 5. The thickness of the insulating layer 6 on the sidewall 7 increases toward the rear surface 2" of the substrate, so that the through hole becomes narrower. The through hole 5 can be at least partially formed by deep reactive ion etching (DRIE). The insulating layer 6 can be formed by non-conformal deposition of an oxide, in particular by silicon oxide. Therefore, the protruding portion of the insulating layer 6 is formed on the rear surface 2" of the substrate 2, and the opening of the through hole 5 is narrowed. The opening diameter d is shown in FIG. 1. The diameter d may be different in each embodiment. For example, the diameter d may be between 0.5 μm and 20 μm.

The intermediate product of the semiconductor device shown in Figure 1 represents the starting point for the process steps described below. This means that each process according to FIGS. 2 a to 2 c, 3 a to 3 c, and 4 a to 4 c is based on the intermediate product shown in FIG. 1 .

2a to 2c illustrate further steps of a method of manufacturing a semiconductor device according to an embodiment. According to Figure 2a, a metallization layer 8 is deposited.

The metallization layer 8 includes a base 8' that is in direct contact with the metal layer 4. Therefore, the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2" of the substrate 2. In addition, the metallization layer 8 includes a sidewall portion 8". The sidewall portion 8" covers the insulating layer 6 on the sidewall 7 of the through hole 5. The base 8' and the sidewall portion 8" of the metallization layer 8 form a continuous layer. On the rear surface 2" of the substrate 2, the metallization layer forms a plug 9 that seals the through hole 5. Therefore, a cavity 10 is formed.

Depositing the metallization layer 8 may include at least two deposition steps, wherein, in a first deposition step of enhancing the gas flow, a first portion of the metallization layer 8 having a conformal thickness is deposited, thereby mainly forming a base portion 8' and a sidewall portion 8" of the metallization layer 8. In a second deposition step of reducing the gas flow, a second portion of the metallization layer 8 having a non-conformal thickness is deposited, so that the through hole is sealed by the second portion. The second portion may mainly form a plug 9.

By means of the above-mentioned deposition step, a portion of the metallization layer 8 can be deposited on the portion 6' of the insulating layer 6 on the rear surface 2" of the substrate 2 outside the cavity 10. These portions can be removed in a subsequent planarization step, as described below.

FIG. 2 b shows the semiconductor device 1 according to FIG. 2 a after a planarization step. The planarization step may include chemical mechanical polishing (CMP), in particular tungsten chemical mechanical polishing (W-CMP). By means of the planarization step, the metallization layer 8 on the rear surface 2 ″ of the substrate 2 outside the cavity 10 is removed/polished until a portion 6 ′ of the insulator 6 is exposed. Thus, a planar surface 11 is formed by the portion 6 ′ of the insulating layer 6 and the metallization layer 8, in particular the plug 9 formed by the metallization layer 8. In a plan view, the plug 9 may form a circular area within the planar surface 11. A functional through substrate via (TSV) 12 is formed by the metallization layer 8 electrically contacting the metal layer 4 and isolated from the substrate 2.

Fig. 2c shows the semiconductor device 1 according to Fig. 2b after further processing steps. The semiconductor device 1 according to Fig. 2c comprises a redistribution layer 13 which can be deposited by a sputtering process. The redistribution layer 13 shown in Fig. 2c is a planar layer arranged on the flat surface 11. The redistribution layer 13 is electrically connected to the metallization layer 8, in particular the plug 9, and forms at least one contact area 14 on the rear surface 2" of the substrate 2. Since the processing on the flat surface 11 does not require a high viscosity photoresist, the redistribution layer 13 can be formed by known photolithography. As shown in FIG. 2c, except for the contact area 14, the redistribution layer 13 is covered by the passivation layer 15. At least one opening in the passivation layer 15 provides access to the contact area 14. In some embodiments, the passivation layer 15 can further cover a portion 6' of the insulating layer 6 disposed on the rear surface 2" of the substrate 2.

Figures 3a to 3c illustrate further steps of a method of manufacturing a semiconductor device 1 according to another embodiment. This embodiment may use the intermediate product shown in Figure 1, or a similar intermediate product. The dimensions may differ between the embodiment according to Figures 2a to 2c and the embodiment according to Figures 3a to 3c. In particular, the opening diameter d of the through hole 5 may be different after the insulating layer 6 is deposited.

According to Figure 3a, a metallization layer 8 is deposited. The metallization layer 8 includes a base 8' in direct contact with the exposed metal layer 4. Therefore, the metallization layer 8 is in electrical contact with the metal layer 4 from the rear surface 2 ″ of the substrate 2 . Furthermore, the metallization layer 8 includes sidewall portions 8 ″. The sidewall portion 8″ covers the insulating layer 6 on the sidewall 7 of the through hole 5. Another part of the metallization layer 8 may be deposited on the part 6′ of the insulating layer 6 on the rear surface 2″ of the substrate 2 outside the through hole 5. The base portion 8', the sidewall portion 8" and another portion of the metallization layer 8 can form a continuous layer with a uniform thickness. Since the surface 2" of the metallization layer 8 is electrically in contact with the metal layer 4 from the rear surface 2" of the substrate 2 and is isolated from the substrate 2, Formation of functional TSV 12.

In addition, a sealing layer 16 is deposited, where the sealing layer 16 may be an oxide layer 16. As shown in FIG. 3a, the deposition of the sealing layer 16 may be non-conformal deposition. This means that the sealing layer 16 has a non-uniform thickness, such that the thickness is thicker at the opening of the through hole 5 and thinner in the through hole 5. However, a portion of the sealing layer 16 may also exist in the through hole 5. The sealing layer 16 seals the through hole 5 by forming the plug 9. Thus, the cavity 10 of the TSV 12 is formed.

A portion of the sealing layer 16 may be deposited on another portion of the metallization layer 8 , which is disposed on the rear surface 2 ″ of the substrate 2 outside the through hole 5 . Therefore, the sealing layer 16 may completely cover the metallization layer 8 .

FIG. 3b shows the semiconductor device 1 according to FIG. 3a after a planarization step. The planarization step may include chemical mechanical polishing (CMP). By means of the planarization step, the sealing layer 16 and the portion of the metallization layer 8 on the portion 6' of the insulating layer 6 arranged outside the through hole 5 are removed. The sealing layer 16 and the portion of the metallization layer 8 are removed/polished until the portion 6' of the insulating body 6 is exposed. Thus, a planar surface 11 is formed by the portion 6' of the insulating layer 6, the metallization layer 8 and the sealing layer 16 forming the plug 9. In a plan view, the metallization layer 8 forms an annular area within the planar surface 11.

Figure 3c shows the semiconductor device 1 according to Figure 3b after further processing steps. The semiconductor device 1 according to Figure 3c includes a redistribution layer 13 and a passivation layer 15, corresponding to the embodiment of Figure 2c. Therefore, further explanation is provided in the above description.

4a to 4c show further steps of a method for manufacturing a semiconductor device 1 according to another embodiment. Likewise, the embodiment can also be based on the intermediate product shown in FIG. 1 , or a similar intermediate product. However, the dimensions may be different, in particular the opening diameter d of the through hole 5 after the deposition of the insulating layer 6 may be different.

According to Figure 4a, a metallization layer 8 is deposited. The metallization layer 8 includes a base 8' in direct contact with the exposed metal layer 4. Therefore, the metallization layer 8 is in electrical contact with the metal layer 4 from the rear surface 2 ″ of the substrate 2 . Furthermore, the metallization layer 8 includes sidewall portions 8 ″. The side wall portion 8″ covers the insulating layer 6 on the side wall 7 of the through hole 5.

By means of the etching step, another part (not shown) of the metallization layer 8 deposited on the part 6' of the insulating layer 6 on the rear surface 2" of the substrate 2 outside the through hole 5 can be removed. Therefore, the rear surface 2 of the substrate 2 A portion 6' of the insulating layer 6 on " is exposed, and the metallization layer 8 is confined in the via hole. The base portion 8' and the sidewall portions 8" may form a continuous layer of substantially uniform thickness. Since the metallization layer 8 electrically contacts the metal layer 4 from the rear surface 2" of the substrate 2 and is isolated from the substrate 2, a functional TSV 12 is formed .

In the next step, a redistribution layer 13 is applied, as shown in Figure 4b. The redistribution layer 13 at least partially covers the portion 6′ of the insulating layer 6 disposed on the rear surface 2″ of the substrate 2. In addition, The redistribution layer 13 extends into the via 5 such that it at least overlaps the metallization layer 8 . In particular, the redistribution layer 13 overlaps with the upper portion of the sidewall portion 8″ of the metallization layer 8 near the via opening. Therefore, the redistribution layer 13 is electrically connected to the metallization layer 8. The redistribution layer 13 can be formed by sputtering Process deposition. The sputtering process will cause non-conformal deposition, so that the thickness of the redistribution layer 13 decreases as the depth of the through hole 5 increases.

In a next step according to FIG. 4 c , a passivation layer 15 is deposited. The passivation layer 15 covers the redistribution layer 13 except for the contact area 14 . This means that at least one opening in the passivation layer 15 provides access to the redistribution layer 13 . Apart from the contact area 14 , the passivation layer 15 may cover the entire rear surface 2 ”.

Furthermore, according to this embodiment, the passivation layer 15 serves as the sealing layer 15 for sealing the through hole 5 . Therefore, the passivation layer 15 forms the plug 9 and thus the cavity 10 . Since passivation layer 15 is typically deposited by chemical vapor deposition, portions of passivation layer 15 may also be present within cavity 10 covering base 8' and sidewall portions 8" of metallization layer 8. Passivation layer 15 spans TSV 12 . However, according to this embodiment, the flat surface 11 may not be formed, and the surface may be recessed at the TSV 12, as shown in Figure 4c.

A sensor device 17 including a semiconductor device 1 is schematically shown in FIG. 5 . The sensor device 17 may be an ambient light sensor, a color sensor, a proximity sensor, a photon counting sensor and a time of flight sensor. The sensor device may be located behind an organic light emitting diode display (not shown).

In order to familiarize the reader with the novel aspects of the present technical ideas, embodiments of the semiconductor device 1 disclosed herein and methods of manufacturing the semiconductor device 1 are discussed. Although shown and described relatively Although preferred embodiments are preferred, many changes, modifications, equivalents, and substitutions of the disclosed concepts can be made by those of ordinary skill in the art without unnecessarily departing from the scope of the claimed patent.

It should be understood that the present disclosure is not limited to the disclosed embodiments and the contents that have been specifically shown and described above. On the contrary, the features listed in separate dependent claims or mentioned in the description can be combined in an advantageous manner. In addition, the scope of the present disclosure includes those changes and modifications that are obvious to a person with ordinary knowledge in the art and fall within the scope of the attached patent application.

The term "comprising" used in the scope of the patent application or the specification does not exclude corresponding features or other elements or steps of the process. Where the term a/an is used in connection with a feature, a plurality of such feature is not excluded. Furthermore, any element numbering in the claimed scope should not be construed as limiting the scope thereof.

This patent application claims priority to German Patent Application No. 102021109045.8, the disclosure of which is incorporated herein by reference.

6: Insulating layer

6’: Part of the insulating layer

8: Metallization layer

9: Plug

11: Flat surface

16: Oxidation layer, sealing layer

Claims (12)

A semiconductor device comprises: a substrate having a rear surface and a main surface; a metal layer disposed on or above the main surface of the substrate; and a through-substrate via (TSV), comprising a through hole, an insulating layer and a metallization layer, wherein the through hole reaches the metal layer from the rear surface of the substrate, the insulating layer is disposed on a side wall of the through hole between the substrate and the metallization layer, and the metallization layer is configured to electrically connect the through hole from the rear surface of the substrate to the metal layer. The metal layer is contacted with the substrate, wherein the thickness of the insulating layer increases toward the rear surface of the substrate, so that the through hole is narrowed and sealed by the metal layer, wherein the metal layer includes a first portion having a conformal thickness and a second portion having a non-conformal thickness, so that the through hole is sealed by the second portion to form a cavity, or the through hole is sealed by a sealing layer, wherein the sealing layer includes one of an oxide layer and a passivation layer that seals the through hole to form a cavity. The semiconductor device of claim 1, further comprising a dielectric insulating layer disposed on the main surface of the substrate, wherein the metal layer is embedded in the dielectric insulating layer. A semiconductor device as described in claim 2, wherein the metallization layer or the sealing layer forms a plug sealing the through hole on the rear surface of the substrate. A semiconductor device as described in claim 1, wherein a portion of the insulating layer is disposed on the rear surface of the substrate. The semiconductor device of claim 4, wherein the flat surface is formed by the portion of the insulating layer, the metallization layer and/or the sealing layer disposed on the rear surface of the substrate, and the flat surface spans the substrate through hole. A semiconductor device as described in claim 1, further comprising a redistribution layer, the redistribution layer being electrically connected to the metallization layer and forming at least one contact region on the rear surface of the substrate. The semiconductor device of claim 6, wherein the redistribution layer is covered by the passivation layer except for the contact area. A sensor device, including the semiconductor device according to any one of claims 1 to 7, wherein the sensor device is particularly an ambient light sensor or a color sensor behind an organic light-emitting diode display. , a proximity sensor, a photon counting sensor, and a time-of-flight sensor. A method for manufacturing a semiconductor device, the method comprising the following steps: providing a substrate having a rear surface and a main surface; configuring a metal layer on or above the main surface of the substrate; and forming a through-substrate via, i.e., TSV, comprising the following steps: forming a through hole from the rear surface of the substrate to the metal layer; depositing an insulating layer on the sidewall of the through hole, the thickness of the insulating layer increasing toward the rear surface of the substrate so that the through hole becomes narrower; depositing a metallization layer, the metallization layer configured to electrically connect the rear surface of the substrate to the through hole; contacting the metal layer; and sealing the through hole to form a cavity, wherein the step of depositing the metallization layer includes at least two deposition steps, wherein in a first deposition step of increasing the gas flow, a first portion of the metallization layer is deposited with a conformal thickness, and in a second deposition step of reducing the gas flow, a second portion of the metallization layer is deposited with a non-conformal thickness, so that the through hole is sealed by the second portion, or wherein the step of sealing the through hole includes depositing a sealing layer, i.e., depositing one of an oxide layer and a passivation layer to seal the through hole. The manufacturing method of a semiconductor device as claimed in claim 9, further comprising a planarization step after sealing the through hole, so that the planar surface consists of a portion of the insulating layer disposed on the rear surface of the substrate, the A metallization layer and/or the sealing layer is formed, and the flat surface spans the substrate through hole. A method for manufacturing a semiconductor device as described in claim 10, wherein the planarization step includes chemical mechanical polishing, i.e., CMP. The manufacturing method of a semiconductor device according to any one of claims 9 to 11, further comprising depositing a redistribution layer so that the redistribution layer is electrically connected to the metallization layer and on the rear surface of the substrate At least one contact area is formed.

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