DE102020214547A1 - Micromechanical device and method of manufacture - Google Patents

Abstract

The invention relates to a micromechanical device with a first MEMS substrate (10), a second MEMS substrate (20) and an ASIC substrate (30), the substrates (10, 20, 30) being stacked on top of one another in such a way that that the ASIC substrate is arranged between the first MEMS substrate and the second MEMS substrate, the ASIC substrate with the first MEMS substrate by means of a first metal bond connection (15) and with the second MEMS substrate by means of a second metal bond connection (25) is mechanically connected and electrically contacted, and the ASIC substrate has at least one via (35) which is electrically conductively connected to the first MEMS substrate and/or to the second MEMS substrate.
The invention also relates to a method for manufacturing a stacked micromechanical device with a first MEMS wafer, an ASIC wafer and a second MEMS wafer.

Description

State of the art

Micromechanical inertial sensors for measuring physical quantities such as acceleration, yaw rate and pressure are mass-produced for various applications in the automotive and consumer sectors. MEMS components that can be evaluated capacitively are particularly widespread due to their good signal-to-noise ratio and low power consumption at the same time. Such capacitive MEMS components need to convert an external measured variable, z. B. an acceleration, and a resulting proportional change in capacitance an integrated circuit or ASIC, which is typically manufactured in CMOS semiconductor technology. This converts the change in capacitance into a change in voltage, and for newer types the output signal is also digitized. MEMS and ASIC are often placed on top of each other in various packaging forms, especially in LGA or BGA mold housings, but also as bare die or chip scale packages, i.e. without outer packaging.

In a common product concept, a CMOS wafer and a MEMS wafer are processed separately, and after dicing the two wafers, an ASIC chip and a MEMS chip are packaged in a package, e.g. B. a mold housing, mechanically and electrically connected to each other, in particular arranged one on top of the other in order to keep the lateral dimensions of the housing as small as possible. In this multiple-stack production from chips that have already been separated, an adhesive or adhesive film must be introduced between the chips to be connected. In addition, the chips are typically encapsulated with a molding compound. Both can have negative effects on the subsequent performance of the component (e.g. as a result of stress due to temperature changes, bending, moisture in the adhesive or in the molding compound). At the same time, the production of the above Multiple stacks of individual chips require separate, intrinsically stable individual wafers or stacks with a specific thickness, which then have to be isolated. This limits the possible height of the entire stack, because the individual wafers or wafer stacks can only be ground thin to a limited extent.

Alternatively, MEMS ASIC stacks can already be produced at the wafer level and separated later. In these so-called vertical integration methods, a MEMS wafer is bonded to an ASIC wafer using a metallic bonding method, with the ASIC representing the electronic evaluation circuit and at the same time the hermetic encapsulation for the MEMS element, as for example in the documents DE 19 616 014 A1 and U.S. 2006 0 208 326 A1 is revealed. These vertical integration methods are particularly attractive in combination with vias (through silicon vias, TSVs) and flip-chip technologies, which means that construction and contacting can take place as a chip-scale package. Such vertical integration methods are, for example, in the writings U.S. 2012 0 049 299 A1 and U.S. 2012 0 235 251 A1 disclosed. Such arrangements allow particularly small sizes, both in terms of base area and height.

A disadvantage of the vertical integration method is the requirement that the areas of the ASIC and MEMS must be exactly identical. As a result, the larger chip always determines the total area, and the other chip, which could actually be made smaller, has to be artificially enlarged. This leads to additional costs which, depending on the extent of the required upscaling of the chip area, can negate any cost advantages of vertical integration. In some applications, the required ASIC area will be significantly larger than the MEMS area. For such cases, Scripture shows US 2018 0 009 654 A1 a possible technical solution in which two ASIC wafers are vertically integrated with a MEMS wafer at the wafer level. However, no suggestion is made in this publication as to how arrangements could look like for cases where the total MEMS area is significantly larger than the required ASIC area.

object of the invention

It is the object of the invention to provide a micromechanical device in which the footprint of the ASIC substrate is smaller than the combined footprint of the two MEMS substrates.

Advantages of the Invention

The object is achieved according to the invention by a micromechanical device with a stack of two MEMS substrates and an ASIC substrate arranged between them.

The invention also relates to a method for manufacturing a stacked micromechanical device with a first MEMS wafer, an ASIC wafer and a second MEMS wafer. For this purpose, a triple wafer stack consisting of two MEMS wafers and one ASIC wafer is produced, with the ASIC wafer being arranged between the two MEMS wafers. The mechanical and electrical connection, i.e. also the production of the electrical contacts both between the first MEMS wafer and the ASIC and between second MEMS wafer and ASIC is manufactured using metallic bonding processes. For this purpose, the ASIC has through contacts (through silicon vias, TSVs).

The present invention allows flexible and cost-effective production of extremely small ASIC-MEMS multistacks, in which the area required for the MEMS structures is significantly larger than the area required for the CMOS-ASIC.
Savings in the packaging process are particularly advantageous. This is especially true for comparatively small chips, since the packaging processes, in particular forming the stack of ASIC and MEMS, forming electrical contacts, applying TSVs, and arranging solder balls are essentially carried out at wafer level, i.e. the cheaper the more chips per Wafers can be placed.

The invention enables a micromechanical device with an extremely small size, both in terms of height and footprint. A reduction in the base area is advantageously possible in that the MEMS chips are stacked according to the invention and not next to one another. A reduction in the overall height of the stack is advantageously possible by thinning back the mutually stabilizing stack at the end of the production process instead of producing intrinsically stable individual wafers.

Savings in the packaging process are advantageously possible and disadvantages of conventional methods, such as a negative influence of molding compound or adhesive on the performance of the micromechanical device, can be avoided. The MEMS-CMOS-MEMS stack can advantageously be used as a bare die or chip scale package. Alternatively, further installation in a standard mold housing is also possible.

An advantageous embodiment of the device according to the invention provides that at least one of the two MEMS wafers also has TSVs. Advantageously, all electrical structures in a triple wafer stack can be electrically contacted from one side.

An advantageous embodiment of the device according to the invention provides that a partial area of the first or second MEMS substrate is removed and electrical contacts are arranged on the ASIC substrate in this partial area. In this way, the application of TSVs in one of the MEMS wafers can advantageously be dispensed with.

An advantageous embodiment of the device according to the invention provides that the ASIC has a depression on the non-active side, at least in partial areas, which provides an enlarged cavern volume for a MEMS element on one of the two MEMS wafers.

An advantageous embodiment of the device according to the invention provides that the metallic bond between the first MEMS wafer and the ASIC substrate or between the second MEMS wafer and the ASIC substrate forms a hermetic seal of a MEMS cavity.

An advantageous embodiment of the device according to the invention provides that a different internal pressure is set in the cavity formed by the first MEMS wafer and ASIC substrate than in the cavity formed by the second MEMS wafer and ASIC substrate. Advantageously, a yaw rate sensor on the first MEMS substrate and an acceleration sensor on the second MEMS substrate, for example, can thus be operated at optimum internal pressure in each case.

An advantageous embodiment of the device according to the invention provides that a yaw rate sensor is arranged on one of the two MEMS substrates and an acceleration sensor is arranged on the other of the two MEMS substrates.

character list

• 1 shows a schematic of a MEMS-ASIC-MEMS stack according to the invention in a first exemplary embodiment.
• 2 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a second embodiment.
• 3 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a third embodiment.
• 4 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a fourth embodiment.
• 5 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a fifth embodiment.
• 6 12 schematically shows a method according to the invention for producing a stacked micromechanical device.

description

The device according to the invention can be manufactured at the wafer level and then divided into chips. The figures each show the isolated device with three stacked one on top of the other ten substrates. Alternatively, the invention is described with reference to wafers, where this appears to make sense, particularly with regard to the manufacturing process.

1 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a first embodiment. A micromechanical device is shown with a first MEMS substrate 10, a second MEMS substrate 20 and an ASIC substrate 30, the three substrates (10, 20, 30) being stacked on top of one another. In this case, the ASIC substrate is arranged between the first MEMS substrate and the second MEMS substrate. The ASIC substrate is mechanically connected and electrically contacted to the first MEMS substrate by means of a first metallic bond connection 15 and to the second MEMS substrate by means of a second metallic bond connection 25 . The ASIC substrate, the first MEMS substrate and the first metal bond connection surround a first cavern 91. The ASIC substrate, the second MEMS substrate and the second metal bond connection surround a second cavern 92. The ASIC substrate has vias (through silicon vias, TSVs) 35, which are electrically conductively connected to the first MEMS substrate and the second MEMS substrate. The second MEMS substrate 20 also has vias 35 and solder balls 50 on an outer surface for contacting.

MEMS and ASIC substrates have actual functional areas 40 which are each arranged on or near a substrate surface. Each wafer thus has an active side and a passive side. With the help of the vertically arranged TSVs 35, electrical signals can be routed from the active to the passive side of the wafer or substrate. The metallic bond connections 15, 25 on the outer edge of the chip produce the mechanical connection between the corresponding MEMS and the ASIC. In addition, small electrical contacts can also be made between the MEMS and ASIC wafers via the metallic bonds (these are shown in the simplified 1 not shown separately). The bonding connection can particularly preferably be carried out all around the entire outer edge of the future chip in order to form hermetically sealed cavities and thus set a defined gas pressure in the cavity, which is necessary for operating an acceleration or yaw rate sensor, for example. In addition, the functional areas of MEMS and ASIC can be protected against environmental influences such as moisture, harmful gases and particles.

The ASIC substrate 30 also has a rear recess 80 which is opposite the functional area 40 of the second MEMS substrate 20 and thus forms an enlarged second cavity 92 .

In the following, an inventive manufacturing method for the arrangement of 1 described. The two MEMS wafers and the ASIC are first pre-processed individually, in particular all relevant functional structures are created on the respective active wafer side. In the ASIC wafer, TSVs are optionally placed ahead of the first wafer bonding. The first (in 1 the top) MEMS wafer is then bonded to the ASIC wafer with the active sides of the two wafers facing each other. The ASIC wafer is then thinned back (preferably only after wafer bonding, in order to still be able to use a wafer assembly that is as stable as possible during bonding), preferably to thicknesses between 30 and 200 μm. If vias (TSVs) were already pre-laid, they will be exposed when looping back. Otherwise, the TSVs are now manufactured, e.g. B. via a trench process sequence from the passive ASIC side through the entire ASIC substrate with a stop on oxide, isolating the side walls of the resulting trench using oxide, opening the oxide insulation at the bottom of the TSVs, metallic layer deposition to produce the electrical connection between the passive and the active ASIC side. The metallic layer deposition can also be used in addition to the rewiring (Redistribution Layer, RDL) on the passive side of the ASIC. Optionally, the ASIC substrate is etched locally on the passive ASIC side in order to provide a cavity for the MEMS functional structures on the second wafer. In the next step, the second MEMS wafer is bonded with its active side against the passive side of the ASIC. Here, too, a metallic bonding process is used in order to be able to route electrical signals between the wafers via dedicated metallic bonding contacts, for example to control and read out the MEMS functional structures. In this case too, wafer bonding is preferably used to produce a hermetic bonding frame between the ASIC and the second MEMS wafer. After the second wafer bonding, the second MEMS wafer and optionally also the first MEMS wafer are back-thinned to the target thickness. If the target thickness of the first MEMS wafer is very small, this wafer is preferably thinned back at a later point in time in order to be able to use a sufficiently thick, i.e. stable, wafer assembly for the remaining process steps. In the arrangement of 1 the second MEMS wafer also requires TSVs. These are created after the second MEMS wafer has been thinned back, for example using the method already described for creating the ASIC-TSVs. Also here the metallic layer deposition for the electrically conductive TSV sidewall can be used as RDL on the passive MEMS side. The MEMS TSVs are usually not required for the MEMS signals themselves, because they only rarely have to be read externally, but to transmit the signals between the ASIC and the circuit board, i.e. to be able to control and read the ASIC from the outside. This is followed by the arrangement of solder balls to provide electrical contacts on an application circuit board (PCB). If this has not already happened before, the first MEMS wafer is now also thinned back to the target thickness.

During the manufacturing process shown, two manufacturing steps of metallic bonding take place one after the other. In order to prevent the first bonding connection from melting during the second bonding process, a material system is required for the first bonding that does not melt during the second bonding. This can be ensured, for example, by using aluminum on one side and germanium on the other side during the first bonding, with at least one of the bonding layers being in contact with silicon. When heated to temperatures above 420°C, aluminum and germanium begin to mix, but silicon also diffuses into the metallic compound, resulting in a ternary system that requires a significantly higher temperature load for remelting. It is therefore possible to use a combination of Al and Ge also in the second wafer bonding without damaging the first bond connection. Alternatively, it is of course possible to use two material systems with different softening points, e.g. B. Al-Ge for the first wafer bonding and Cu-Sn, which requires lower bonding temperatures, for the second wafer bonding.

Different gas pressures or gas compositions can be provided in the wafer bonding chamber for the first and second wafer bonding. It is therefore possible to set a first internal pressure in the first cavity 91 formed by the first MEMS substrate 10 and ASIC substrate 30 and a second internal pressure in the second cavity 92 formed by the second MEMS substrate 20 and ASIC substrate 30 .

For example, a rotation rate sensor can be arranged on the first MEMS substrate 10 and subjected to low internal pressure in the first cavern 91 formed by the MEMS substrate 10 and ASIC substrate 30, while an acceleration sensor is arranged on the second MEMS substrate 10 and has a significantly higher pressure Internal pressure in the second cavity 92 formed by the MEMS substrate 20 and ASIC substrate 30 can be applied. It is also possible, for example, to use a first gas, e.g. B. nitrogen for the rotation rate sensor, and the second wafer bonding in order to increase the viscous damping of the acceleration sensor, a second gas, z. As neon to use. The gas composition is not limited to a single gas, but can also be a gas mixture.

2 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a second embodiment.

The second exemplary embodiment differs from the first in that partial areas of the second MEMS wafer 20 were removed after the second wafer bonding, for example by means of a sawing process or via a trenching process, and the external electrical contact is made directly on the passive side of the ASIC by means of larger solder balls 50 . In this arrangement, no TSVs are needed in any of the MEMS wafers.

3 schematically shows a MEMS-ASIC-MEMS stack according to the invention in a third exemplary embodiment.

The third exemplary embodiment differs from the second in that the ASIC wafer 30 is arranged upside down, ie the active side with the functional area 40 faces the second (lower) MEMS wafer 20 . As a result, the electrical signals of the ASIC itself are no longer routed via TSVs, but direct contact is made between the ASIC and a printed circuit board via large solder balls 50. In this exemplary embodiment, the TSVs 35 of the ASIC are used to transmit the signals between the first (upper) To lead MEMS wafer 10 and the ASIC.

The ASIC substrate 30 also has a rear recess 80 which is opposite the functional area 40 of the first MEMS substrate 10 and thus forms an enlarged first cavity 91 .

4 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a fourth embodiment.

The fourth exemplary embodiment differs from the first essentially in that the electrical signals of the ASIC 30 are now routed through the upper MEMS wafer 10 via TSVs 35 rather than through the lower MEMS wafer 20 via TSVs 35 . For example, the component could be glued to an LGA substrate and the ASIC signals could be tapped via bonding wires. Alternatively (not specifically illustrated) it is Of course, it is possible to arrange solder balls on the upper MEMS wafer and then to arrange the component upside down as a chip scale package directly on an application circuit board.

5 shows schematically a MEMS-ASIC-MEMS stack according to the invention in a fifth embodiment.

In contrast to the fourth exemplary embodiment, a partial area of the first MEMS wafer 10 has been removed here. This is done in turn by means of a sawing or trenching process in order to expose electrical bonding pads on the ASIC 30 and to enable the electrical contacting of the component by means of bonding wires 70 in an LGA housing, for example. The upper MEMS wafer 10 then does not require any TSVs.

It is obvious and therefore not specifically illustrated that in the basic arrangement of 5 the exposure of electrical connections of the ASIC could also be done on two sides of the chip. Thus, the arrangement of large solder balls would be similar to that in 3 , but now possible next to the top MEMS chip to create a chip scale package that could be flipped directly onto a circuit board.

6 12 schematically shows a method according to the invention for producing a stacked micromechanical device.

• A: Bereitstellen eines ersten MEMS-Wafers und eines ASIC-Wafers;
• B: Herstellen einer ersten metallischen Bondverbindung durch Waferbonden des ASIC-Wafers auf den ersten MEMS-Wafer;
• C: Bereitstellen eines zweiten MEMS-Wafers;
• D: Herstellen einer zweiten metallischen Bondverbindung durch Waferbonden des zweiten MEMS-Wafers auf den ASIC-Wafer.

The procedure includes the steps:

• A: Providing a first MEMS wafer and an ASIC wafer;
• B: Establishing a first metal bonding connection by wafer bonding the ASIC wafer onto the first MEMS wafer;
• C: providing a second MEMS wafer;
• D: Establishing a second metallic bond connection by wafer bonding the second MEMS wafer to the ASIC wafer.

Reference List

10

first MEMS substrate

15

first metallic bond connection

20

second MEMS substrate

25

second metallic bond connection

30

ASIC substrate

35

Via (TSV)

40

functional area

50

solder ball

70

bonding wire

80

rear recess

91

first cavern

92

second cavern

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• DE 19616014 A1 [0003]
• US20060208326A1 [0003]
• US20120049299A1[0003]
• US20120235251A1 [0003]
• US20180009654A1 [0004]

Claims (13)

Micromechanical device with a first MEMS substrate (10), a second MEMS substrate (20) and an ASIC substrate (30), wherein the substrates (10, 20, 30) are stacked on top of each other, such that - the ASIC substrate is arranged between the first MEMS substrate and the second MEMS substrate, - the ASIC substrate is mechanically connected and electrically contacted to the first MEMS substrate by means of a first metal bond connection (15) and to the second MEMS substrate by means of a second metal bond connection (25), and - The ASIC substrate has at least one via (35) which is electrically conductively connected to the first MEMS substrate and/or to the second MEMS substrate. micromechanical device claim 1 , characterized in that the first MEMS substrate (10) and / or the second MEMS substrate (20) has a via (35). micromechanical device claim 1 or 2 , characterized in that at least a portion of the first MEMS substrate (10) and / or the second MEMS substrate (20) is removed and in this portion at least one electrical contact on the active and / or passive side of the ASIC substrate (30) is arranged. Micromechanical device according to one of the preceding claims, characterized in that the ASIC substrate (30) has a rear recess (80) which is opposite a functional area (40) of one of the two MEMS substrates (10, 20) and thus an enlarged cavern forms. Micromechanical device according to one of the preceding claims, characterized in that the first metallic bond connection (15) between the first MEMS substrate (10) and the ASIC substrate (30) and / or the second metallic bond connection (25) between the second MEMS - Substrate (20) and the ASIC substrate (30) forms a hermetic seal. Micromechanical device according to one of the preceding claims, characterized in that in a first cavity (91) formed by the first MEMS substrate (10) and the ASIC substrate (30) a different gas pressure and/or a different gas composition than in one of the second MEMS substrate (20) and the ASIC substrate (30) formed second cavity (92) is present. Micromechanical device according to one of the preceding claims, characterized in that a yaw rate sensor is arranged on the first MEMS substrate (10) and an acceleration sensor is arranged on the second MEMS substrate (20), or vice versa. A method of making a stacked micromechanical device, comprising the steps of: A: Providing a first MEMS wafer and an ASIC wafer; B: Establishing a first metal bonding connection by wafer bonding the ASIC wafer onto the first MEMS wafer; C: providing a second MEMS wafer; D: Establishing a second metallic bond connection by wafer bonding the second MEMS wafer to the ASIC wafer. Method of making a stacked micromechanical device claim 8 , characterized in that at least in step B, two metals or semi-metals are used to produce the first metallic bond connection, which form a ternary system with a substrate material, which requires a higher temperature for remelting than the melting temperature of a material system made only of the two metals or semimetals. Method of making a stacked micromechanical device claim 9 , characterized in that in step A at least one wafer is provided with the substrate material silicon, and in step B aluminum and germanium are used to produce the first metallic bonding connection. Method of making a stacked micromechanical device claim 10 , characterized in that in step A, two metals or semi-metals are used to produce the first metallic bond connection, which require a higher temperature for remelting than the melting temperature of a material system made of two metals or semi-metals, which in step D for producing the second metallic Bond connection are used. Method of making a stacked micromechanical device claim 11 , characterized in that aluminum and germanium are used in step B for producing the first metallic bond connection and in step D for producing the second metalli mechanical bond copper and tin can be used. Method of making a stacked micromechanical device claim 8 , characterized in that in step B when producing the first metallic bond connection, a different gas pressure and/or a different gas composition is used than in step D when producing the second metallic bond connection.

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