DE102009004725A1 - Through-hole semiconductor circuit and method of manufacturing vertically integrated circuits - Google Patents
Through-hole semiconductor circuit and method of manufacturing vertically integrated circuits Download PDFInfo
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- DE102009004725A1 DE102009004725A1 DE200910004725 DE102009004725A DE102009004725A1 DE 102009004725 A1 DE102009004725 A1 DE 102009004725A1 DE 200910004725 DE200910004725 DE 200910004725 DE 102009004725 A DE102009004725 A DE 102009004725A DE 102009004725 A1 DE102009004725 A1 DE 102009004725A1
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
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Abstract
Halbleiterbauelemente (S1, S2) sind mittels einer Verbindungsschicht (5) miteinander verbunden. Eine Anschlusskontaktschicht (17) ist über eine Metallisierung (11) in einem Kontaktloch (14) mit einer Anschlussmetallschicht (12) verbunden. Die Anschlusskontaktschicht und die Anschlussmetallschicht können mit einer Metallebene (7) einer Verdrahtung verbunden sein oder mit einer Kontaktfläche zum Anschluss eines weiteren Halbleiterbauelementes.Semiconductor devices (S1, S2) are interconnected by means of a connection layer (5). A terminal contact layer (17) is connected to a terminal metal layer (12) via a metallization (11) in a contact hole (14). The terminal contact layer and the terminal metal layer may be connected to a metal level (7) of a wiring or to a contact area for connecting a further semiconductor component.
Description
Die vorliegende Erfindung betrifft Anordnungen von Halbleiterbauelementen, bei denen mindestens ein Halbleiterbauelement mit einer Durchkontaktierung durch das Substrat versehen ist, sowie die Herstellung vertikal oder kubisch integrierter Schaltungen.The The present invention relates to arrangements of semiconductor devices, in which at least one semiconductor device with a via is provided by the substrate, as well as the production vertically or cubic integrated circuits.
Zur
Herstellung komplexer Halbleiterschaltungen können Halbleiterchips
gestapelt und durch elektrische Anschlusskontakte auf den Oberseiten und
Unterseiten miteinander verbunden werden. Hierzu müssen
elektrisch leitende Verbindungen von der jeweiligen Oberseite eines
Chips zu der Unterseite durch das Substrat hindurch hergestellt
werden. Das geschieht üblicherweise, indem Kontaktlöcher
in das Substrat geätzt und anschließend mit Metall
oder einem anderen elektrisch leitfähigen Material gefüllt werden.
Falls der elektrische Leiter, der so hergestellt wird, nicht bis
auf die Rückseite des Substrates reicht, wird das Substrat
von der Rückseite her durch Abschleifen gedünnt,
bis das elektrisch leitfähige Material der Kontaktlochfüllung
freigelegt ist. Zum Anschließen der Durchkontaktierung
können auf die Oberflächen des Bauelementes Metallschichten
aufgebracht und entsprechend den vorgesehenen Anschlüssen
strukturiert werden. Beim Stapeln der Chips werden die zueinander
gehörenden Anschlusskontaktflächen übereinander
angeordnet und zum Beispiel mittels eines Lotes elektrisch leitend dauerhaft
verbunden. (
Übliche
Verfahren erzeugen Durchkontaktierungen mit Durchmessern von 10 μm
bis 50 μm, wobei die Kontaktlöcher mit Kupfer
(
Größer
dimensionierte Durchkontaktierungen in Halbleiterwafern werden zum
Beispiel durch Ätzen größerer Ausnehmungen
mit schrägen Seitenwänden, zum Beispiel unter
Verwendung von KOH, hergestellt. Eine in der Ausnehmung aufgebrachte Metallschicht
wird von der gegenüberliegenden Oberseite des Wafers her
freigelegt und dort mit einem Kontakt versehen. Bisher übliche
Verfahren sind beschrieben in
In
der
In
der
Aufgabe der vorliegenden Erfindung ist es, eine neue Integrationstechnik anzugeben, die Möglichkeiten zur vereinfachten Herstellung vertikal integrierter Schaltungen aufzeigt.task It is the object of the present invention to provide a new integration technique specify the possibilities for simplified production vertically integrated circuits shows.
Diese Aufgabe wird mit der Halbleiterschaltung mit Durchkontaktierung mit den Merkmalen des Anspruches 1 beziehungsweise mit dem Verfahren zur Herstellung vertikal integrierter Schaltungen mit den Merkmalen des Anspruches 12 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the semiconductor circuit with via with the features of claim 1 and with the method for Production of vertically integrated circuits with the features of claim 12 solved. Embodiments arise from the dependent claims.
Bei der Halbleiterschaltung sind ein erstes Halbleiterbauelement mit einem ersten Substrat, das mit einem Bauelement oder einer integrierten Schaltung versehen ist, und ein zweites Halbleiterbauelement mit einem zweiten Substrat, das ebenfalls mit einem Bauelement oder einer integrierten Schaltung versehen ist, mittels einer Verbindungsschicht dauerhaft miteinander verbunden. Die Halbleiterbauelemente befinden sich bei der Herstellung der Halbleiterschaltung vorzugsweise noch im Verbund eines jeweiligen Halbleiter-Wafers, und die Halbleiter-Wafer werden durch einen an sich bekannten Prozess des Wafer-Bonding miteinander verbunden. Zu diesem Zweck wird zumindest einer der miteinander zu verbindenden Halbleiter-Wafer auf einer Oberseite mit einer Verbindungsschicht oder Bond-Schicht versehen. Die Verbindungsschicht kann zum Beispiel ein Oxid des Halbleitermaterials, insbesondere Siliziumdioxid, sein. Der andere Wafer wird auf der Verbindungsschicht angeordnet und dauerhaft darauf befestigt. Diese Anordnung aus zwei Halbleiterkörpern und der dazwischen vorhandenen Verbindungsschicht ist für eine Anwendung des eingangs beschriebenen Herstellungsverfahrens geeignet, bei dem eine Durchkontaktierung hergestellt wird, indem eine Metallisierung auf ein in einem Kontaktloch freigelegtes Anschlusspad und auf die Seitenwände des Kontaktloches aufgebracht wird. Eine oberseitig angeordnete Anschlussmetallschicht ist mit der Metallisierung elektrisch leitend verbunden und vervollständigt die Durchkontaktierung. Als Anschlusspad ist eine beliebige Anschlusskontaktschicht geeignet, insbesondere eine Metallschicht, zum Beispiel eine Metallebene einer Verdrahtung. Wenn die mit einer Bauelementstruktur, einer Schaltung und/oder einer Verdrahtung versehene oder in sonstiger Weise prozessierte Seite eines Halbleiter-Wafers oder Substrates als Vorderseite des Halbleiterbauelementes und die gegenüberliegende Seite als dessen Rückseite bezeichnet wird, können das erste Halbleiterbauelement und das zweite Halbleiterbauelement mit ihren Vorderseiten, mit ihren Rückseiten oder mit einer Vorderseite und einer Rückseite miteinander verbunden werden. Daraus ergeben sich unterschiedliche Ausführungsformen der Halbleiterschaltung. Eine Oberseite eines Halbleiterbauelementes, die von dem anderen Halbleiterbauelement abgewandt ist, kann bei der Halbleiterschaltung zur Aufnahme weiterer Komponenten vorgesehen werden.In the semiconductor circuit, a first semiconductor device having a first substrate provided with a device or an integrated circuit and a second semiconductor device having a second substrate also provided with a device or an integrated circuit are permanently connected to each other by means of a connection layer , In the production of the semiconductor circuit, the semiconductor components are preferably still in the combination of one each The semiconductor wafers and the semiconductor wafers are interconnected by a per se known process of wafer bonding. For this purpose, at least one of the semiconductor wafers to be connected to one another is provided on an upper side with a connection layer or bonding layer. The bonding layer may be, for example, an oxide of the semiconductor material, in particular silicon dioxide. The other wafer is placed on the tie layer and permanently attached thereto. This arrangement of two semiconductor bodies and the connecting layer therebetween is suitable for an application of the manufacturing method described in the introduction, in which a via is produced by applying a metallization to a contact pad exposed in a contact hole and to the side walls of the contact hole. A terminal metal layer arranged on the upper side is electrically conductively connected to the metallization and completes the through-connection. Any connection contact layer is suitable as a connection pad, in particular a metal layer, for example a metal plane of a wiring. If the side of a semiconductor wafer or substrate provided with a component structure, a circuit and / or a wiring or otherwise processed is referred to as the front side of the semiconductor component and the opposite side as its back side, the first semiconductor component and the second semiconductor component can be connected to their Front sides, with their backs or with a front and a back connected to each other. This results in different embodiments of the semiconductor circuit. An upper side of a semiconductor device, which is remote from the other semiconductor device, may be provided in the semiconductor circuit for receiving further components.
Die Anschlusskontaktschicht kann ein Diffusionsbereich in einem Substrat sein und zum Beispiel durch Einbringen von Dotierstoff in einen Bereich des Halbleitermateriales hergestellt werden. Vorzugsweise befindet sich der Diffusionsbereich an einer Vorderseite eines Substrates, über der Metallebenen einer Verdrahtung angeordnet sind.The Terminal contact layer may be a diffusion region in a substrate and, for example, by introducing dopant into one Be prepared area of the semiconductor material. Preferably the diffusion region is at a front side of a substrate, over the metal levels of a wiring are arranged.
Die Durchkontaktierung kann in nur einem der Halbleiterbauelemente oder in beiden Halbleiterbauelementen vorhanden sein. Wenn die Durchkontaktierung in beiden Halbleiterbauelementen vorgesehen ist, können die Verbindungsschicht und die Anschlusskontaktschicht auf verschiedenen Seiten eines der Halbleiter-Wafer angeordnet werden und das Kontaktloch zur Aufnahme der Metallisierung der Durchkontaktierung durch beide Halbleiter-Wafer hindurch geätzt werden. Statt dessen kann die Anschlusskontaktschicht zwischen den verbundenen Halbleiter-Wafern angeordnet werden. In diesem Fall werden in beide Halbleiter-Wafer Kontaktlöcher jeweils bis zu der Anschlusskontaktschicht geätzt und die Kontaktlöcher mit Metallisierungen versehen, die die Anschlusskontaktschicht auf einander gegenüberliegenden Seiten kontaktieren.The Through-hole can be in only one of the semiconductor devices or be present in both semiconductor devices. If the feedthrough is provided in both semiconductor devices, can the connection layer and the terminal contact layer on different Sides of one of the semiconductor wafers are arranged and the contact hole for receiving the metallization of the via through both Etched through semiconductor wafers. Instead, you can the terminal contact layer between the connected semiconductor wafers to be ordered. In this case, in both semiconductor wafers Contact holes each up to the terminal contact layer etched and the contact holes with metallizations provided that the terminal contact layer on opposite one another Contact pages.
Die Metallisierung der Durchkontaktierung ist vorzugsweise von dem Halbleitermaterial des betreffenden Substrates durch eine auf der Seitenwand des Kontaktloches vorhandene Seitenwandisolation elektrisch isoliert. Die Metallisierung der Durchkontaktierung kann zwei oder mehrere Anschlusskontaktschichten gleichzeitig kontaktieren. Zwei oder mehr Durchkontaktierungen in demselben Halbleiterbauelement können zu Anschlusskontaktflächen verschiedener Metallebenen desselben Halbleiterbauelementes oder beider Halbleiterbauelemente geführt sein.The Metallization of the via is preferably of the semiconductor material of the relevant substrate by a on the side wall of the contact hole existing sidewall insulation electrically isolated. The metallization the via may include two or more terminal contact layers contact at the same time. Two or more vias in the same semiconductor device can to terminal contact surfaces different metal levels of the same semiconductor device or be guided both semiconductor devices.
Bei Ausführungsbeispielen ist ein mikromechanischer Sensor, wie zum Beispiel ein Drucksensor oder ein auf Trägheitskräfte ansprechender Beschleunigungssensor oder Drehratensensor in einem Halbleiterbauelement eingebaut. Bei einer solchen Ausführungsform kann in der mit der Verbindungsschicht versehenen Vorderseite des einen Halbleiterbauelementes mindestens ein elektrisch leitfähiges Element eines Sensors angeordnet sein, das mit der Anschlusskontaktschicht elektrisch leitend verbunden ist. Das elektrisch leitfähige Element ist zum Beispiel eine Elektrode eines kapazitiv messenden Beschleunigungssensors mit Trägheitselement. Derartige Sensoren sind an sich bekannt und können in Verbindung mit der Halbleiterschaltung eingesetzt werden. Bei einem Drucksensor kann das elektrisch leitfähige Element eine zumindest bereichsweise elektrisch leitfähige Membran sein, die über einer Aussparung in der Vorderseite eines auf der Rückseite mit der Verbindungsschicht versehenen Halbleiterbauelementes angeordnet und mit der Anschlusskontaktschicht elektrisch leitend verbunden ist.at Exemplary embodiments is a micromechanical sensor, such as a pressure sensor or inertial forces responsive acceleration sensor or yaw rate sensor in a semiconductor device built-in. In such an embodiment, in the front side of the one semiconductor device provided with the connection layer at least one electrically conductive element of a sensor be arranged with the terminal contact layer electrically is conductively connected. The electrically conductive element is, for example, an electrode of a capacitive acceleration sensor with inertia element. Such sensors are known per se and may be used in conjunction with the semiconductor circuit become. In a pressure sensor, the electrically conductive Element an at least partially electrically conductive Membrane that has a recess in the front one provided with the tie layer on the back Semiconductor component arranged and with the terminal contact layer is electrically connected.
Auf der Anschlussmetallschicht der Durchkontaktierung kann eine Kontaktfläche zum Aufbringen einer Lotkugel vorgesehen sein. Statt dessen kann die Anschlussmetallschicht zu einer Metallebene der Verdrahtung des betreffenden Halbleiterbauelementes gehören oder mit einer Metallebene der Verdrahtung elektrisch leitend verbunden sein. Ausgestaltungen der Halb leiterschaltung sehen vor, dass die Anschlussmetallschicht mit einem Anschlussleiter eines Oberflächensensors versehen ist und eine Leiterstruktur, zum Beispiel für einen biologischen Sensor, auf der betreffenden Oberseite der Halbleiterschaltung vorhanden ist.On The terminal metal layer of the via can have a contact surface be provided for applying a solder ball. Instead, you can the terminal metal layer to a metal level of the wiring belonging to the semiconductor device concerned or with a metal level of the wiring to be electrically connected. Embodiments of the semiconductor circuit provide that the terminal metal layer provided with a connection conductor of a surface sensor is and a ladder structure, for example for a biological sensor, present on the relevant upper side of the semiconductor circuit is.
Es folgt eine genauere Beschreibung von Beispielen der Halbleiterschaltung und des Herstellungsverfahrens anhand der beigefügten Figuren.It follows a more detailed description of examples of the semiconductor circuit and the manufacturing process with reference to the attached figures.
Die
Die
mit mindestens einer Metallebene
An
der Vorderseite F1 des ersten Halbleiterbauelementes S1 befindet
sich eine Anschlusskontaktschicht
Auf
der von der Verbindungsschicht
Das
Ausführungsbeispiel der
Die
Die
Anschlussmetallschicht
Die
Die
Die
Bei
der Herstellung der Durchkontaktierung des Ausführungsbeispiels
der
Anstatt
das Kontaktloch
Die
Falls
das Kontaktloch in einem ersten Ätzschritt nur durch das
zweite Substrat
Das
weitere Ausführungsbeispiel gemäß der
Das
weitere Ausführungsbeispiel gemäß der
Das
weitere Ausführungsbeispiel gemäß der
Die
Die
Leiterbahn
Das
weitere Ausführungsbeispiel gemäß der
Das
weitere Ausführungsbeispiel gemäß der
Das
Ausführungsbeispiel gemäß der
Das
Ausführungsbeispiel gemäß der
Die Möglichkeiten dieser Integrationstechnik sind nicht auf die beschriebenen Ausführungsbeispiele beschränkt. Die Merkmale der verschiedenen Ausgestaltungen können auf vielfältige Weise miteinander kombiniert werden, so dass eine Vielfalt von vertikal integrierten Halbleiterschaltungen auf einfache Weise mit den beschriebenen Durchkontaktierungen realisierbar ist. Die Anschlusskontaktschicht kann in verschiedenen Schichtlagen angeordnet und durch eine Metallschicht oder einen Diffusionsbereich gebildet sein. Die Anschlussmetallschicht kann für einen internen Anschluss an die Verdrahtung der Halbleiterschaltung, für einen externen Anschluss an ein weiteres Halbleiterbauelement oder sowohl für einen internen als auch für einen externen Anschluss vorgesehen sein. Die Durchkontaktierung kann so ausgestaltet sein, dass sie nur ein Substrat oder dass sie beide Substrate umfasst. Die Metallisierung der Durchkontaktierung kann so ausgestaltet sein, dass sie nur eine Anschlusskontaktschicht oder dass sie zwei oder mehrere Anschlusskontaktschichten kontaktiert. Es können beliebig viele Durchkontaktierungen in beiden Substraten vorhanden sein, die jeweils Anschlusskontaktschichten in verschiedenen Schichtlagen kontaktieren können. Diese und andere beschriebene Merkmale können weitgehend unabhängig voneinander ausgewählt und miteinander kombiniert werden.The Possibilities of this integration technique are not on limited the described embodiments. The features of the various embodiments can be various ways combined with each other, so that a variety of vertically integrated semiconductor circuits easy way with the vias described feasible is. The terminal contact layer may be in different layers arranged and through a metal layer or a diffusion region be formed. The terminal metal layer can for a internal connection to the wiring of the semiconductor circuit, for an external connection to another semiconductor device or for both internal and external Connection be provided. The via can be configured be that it is just a substrate or that it includes both substrates. The metallization of the via can be designed so that they have only one terminal contact layer or that they have two or more contacted several terminal contact layers. It can Any number of plated-through holes in both substrates available be, each terminal contact layers in different layers can contact. These and other features described can be selected largely independently and combined with each other.
- 11
- erstes Substratfirst substratum
- 22
- zweites Substratsecond substratum
- 33
- Isolationsschichtinsulation layer
- 44
- Zwischenmetalldielektrikumintermetal
- 55
- Verbindungsschichtlink layer
- 66
- Passivierungpassivation
- 77
- Metallebenemetal plane
- 88th
- vertikale leitende Verbindungvertical conductive connection
- 99
- Kontaktflächecontact area
- 1010
- SeitenwandisolationSidewall insulation
- 10a10a
- weitere SeitenwandisolationFurther Sidewall insulation
- 1111
- Metallisierungmetallization
- 11a11a
- weitere MetallisierungFurther metallization
- 1212
- AnschlussmetallschichtTerminal metal layer
- 12a12a
- AnschlussmetallschichtTerminal metal layer
- 1313
- Lotkugelsolder ball
- 1414
- Kontaktlochcontact hole
- 14a14a
- weiteres Kontaktlochadditional contact hole
- 1515
- Isolationsschichtinsulation layer
- 1616
- Schutzschichtprotective layer
- 1717
- AnschlusskontaktschichtConnection contact layer
- 17a17a
- AnschlusskontaktschichtConnection contact layer
- 1818
- weitere AnschlusskontaktschichtFurther Connection contact layer
- 18a18a
- weitere AnschlusskontaktschichtFurther Connection contact layer
- 18b18b
- weitere AnschlusskontaktschichtFurther Connection contact layer
- 18c18c
- weitere AnschlusskontaktschichtFurther Connection contact layer
- 1919
- Kontaktflächecontact area
- 2020
- SeitenwandisolationSidewall insulation
- 2121
- Metallisierungmetallization
- 2222
- AnschlussmetallschichtTerminal metal layer
- 2323
- Hohlraumcavity
- 2424
- Kontaktlochcontact hole
- 2525
- Biegebalkenbending beam
- 2626
- Gegenelektrodecounter electrode
- 26a26a
- Gegenelektrodecounter electrode
- 2727
- Leiterbahnconductor path
- 2828
- vertikale leitende Verbindungvertical conductive connection
- 28a28a
- vertikale leitende Verbindungvertical conductive connection
- 2929
- Anschlussleiterconnecting conductors
- 3030
- Leiterstrukturconductor structure
- 3131
- Membranmembrane
- 3232
- Aussparungrecess
- B1B1
- Rückseite des ersten Halbleiterbauelementesback of the first semiconductor device
- B2B2
- Rückseite des zweiten Halbleiterbauelementesback of the second semiconductor device
- F1F1
- Vorderseite des ersten Halbleiterbauelementesfront of the first semiconductor device
- F2F2
- Vorderseite des zweiten Halbleiterbauelementesfront of the second semiconductor device
- PP
- Drucksensorpressure sensor
- SS
- mikromechanischer Sensormicromechanical sensor
- S1S1
- erstes Halbleiterbauelementfirst Semiconductor device
- S2S2
- zweites Halbleiterbauelementsecond Semiconductor device
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
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Zitierte Nicht-PatentliteraturCited non-patent literature
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- - T. Rowbotham et al., „Back side exposure of variable size through silicon vias”, J. Vac. Sci. Techn. B24(5), 2006 [0003] T. Rowbotham et al., "Back side exposure of variable size through silicon vias", J. Vac. Sci. Techn. B24 (5), 2006 [0003]
- - E. M. Chow et al., „Process compatible polysilicon-based electrical through-wafer interconnects in silicon substrates”, J. of Micromechanical Systems, Vol. 11, No. 6, 2002 [0003] EM Chow et al., "Process-compatible polysilicon-based electrical through-wafer interconnects in silicon substrates", J. of Micromechanical Systems, Vol. 6, 2002 [0003]
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Claims (14)
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DE200910004725 DE102009004725A1 (en) | 2009-01-15 | 2009-01-15 | Through-hole semiconductor circuit and method of manufacturing vertically integrated circuits |
PCT/EP2009/067211 WO2010081603A1 (en) | 2009-01-15 | 2009-12-15 | Semiconductor circuit having interlayer connections and method for producing vertically integrated circuits |
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DE200910004725 DE102009004725A1 (en) | 2009-01-15 | 2009-01-15 | Through-hole semiconductor circuit and method of manufacturing vertically integrated circuits |
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