JP2011135064A - 積層酸化物材料、半導体装置、および半導体装置の作製方法 - Google Patents
積層酸化物材料、半導体装置、および半導体装置の作製方法 Download PDFInfo
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- JP2011135064A JP2011135064A JP2010262853A JP2010262853A JP2011135064A JP 2011135064 A JP2011135064 A JP 2011135064A JP 2010262853 A JP2010262853 A JP 2010262853A JP 2010262853 A JP2010262853 A JP 2010262853A JP 2011135064 A JP2011135064 A JP 2011135064A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract
【解決手段】下地部材上に、第1の酸化物部材を形成し、第1の加熱処理を行って表面から内部に向かって結晶成長し、下地部材に少なくとも一部接する第1の酸化物結晶部材を形成し、第1の酸化物結晶部材上に第2の酸化物部材を形成し、第2の加熱処理を行って第1の酸化物結晶部材を種として結晶成長させて第2の酸化物結晶部材を設ける積層酸化物材料の作製方法である。
【選択図】図1
Description
本実施の形態では、トランジスタの作製例の一例を図1、図2、及び図3を用いて示す。
実施の形態1は、第1の酸化物部材と第2の酸化物部材に同一成分を含む酸化物半導体材料を用いる場合を示したが、本実施の形態では異なる成分の酸化物半導体材料を用いる場合を示す。なお、図10(A)中、図1(A)と同じ部分には同じ符号を用いて説明する。
本実施の形態では、c軸配向した結晶層を有する積層酸化物材料を含むトランジスタを作製し、該トランジスタを画素部、さらには駆動回路に用いて表示機能を有する半導体装置(表示装置ともいう)を作製する場合について説明する。また、トランジスタを、駆動回路の一部または全体を、画素部と同じ基板上に一体形成し、システムオンパネルを形成することができる。
半導体装置の一形態に相当する発光表示パネル(発光パネルともいう)の外観及び断面について、図12を用いて説明する。図12は、第1の基板上に形成されたc軸配向した結晶層を有する積層酸化物材料を含むトランジスタ及び発光素子を、第2の基板との間にシール材によって封止した、パネルの平面図であり、図12(B)は、図12(A)のH−Iにおける断面図に相当する。
半導体装置の一形態として電子ペーパーの例を示す。
本明細書に開示する半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
401 ゲート電極層
402 ゲート絶縁層
403 第1の酸化物半導体層
404 第2の酸化物半導体層
405a ソース電極層
405b ドレイン電極層
407 酸化物絶縁層
430 酸化物半導体積層
431 酸化物半導体積層
432 酸化物半導体積層
470 トランジスタ
500 下地部材
501 第1の酸化物結晶部材
502 第2の酸化物部材
503a 第1の酸化物結晶部材
503b 第2の酸化物結晶部材
504 結晶領域
520 下地部材
531 第1の酸化物結晶部材
532 第2の酸化物部材
533a 酸化物結晶部材
533b 酸化物結晶部材
580 基板
581 トランジスタ
583 絶縁層
587 電極層
588 電極層
589 球形粒子
590a 黒色領域
590b 白色領域
594 キャビティ
595 充填材
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカ
2800 筐体
2801 筐体
2802 表示パネル
2803 スピーカー
2804 マイクロフォン
2805 操作キー
2806 ポインティングデバイス
2807 カメラ用レンズ
2808 外部接続端子
2810 太陽電池セル
2811 外部メモリスロット
3001 本体
3002 筐体
3003 表示部
3004 キーボード
3021 本体
3022 スタイラス
3023 表示部
3024 操作ボタン
3025 外部インターフェイス
3051 本体
3053 接眼部
3054 操作スイッチ
3055 表示部(B)
3056 バッテリー
3057 表示部(A)
4001 基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 第2の基板
4008 液晶層
4010 トランジスタ
4011 トランジスタ
4013 液晶素子
4015 接続端子電極
4016 端子電極
4018 FPC
4019 異方性導電層
4020 絶縁層
4021 絶縁層
4030 画素電極層
4031 対向電極層
4032 絶縁層
4040 導電層
4501 第1の基板
4502 画素部
4503a、4503b 信号線駆動回路
4504a、4504b 走査線駆動回路
4505 シール材
4506 第2の基板
4507 充填材
4509 トランジスタ
4510 トランジスタ
4511 発光素子
4512 電界発光層
4513 電極層
4515 接続端子電極
4516 端子電極
4517 電極層
4518a、4518b FPC
4519 異方性導電層
4520 隔壁
4540 導電層
4541 絶縁層
4543 保護絶縁層
4544 絶縁層
Claims (41)
- 下地部材上に、酸化物部材を形成し、
加熱処理を行って表面から内部に向かって結晶成長し、前記下地部材に少なくとも一部接する第1の酸化物結晶部材を形成し、
前記第1の酸化物結晶部材上に第2の酸化物結晶部材を積層して設ける積層酸化物材料の作製方法。 - 下地部材上に、酸化物部材を形成し、
加熱処理を行って表面から内部に向かって結晶成長し、前記下地部材に少なくとも一部接し、前記表面に対して垂直方向にc軸配向を有する第1の酸化物結晶部材を形成し、
前記第1の酸化物結晶部材上に前記第1の酸化物結晶部材のc軸配向と揃っているc軸配向を有する第2の酸化物結晶部材を積層して設ける積層酸化物材料の作製方法。 - 下地部材上に、酸化物部材を形成し、
加熱処理を行って表面から内部に向かって結晶成長し、前記下地部材に少なくとも一部接する第1の酸化物結晶部材を形成し、
前記第1の酸化物結晶部材上に第2の酸化物結晶部材を積層し、
前記第1の酸化物結晶部材及び前記第2の酸化物結晶部材は、表面に垂直方向にc軸配向した結晶である積層酸化物材料の作製方法。 - 請求項1乃至3のいずれか一において、前記加熱処理は、450℃以上850℃以下での窒素雰囲気、酸素雰囲気、または乾燥空気雰囲気であることを特徴とする積層酸化物材料の作製方法。
- 請求項1乃至4のいずれか一において、前記下地部材に凹部、または凸部がある結晶成長部材においては凹部、または凸部の境界に粒界を有する積層酸化物材料の作製方法。
- 請求項1乃至5のいずれか一において、第1の酸化物結晶部材及び第2の酸化物結晶部材は単結晶である積層酸化物材料の作製方法。
- 請求項1乃至6のいずれか一において、前記第2の酸化物結晶部材は、成膜中の温度を200℃以上600℃以下に加熱しながら結晶成長させて得ることを特徴とする積層酸化物材料の作製方法。
- 請求項1乃至7のいずれか一において、前記第2の酸化物結晶部材は、スパッタ法を用いて形成され、その後または成膜と同時に加熱処理がなされており、その金属酸化物ターゲットの組成比は、In:Ga:Zn=1:x:y(xは0以上2以下、yは1以上5以下)である積層酸化物材料の作製方法。
- 請求項8において、前記金属酸化物ターゲットの組成比は、In:Ga:Zn=1:x:y(xは1、yは1)である積層酸化物材料の作製方法。
- 請求項8において、前記金属酸化物ターゲットの組成比は、In:Ga:Zn=1:x:y(xは0、yは1)である積層酸化物材料の作製方法。
- 請求項1乃至10のいずれか一において、第1の酸化物結晶部材は高純度の真性の導電型である積層酸化物材料の作製方法。
- 請求項1乃至11のいずれか一において、第2の酸化物結晶部材は高純度の真性の導電型である積層酸化物材料の作製方法。
- 請求項1乃至12のいずれか一において、前記積層酸化物材料のキャリア濃度は、1.0×1012cm−3未満である積層酸化物材料の作製方法。
- 請求項1乃至13のいずれか一において、前記積層酸化物材料のキャリア濃度は、1.45×1010cm−3未満である積層酸化物材料の作製方法。
- 下地部材上に、第1の酸化物部材を形成し、
第1の加熱処理を行って表面から内部に向かって結晶成長し、下地部材に少なくとも一部接する第1の酸化物結晶部材を形成し、
前記第1の酸化物結晶部材上に第2の酸化物部材を形成し、
第2の加熱処理を行って前記第1の酸化物結晶部材を種として結晶成長させて第2の酸化物結晶部材を設ける積層酸化物材料の作製方法。 - 請求項1乃至15のいずれか一において、前記第1の酸化物結晶部材は、その表面にa−b面を有し、前記第1の酸化物結晶部材の表面に対して垂直方向にc軸配向をしていることを特徴とする積層酸化物材料の作製方法。
- 請求項1乃至16のいずれか一において、前記酸化物部材の厚さは2nm以上15nm以下を有する積層酸化物材料の作製方法。
- 下地部材上に少なくとも一部接し、且つ、第1の酸化物結晶部材の表面から内部に向かって結晶成長する第1の酸化物結晶部材と、前記第1の酸化物結晶部材上に第2の酸化物結晶部材を積層してなる積層酸化物材料。
- 下地部材上に少なくとも一部接する第1の酸化物結晶部材と、前記第1の酸化物結晶部材上に接する第2の酸化物結晶部材は、同一結晶軸を有する積層酸化物材料。
- 下地部材上に少なくとも一部接する第1の酸化物結晶部材と、前記第1の酸化物結晶部材上に接する第2の酸化物結晶部材は、一つの単結晶である積層酸化物材料。
- 請求項18乃至20のいずれか一において、表面から内部に向かって結晶成長する前記第1の酸化物結晶部材は、前記第1の酸化物結晶部材の表面にa−b面を有し、表面に対して垂直方向にc軸配向をしていることを特徴とする積層酸化物材料。
- 請求項18乃至21のいずれか一において、前記第1の酸化物結晶部材及び前記第2の酸化物結晶部材は、表面にa−b面を有し、表面に対して垂直方向にc軸配向をしていることを特徴とする積層酸化物材料。
- 請求項18乃至22のいずれか一において、下地部材は絶縁物表面または酸化物、窒化物、または金属表面を有する積層酸化物材料。
- 請求項18乃至23のいずれか一において、前記第1の酸化物結晶部材と前記第2の酸化物結晶部材は、同一成分を含む材料である積層酸化物材料。
- 請求項18乃至24のいずれか一において、前記第1の酸化物結晶部材は2nm以上10nm以下の平均厚さを有することを特徴とする積層酸化物材料。
- 請求項18乃至25のいずれか一において、前記第1の酸化物結晶部材と前記第2の酸化物結晶部材の電子親和力は同じである積層酸化物材料。
- 請求項18乃至23のいずれか一において、前記第1の酸化物結晶部材と前記第2の酸化物結晶部材の材料は異なる積層酸化物材料。
- 下地表面上に平坦表面を有するゲート電極層を形成し、
前記ゲート電極層上にゲート絶縁層を形成し、
前記ゲート絶縁層上に第1の酸化物半導体層を形成し、
第1の加熱処理を行って前記第1の酸化物半導体層の表面から内部に向かって結晶成長させて第1の単結晶層を形成し、
前記第1の単結晶層上に第2の酸化物半導体層を形成し、
第2の加熱処理を行って前記第1の単結晶層からその上の前記第2酸化物半導体層表面に向かって結晶成長させて第2の単結晶層を形成し、
前記第1の結晶層及び前記第2の単結晶層の積層上にソース電極層またはドレイン電極層を形成する半導体装置の作製方法。 - 下地表面上に平坦表面を有するゲート電極層を形成し、
前記ゲート電極層上にゲート絶縁層を形成し、
前記ゲート絶縁層上に第1の酸化物半導体層を形成し、
第1の加熱処理を行って前記第1の酸化物半導体層の表面から内部に向かって結晶成長させて第1の単結晶層を形成し、
前記第1の単結晶層上に第2の酸化物半導体層を形成し、
第2の加熱処理を行って前記第1の単結晶層からその上の前記第2酸化物半導体層表面に向かって結晶成長させて第2の単結晶層を形成し、
前記第1の結晶層及び前記第2の単結晶層の積層上にソース電極層またはドレイン電極層を形成し、
前記ゲート電極層の端部と前記ソース電極層または前記ドレイン電極層は、重なりを有し、その重なりはゲート電極層の平坦部にまで渡って設けられている半導体装置の作製方法。 - 請求項28または請求項29において、前記第1の単結晶層は、その表面にa−b面を有し、前記第1の単結晶層の表面に対して垂直方向にc軸配向をしていることを特徴とする半導体装置の作製方法。
- 請求項28乃至30のいずれか一において、前記第2の単結晶層は、その表面にa−b面を有し、前記第2の単結晶層の表面に対して垂直方向にc軸配向をしていることを特徴とする半導体装置の作製方法。
- 請求項28乃至31のいずれか一において、前記第2の酸化物半導体層の厚さは前記第1の酸化物半導体層の厚さよりも大きいことを特徴とする半導体装置の作製方法。
- 請求項28乃至32のいずれか一において、前記第1の酸化物半導体層と前記第2の酸化物半導体層の電子親和力は同じであることを特徴とする半導体装置の作製方法。
- 請求項28乃至32のいずれか一において、前記第1の酸化物半導体層と前記第2の酸化物半導体層の材料は異なることを特徴とする半導体装置の作製方法。
- 下地表面上に平坦表面を有するゲート電極層と、
前記ゲート電極層上にゲート絶縁層と、
前記ゲート絶縁層上に少なくとも一部接し、且つ、表面にa−b面を有し、表面に対して垂直方向にc軸配向をしている第1の単結晶層と、
前記第1の単結晶層上に接し、且つ、表面にa−b面を有し、表面に対して垂直方向にc軸配向をしている第2の単結晶層と、
前記第1の単結晶層及び前記第2の単結晶層の積層上にソース電極層またはドレイン電極層とを有し、
前記第1の単結晶層及び前記第2の単結晶層は、金属酸化物層であることを特徴とする半導体装置。 - 下地表面上に平坦表面を有するゲート電極層と、
前記ゲート電極層上にゲート絶縁層と、
前記ゲート絶縁層上に少なくとも一部接し、且つ、表面にa−b面を有し、表面に対して垂直方向にc軸配向をしている第1の単結晶層と、
前記第1の単結晶層上に接し、且つ、表面にa−b面を有し、表面に対して垂直方向にc軸配向をしている第2の単結晶層と、
前記第1の単結晶層及び前記第2の単結晶層の積層上にソース電極層またはドレイン電極層を有し、
前記ソース電極層または前記ドレイン電極層は、ゲート電極の平坦部の上方にまで渡って設け、ゲート電極層と重なりを有することを特徴とする半導体装置。 - 請求項35または請求項36において、前記第2の単結晶層の厚さは前記第1の単結晶層の厚さよりも大きいことを特徴とする半導体装置。
- 請求項35乃至37のいずれか一において、前記第1の単結晶層と前記第2の単結晶層の電子親和力は同じであることを特徴とする半導体装置。
- 請求項35乃至37のいずれか一において、前記第1の単結晶層と前記第2の単結晶層の材料は異なることを特徴とする半導体装置。
- 請求項35乃至39のいずれか一において、前記第2の単結晶層表面の前記ゲート電極層と重なる領域の高低差は、1nm以下であることを特徴とする半導体装置。
- 請求項35乃至39のいずれか一において、前記第2の単結晶層表面の前記ゲート電極層と重なる領域の高低差は、0.2nm以下であることを特徴とする半導体装置。
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TW201140700A (en) | 2011-11-16 |
JP5797894B2 (ja) | 2015-10-21 |
WO2011065210A1 (en) | 2011-06-03 |
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TW201614738A (en) | 2016-04-16 |
JP5303687B2 (ja) | 2013-10-02 |
JP5122016B2 (ja) | 2013-01-16 |
JP5312708B2 (ja) | 2013-10-09 |
US8765522B2 (en) | 2014-07-01 |
US20110127579A1 (en) | 2011-06-02 |
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JP2012235150A (ja) | 2012-11-29 |
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