JP2011134956A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2011134956A JP2011134956A JP2009294434A JP2009294434A JP2011134956A JP 2011134956 A JP2011134956 A JP 2011134956A JP 2009294434 A JP2009294434 A JP 2009294434A JP 2009294434 A JP2009294434 A JP 2009294434A JP 2011134956 A JP2011134956 A JP 2011134956A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- chip
- wiring
- heat dissipation
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Thermal Sciences (AREA)
Abstract
【解決手段】半導体装置10は、半導体素子(チップ)30が配線基板20に形成されたキャビティ27内にその底面との間に接着材料33を介在させて搭載され、チップの電極端子31がキャビティ周囲の基板上に形成された配線部分22a,22bにワイヤ32を介して接続された構造を有する。チップ30は、配線部分のうち他の配線に比べて高周波用の配線22aが形成されている領域に近い側のキャビティの側壁27aに密着して搭載され、チップ30を密着させた側のキャビティの底面27eに凹部28が設けられ、さらにこの凹部の底面から基板外部に繋がるサーマルビア29が設けられている。
【選択図】図1
Description
図1は本発明の第1の実施形態に係る半導体装置の構成を断面図の形態で示したものであり、図2はこの半導体装置をチップが実装される側の面から平面的に見たときの概略構成を示している。
図4は本発明の第2の実施形態に係る半導体装置の構成を断面図の形態で示したものである。
また、上述した各実施形態では、配線基板(パッケージ)の形態として樹脂基板を使用した場合を例にとって説明したが、本発明の要旨からも明らかなように、樹脂基板に限定されないことはもちろんであり、例えば、セラミック基板を使用した場合にも同様に適用することが可能である。
20,50…配線基板(パッケージ)、
22a,22b,22c,22d,23…配線(層)、
24…ソルダレジスト層(保護膜)、
27(27a〜27d,27e)…キャビティ(キャビティの側壁、底面)、
28…溝(接着剤溜め部分/凹部)、
28a,28b…凹部(接着剤溜め部分)、
29…サーマルビア(放熱用ビアホール)、
30…半導体素子(チップ)、
31…電極パッド(端子)、
32…ボンディングワイヤ、
33…チップ搭載用の接着剤(接着材料)、
ANT…アンテナ、
P1,P2,P3…パッド(ボンディング用、層間接続用、外部接続用)、
SB…はんだボール(外部接続端子)、
WR…配線形成領域。
Claims (9)
- 半導体素子が配線基板に形成されたキャビティ内にその底面との間に接着材料を介在させて搭載されるとともに、前記半導体素子の電極端子が前記キャビティの周囲の基板上に形成された配線部分にワイヤを介して接続された構造を有する半導体装置において、
前記半導体素子が、前記配線部分のうち他の配線に比べて高周波用の配線が形成されている領域に近い側の前記キャビティの側壁に密着して搭載され、
前記半導体素子を密着させた側の前記キャビティの底面に、該底面から基板外部に繋がる放熱構造が形成されていることを特徴とする半導体装置。 - 前記放熱構造を第1の放熱構造とするとともに、前記キャビティの底面の、前記第1の放熱構造が形成されている部分以外の部分に、第2の放熱構造が形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記第1の放熱構造は、前記半導体素子を密着させた側の前記キャビティの底面に設けられた凹部と、該凹部の底面から基板外部に繋がるサーマルビアを有していることを特徴とする請求項2に記載の半導体装置。
- 前記接着材料が前記凹部に充填された状態にあることを特徴とする請求項3に記載の半導体装置。
- さらに、前記半導体素子を密着させた前記キャビティの側壁に、前記凹部と一体的に繋がる別の凹部が設けられていることを特徴とする請求項4に記載の半導体装置。
- 前記第1の放熱構造は、前記半導体素子を密着させた側の前記キャビティの底面から基板外部に繋がり、かつ、前記第2の放熱構造に比べて密に形成されたサーマルビアを有していることを特徴とする請求項2に記載の半導体装置。
- 前記第1の放熱構造は、前記凹部の底面から基板外部に繋がり、かつ、前記第2の放熱構造に比べて密に形成されたサーマルビアを有していることを特徴とする請求項3に記載の半導体装置。
- 前記高周波用の配線は、ミリ波帯用の配線であることを特徴とする請求項1から7のいずれか一項に記載の半導体装置。
- 前記配線基板は、前記高周波用の配線に電気的に接続されたアンテナを有していることを特徴とする請求項1から8のいずれか一項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009294434A JP5442424B2 (ja) | 2009-12-25 | 2009-12-25 | 半導体装置 |
US12/972,894 US8373997B2 (en) | 2009-12-25 | 2010-12-20 | Semiconductor device |
US13/676,569 US8729680B2 (en) | 2009-12-25 | 2012-11-14 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009294434A JP5442424B2 (ja) | 2009-12-25 | 2009-12-25 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2011134956A true JP2011134956A (ja) | 2011-07-07 |
JP2011134956A5 JP2011134956A5 (ja) | 2012-11-15 |
JP5442424B2 JP5442424B2 (ja) | 2014-03-12 |
Family
ID=44186434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009294434A Active JP5442424B2 (ja) | 2009-12-25 | 2009-12-25 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (2) | US8373997B2 (ja) |
JP (1) | JP5442424B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012178468A (ja) * | 2011-02-25 | 2012-09-13 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2013120851A (ja) * | 2011-12-07 | 2013-06-17 | Hamamatsu Photonics Kk | センサユニット及び固体撮像装置 |
JP2013214546A (ja) * | 2012-03-30 | 2013-10-17 | Fujitsu Ten Ltd | 半導体装置、及び半導体装置の製造方法 |
JP2019129311A (ja) * | 2018-01-22 | 2019-08-01 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP2019140221A (ja) * | 2018-02-09 | 2019-08-22 | 矢崎総業株式会社 | 電子部品実装品 |
WO2021006344A1 (ja) * | 2019-07-11 | 2021-01-14 | 三菱電機株式会社 | アレイアンテナ装置 |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130187286A1 (en) * | 2011-07-25 | 2013-07-25 | Richard Schneider | Lead frameless hermetic circuit package |
US9093420B2 (en) | 2012-04-18 | 2015-07-28 | Rf Micro Devices, Inc. | Methods for fabricating high voltage field effect transistor finger terminations |
US8846452B2 (en) * | 2012-08-21 | 2014-09-30 | Infineon Technologies Ag | Semiconductor device package and methods of packaging thereof |
US9147632B2 (en) | 2012-08-24 | 2015-09-29 | Rf Micro Devices, Inc. | Semiconductor device having improved heat dissipation |
US9917080B2 (en) | 2012-08-24 | 2018-03-13 | Qorvo US. Inc. | Semiconductor device with electrical overstress (EOS) protection |
WO2014050081A1 (ja) * | 2012-09-25 | 2014-04-03 | 株式会社デンソー | 電子装置 |
US8907482B2 (en) * | 2012-11-08 | 2014-12-09 | Honeywell International Inc. | Integrated circuit package including wire bond and electrically conductive adhesive electrical connections |
US20140326856A1 (en) * | 2013-05-06 | 2014-11-06 | Omnivision Technologies, Inc. | Integrated circuit stack with low profile contacts |
JP2016012719A (ja) * | 2014-06-03 | 2016-01-21 | 住友ベークライト株式会社 | 金属ベース実装基板および金属ベース実装基板実装部材 |
US9536803B2 (en) * | 2014-09-05 | 2017-01-03 | Qorvo Us, Inc. | Integrated power module with improved isolation and thermal conductivity |
US9693445B2 (en) * | 2015-01-30 | 2017-06-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Printed circuit board with thermal via |
US10615158B2 (en) | 2015-02-04 | 2020-04-07 | Qorvo Us, Inc. | Transition frequency multiplier semiconductor device |
US10062684B2 (en) | 2015-02-04 | 2018-08-28 | Qorvo Us, Inc. | Transition frequency multiplier semiconductor device |
US10448805B2 (en) * | 2015-09-28 | 2019-10-22 | Bio-Medical Engineering (HK) Limited | Endoscopic systems, devices and methods |
EP3386277B1 (en) * | 2015-11-30 | 2022-07-06 | NSK Ltd. | Heat-dissipating substrate and electrically driven power steering device |
KR102595896B1 (ko) * | 2016-08-08 | 2023-10-30 | 삼성전자 주식회사 | 인쇄회로기판 및 이를 가지는 반도체 패키지 |
FR3073980A1 (fr) * | 2017-11-23 | 2019-05-24 | Stmicroelectronics (Grenoble 2) Sas | Capot d'encapsulation pour boitier electronique et procede de fabrication |
DE102018102144A1 (de) * | 2018-01-31 | 2019-08-01 | Tdk Electronics Ag | Elektronisches Bauelement |
KR102446108B1 (ko) * | 2018-03-23 | 2022-09-22 | 가부시키가이샤 무라타 세이사쿠쇼 | 고주파 모듈 및 통신 장치 |
DE212019000227U1 (de) * | 2018-03-23 | 2020-11-02 | Murata Manufacturing Co., Ltd. | Hochfrequenzmodul und Kommunikationsgerät |
JP2020126921A (ja) * | 2019-02-04 | 2020-08-20 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
JP2021106341A (ja) * | 2019-12-26 | 2021-07-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
US20220254699A1 (en) * | 2021-02-05 | 2022-08-11 | Advanced Semiconductor Engineering, Inc. | Semiconductor device, semiconductor package, and method of manufacturing the same |
JP2022162487A (ja) * | 2021-04-12 | 2022-10-24 | イビデン株式会社 | 配線基板及び配線基板の製造方法 |
EP4095898A1 (en) * | 2021-05-25 | 2022-11-30 | Mitsubishi Electric R&D Centre Europe B.V. | Thermally improved pcb for semiconductor power die connected by via technique and assembly using such pcb |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09283544A (ja) * | 1996-04-10 | 1997-10-31 | Toshiba Corp | 半導体装置 |
JP2002198660A (ja) * | 2000-12-27 | 2002-07-12 | Kyocera Corp | 回路基板及びその製造方法 |
WO2003023843A1 (fr) * | 2001-09-05 | 2003-03-20 | Renesas Thechnology Corp. | Dispositif a semi-conducteur, son procede de fabrication et dispositif de communication radio |
JP2003273297A (ja) * | 2002-03-14 | 2003-09-26 | Denso Corp | 電子装置 |
JP2003347460A (ja) * | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
JP2004071772A (ja) * | 2002-08-05 | 2004-03-04 | Matsushita Electric Ind Co Ltd | 高周波パッケージ |
JP2004319550A (ja) * | 2003-04-11 | 2004-11-11 | Hitachi Ltd | 半導体装置 |
JP2005353938A (ja) * | 2004-06-14 | 2005-12-22 | Renesas Technology Corp | 半導体装置 |
WO2006048932A1 (ja) * | 2004-11-04 | 2006-05-11 | Renesas Technology Corp. | 電子装置及び電子装置の製造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3292798B2 (ja) * | 1995-10-04 | 2002-06-17 | 三菱電機株式会社 | 半導体装置 |
JP2004214258A (ja) * | 2002-12-27 | 2004-07-29 | Renesas Technology Corp | 半導体モジュール |
-
2009
- 2009-12-25 JP JP2009294434A patent/JP5442424B2/ja active Active
-
2010
- 2010-12-20 US US12/972,894 patent/US8373997B2/en active Active
-
2012
- 2012-11-14 US US13/676,569 patent/US8729680B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09283544A (ja) * | 1996-04-10 | 1997-10-31 | Toshiba Corp | 半導体装置 |
JP2002198660A (ja) * | 2000-12-27 | 2002-07-12 | Kyocera Corp | 回路基板及びその製造方法 |
WO2003023843A1 (fr) * | 2001-09-05 | 2003-03-20 | Renesas Thechnology Corp. | Dispositif a semi-conducteur, son procede de fabrication et dispositif de communication radio |
JP2003273297A (ja) * | 2002-03-14 | 2003-09-26 | Denso Corp | 電子装置 |
JP2003347460A (ja) * | 2002-05-28 | 2003-12-05 | Kyocera Corp | 電子装置 |
JP2004071772A (ja) * | 2002-08-05 | 2004-03-04 | Matsushita Electric Ind Co Ltd | 高周波パッケージ |
JP2004319550A (ja) * | 2003-04-11 | 2004-11-11 | Hitachi Ltd | 半導体装置 |
JP2005353938A (ja) * | 2004-06-14 | 2005-12-22 | Renesas Technology Corp | 半導体装置 |
WO2006048932A1 (ja) * | 2004-11-04 | 2006-05-11 | Renesas Technology Corp. | 電子装置及び電子装置の製造方法 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012178468A (ja) * | 2011-02-25 | 2012-09-13 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP2013120851A (ja) * | 2011-12-07 | 2013-06-17 | Hamamatsu Photonics Kk | センサユニット及び固体撮像装置 |
US9478683B2 (en) | 2011-12-07 | 2016-10-25 | Hamamatsu Photonics K.K. | Sensor unit and solid-state imaging device |
JP2013214546A (ja) * | 2012-03-30 | 2013-10-17 | Fujitsu Ten Ltd | 半導体装置、及び半導体装置の製造方法 |
JP2019129311A (ja) * | 2018-01-22 | 2019-08-01 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP7122650B2 (ja) | 2018-01-22 | 2022-08-22 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP2019140221A (ja) * | 2018-02-09 | 2019-08-22 | 矢崎総業株式会社 | 電子部品実装品 |
JP7005111B2 (ja) | 2018-02-09 | 2022-01-21 | 矢崎総業株式会社 | 電子部品実装品 |
WO2021006344A1 (ja) * | 2019-07-11 | 2021-01-14 | 三菱電機株式会社 | アレイアンテナ装置 |
GB2598674A (en) * | 2019-07-11 | 2022-03-09 | Mitsubishi Electric Corp | Array antenna device |
GB2598674B (en) * | 2019-07-11 | 2023-07-05 | Mitsubishi Electric Corp | Array antenna Apparatus |
Also Published As
Publication number | Publication date |
---|---|
US8373997B2 (en) | 2013-02-12 |
US20130163206A1 (en) | 2013-06-27 |
JP5442424B2 (ja) | 2014-03-12 |
US20110156228A1 (en) | 2011-06-30 |
US8729680B2 (en) | 2014-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5442424B2 (ja) | 半導体装置 | |
JP5231382B2 (ja) | 半導体装置 | |
CN109411423B (zh) | 半导体封装件及包括半导体封装件的电子装置 | |
US7960827B1 (en) | Thermal via heat spreader package and method | |
KR100698526B1 (ko) | 방열층을 갖는 배선기판 및 그를 이용한 반도체 패키지 | |
TWI515844B (zh) | 具一高功率晶片和一低功率晶片的低互連寄生現象的系統 | |
KR100283636B1 (ko) | 반도체패키지및반도체실장부품 | |
JP4910439B2 (ja) | 半導体装置 | |
TWI785515B (zh) | 半導體封裝體及包含半導體封裝體之裝置 | |
KR20130089473A (ko) | 반도체 패키지 | |
KR101301782B1 (ko) | 반도체 패키지 및 그 제조 방법 | |
US11239175B2 (en) | Semiconductor package | |
JPH09326450A (ja) | 半導体装置およびその製造方法 | |
US20180240738A1 (en) | Electronic package and fabrication method thereof | |
JP2004214460A (ja) | 半導体装置 | |
JP2004071597A (ja) | 半導体モジュール | |
KR20190007980A (ko) | 고방열 팬아웃 패키지 및 그 제조방법 | |
JP2016219535A (ja) | 電子回路装置 | |
JP6982219B1 (ja) | 無線通信モジュール | |
JP2004153179A (ja) | 半導体装置および電子装置 | |
JPH11163217A (ja) | 半導体装置 | |
JP2003007914A (ja) | 半導体装置 | |
KR20120031817A (ko) | 반도체 칩 내장 기판 및 이를 포함하는 적층 반도체 패키지 | |
KR20150140977A (ko) | 반도체 패키지 장치 및 그 제조방법 | |
JP2004319905A (ja) | 高周波集積回路パッケージ及び電子装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121002 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20121002 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130813 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130820 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130917 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20131029 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131118 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131210 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131218 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5442424 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |