JP2011091394A - 誘電体とiii/v化合物との間の低欠陥界面の製造方法 - Google Patents
誘電体とiii/v化合物との間の低欠陥界面の製造方法 Download PDFInfo
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Abstract
【解決手段】本発明の方法は、(a)第1のIII−V化合物を含む露出領域を含む基板を用意するステップと、(b)その上に、第2のIII−V化合物を含む少なくとも1つの中間層を形成するステップと、(c)その後、超高真空中で基板に熱処理を施し、第1温度(T1)に到達する際、第2のIII−V化合物の表面再構成が生じて、III族元素リッチの表面を形成するようにしたステップと、(d)III族元素リッチ表面を含む基板を第2温度(T2)にして、III族元素リッチ表面をカルコゲナイドハイドライドガスを含む環境に曝して、カルコゲナイド・パッシベーション表面を形成するステップと、(e)カルコゲナイド・パッシベーション表面の上に誘電体層を形成し、誘電体層と第2のIII−V化合物との間にパッシベーション界面を形成するステップと、を含む。
【選択図】図11
Description
一態様によれば、本発明は、誘電体(材料)とIII−V化合物との間にパッシベーション(passivated)界面を製造する方法に関するものであり、該方法は下記のステップを含む。
(a)第1のIII−V化合物を含む露出領域を含む基板を用意するステップ。
(b)その上に、第2のIII−V化合物を含む少なくとも1つの中間層を形成するステップ。
(c)その後、超高真空中(ultra-high-vacuum)で基板に熱処理を施し、第1温度(T1)に到達する際、第2のIII−V化合物の表面再構成が生じて、III族元素リッチの表面を形成するようにしたステップ。
(d)III族元素リッチ表面を含む基板を第2温度(T2)にして、III族元素リッチ表面をカルコゲナイド(chalcogenide)ハイドライドガスを含む環境に曝して、カルコゲナイド・パッシベーション表面を形成するステップ。
(e)カルコゲナイド・パッシベーション表面の上に誘電体層を形成し、誘電体層と第2のIII−V化合物との間にパッシベーション界面を形成するステップ。
・露出領域を覆い、これと接触する第1中間層を形成するステップと、
・第1中間層を覆い、これと接触する第2中間層を形成するステップと、
・第2中間層を覆い、これと接触する第3中間層を形成するステップと、
・第3中間層を覆い、これと接触する第4中間層を形成するステップとを含み、
第1中間層および第3中間層は、第3のIII−V化合物を含み、第2中間層および第4中間層は、第2のIII−V化合物を含む。
・第1のIII−V化合物を含む露出領域を含む基板と、
・その上に位置し、第2のIII−V化合物を含む少なくとも1つの中間層と、
・第2のIII−V化合物を含む少なくとも1つの中間層を覆う誘電体層と、
・第2のIII−V化合物と高誘電率(high-κ)誘電体との界面に位置し、本質的にカルコゲナイド原子−III族元素原子結合から成るカルコゲナイド・パッシベーション層と、を備える。
・第1のIII−V化合物を含む露出領域を含む基板と、
・その上に位置し、第2のIII−V化合物を含む少なくとも1つの中間層と、
・第2のIII−V化合物を含む少なくとも1つの中間層を覆う誘電体層と、
・第2のIII−V化合物と誘電体材料層との界面に位置し、上述した方法に従って形成されたカルコゲナイド・パッシベーション層とを備える。
・露出領域を覆い、これと接触する第1中間層と、
・第1中間層を覆い、これと接触する第2中間層と、
・第2中間層を覆い、これと接触する第3中間層と、
・第3中間層を覆い、これと接触する第4中間層とを備え、
第1中間層および第3中間層は、第3のIII−V化合物を含み、第2中間層および第4中間層は、第2のIII−V化合物を含む。
(a)第1のIII−V化合物を含む露出領域を含む基板を用意するステップ。
(b)その上に、第2のIII−V化合物を含む少なくとも1つの中間層を形成するステップ。
(c)その後、超高真空中(ultra-high-vacuum)で前記基板に熱処理を施して、第1温度(T1)に到達する際、前記第2のIII−V化合物の表面再構成が生じて、III族元素リッチの表面を形成するようにしたステップ。
(d)前記III族元素リッチ表面を含む基板を第2温度(T2)にして、前記III族元素リッチ表面をカルコゲナイド(chalcogenide)ハイドライドガスを含む環境に曝して、カルコゲナイド・パッシベーション表面を形成するステップ。
(e)前記カルコゲナイド・パッシベーション表面の上に誘電体層を形成し、誘電体層と前記第2のIII−V化合物との間にパッシベーション界面を形成するステップ。
・露出領域を覆い、これと接触する第1中間層(3i)を形成するステップと、
・第1中間層を覆い、これと接触する第2中間層(3ii)を形成するステップと、
・第2中間層を覆い、これと接触する第3中間層(3iii)を形成するステップと、
・第3中間層を覆い、これと接触する第4中間層(3iv)を形成するステップとを含み、
第1中間層および第3中間層は、第3のIII−V化合物を含み、第2中間層および第4中間層は、第2のIII−V化合物を含む。
・第1のIII−V化合物を含む露出領域(2)を含む基板(1)と、
・その上に、第2のIII−V化合物を含む少なくとも1つの中間層(3)と、
・少なくとも1つの中間層(3)を覆う高誘電率(high-κ)誘電体層(5)とを備え、
第2のIII−V化合物と高誘電率(high-κ)誘電体層の間の界面には、カルコゲナイド・パッシベーション層(4)が形成され、カルコゲナイド元素−III族元素の結合で本質的に構成される。
・露出領域を覆い、これと接触する第1中間層(3i)と、
・第1中間層を覆い、これと接触する第2中間層(3ii)と、
・第2中間層を覆い、これと接触する第3中間層(3iii)と、
・第3中間層を覆い、これと接触する第4中間層(3iv)とを備え、
第1中間層および第3中間層は、第3のIII−V化合物を含み、第2中間層および第4中間層は、第2のIII−V化合物を含む。
分子線エピタキシー・マルチチャンバ・クラスターシステムを用いて、Al2O3/S−GaAs(001)ヘテロ構造の成長を行った。異なるチャンバは、共通の移送ユニットと連結されていた。チャンバおよび移送ユニットは、10−11torrの基礎圧力でUHV下に維持されていた。基礎(バックグラウンド)圧力とは、何れかのガスを供給する以前での処理チャンバ内の圧力である。
Claims (18)
- 誘電体材料とIII−V化合物との間にパッシベーション界面を製造する方法であって、
(a)第1のIII−V化合物を含む露出領域を含む基板を用意するステップと、
(b)その上に、第2のIII−V化合物を含む少なくとも1つの中間層を形成するステップと、
(c)その後、超高真空中で基板に熱処理を施し、第1温度(T1)に到達する際、第2のIII−V化合物の表面再構成が生じて、III族元素リッチの表面を形成するようにしたステップと、
(d)III族元素リッチ表面を含む基板を第2温度(T2)にして、III族元素リッチ表面をカルコゲナイドハイドライドガスを含む環境に曝して、カルコゲナイド・パッシベーション表面を形成するステップと、
(e)カルコゲナイド・パッシベーション表面の上に誘電体層を形成し、誘電体層と第2のIII−V化合物との間にパッシベーション界面を形成するステップと、を含む方法。 - ステップ(b)は、超高真空下で実施し、
ステップ(b)〜ステップ(e)において真空破壊を行わないようにした請求項1記載の方法。 - 第1のIII−V化合物または第2のIII−V化合物のいずれかは、Asを含むIII−V化合物およびこれらの任意の組合せまたは混合物からなるグループから選択され、好ましくは、GaAs,InGaAs,InAs,InAlAs,AlGaAs,GaAsSb,InAlAsSb,InAlAsP,InGaAsPおよびこれらの任意の組合せまたは混合物からなるグループから選択され、より好ましくは、GaAs,InGaAs,InAsおよびこれらの任意の組合せまたは混合物からなるグループから選択され、さらにより好ましくは、第1のIII−V化合物または第2のIII−V化合物のいずれかは、GaAsを含むように選択される、請求項1または2記載の方法。
- 第1のIII−V化合物および第2のIII−V化合物は、同じ化学組成を有する請求項1〜3のいずれかに記載の方法。
- 第1温度(T1)は、400℃〜600℃である請求項1〜4のいずれかに記載の方法。
- 第2温度(T2)は、15℃〜400℃である請求項1〜5のいずれかに記載の方法。
- ステップ(c)で得られるIII族元素リッチ表面は、[110]アジマスに沿った(×4)対称性を持つ表面再構成を示す請求項1〜6のいずれかに記載の方法。
- ステップ(d)で得られるカルコゲナイド・パッシベーション表面は、(2×1)対称性を示す請求項1〜7のいずれかに記載の方法。。
- 第2のIII−V化合物は、GaAs、好ましくはGaAs(001)を含み、
第1温度(T1)は、580℃〜600℃、好ましくは580℃〜595℃、より好ましくは585℃〜595℃、さらにより好ましくは585℃〜590℃であり、
第2温度(T2)は、350℃〜400℃、好ましくは350℃〜380℃、より好ましくは360℃〜380℃である、請求項1〜8のいずれかに記載の方法。 - III族元素リッチ表面をカルコゲナイドハイドライドを含む環境に曝すステップは、プラズマ支援されており、第2温度(T2)は、室温である、請求項1〜9のいずれかに記載の方法。
- カルコゲナイドハイドライドガスは、H2S,H2Se,H2Teおよびこれらの任意の組合せまたは混合物からなるグループから選択され、より好ましくは、カルコゲナイドハイドライドは、硫化水素(H2S)を含む、請求項1〜10のいずれかに記載の方法。
- 誘電体層は、Al2O3,HfO2,DyScOおよびこれらの任意の組合せまたは混合物からなるグループから好ましく選択される高誘電率(high-κ)誘電体を含み、より好ましくは、誘電体層は、Al2O3を含むように選択される、請求項1〜11のいずれかに記載の方法。
- ステップ(b)は、
・露出領域を覆い、これと接触する第1中間層を形成するステップと、
・第1中間層を覆い、これと接触する第2中間層を形成するステップと、
・第2中間層を覆い、これと接触する第3中間層を形成するステップと、
・第3中間層を覆い、これと接触する第4中間層を形成するステップとを含み、
第1中間層および第3中間層は、広いバンドギャップを有するように選択された第3のIII−V化合物を含み、第2中間層および第4中間層は、狭いバンドギャップを有するように選択された第2のIII−V化合物を含む、請求項1〜12のいずれかに記載の方法。 - 誘電体層を形成するステップの後、堆積後アニールを実施することをさらに含む、請求項1〜13のいずれかに記載の方法。
- 堆積後アニールは、不活性環境で実施される、請求項14記載の方法。
- 誘電体材料とIII−V化合物との間にパッシベーション界面を有する電子デバイスであって、
・第1のIII−V化合物を含む露出領域を含む基板と、
・その上に位置し、第2のIII−V化合物を含む少なくとも1つの中間層と、
・第2のIII−V化合物を含む少なくとも1つの中間層を覆う誘電体層と、
・第2のIII−V化合物と誘電体との界面に位置し、本質的にカルコゲナイド原子−III族元素原子結合から成るカルコゲナイド・パッシベーション層と、を備えるデバイス。 - 少なくとも1つの中間層は、
・露出領域を覆い、これと接触する第1中間層と、
・第1中間層を覆い、これと接触する第2中間層と、
・第2中間層を覆い、これと接触する第3中間層と、
・第3中間層を覆い、これと接触する第4中間層とを備え、
第1中間層および第3中間層は、広いバンドギャップを有するように選択された第3のIII−V化合物を含み、第2中間層および第4中間層は、狭いバンドギャップを有するように選択された第2のIII−V化合物を含む、請求項16記載のデバイス。 - 電子デバイス、好ましくは、MOSFETデバイスまたはHEMTデバイスの製造のために、請求項1〜15のいずれかに記載の方法の使用。
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Also Published As
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US20110089469A1 (en) | 2011-04-21 |
EP2306497A1 (en) | 2011-04-06 |
US8872238B2 (en) | 2014-10-28 |
US8314017B2 (en) | 2012-11-20 |
US20130043508A1 (en) | 2013-02-21 |
EP2306497B1 (en) | 2012-06-06 |
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