JP2010532089A - 光電構成素子の製造方法および光電構成素子 - Google Patents
光電構成素子の製造方法および光電構成素子 Download PDFInfo
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- JP2010532089A JP2010532089A JP2010513638A JP2010513638A JP2010532089A JP 2010532089 A JP2010532089 A JP 2010532089A JP 2010513638 A JP2010513638 A JP 2010513638A JP 2010513638 A JP2010513638 A JP 2010513638A JP 2010532089 A JP2010532089 A JP 2010532089A
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Abstract
Description
Claims (15)
- 複数の光電構成素子(1)を製造する方法において、
a) それぞれ一つの半導体層列を備える複数の半導体本体(2)を設け、
b) 構成素子担体結合体(3)に複数の接続面(35)を設け、
c) 前記半導体本体(2)を構成素子担体結合体(30)に対して位置決めし、
d) 前記構成素子担体結合体(30)の接続面(35)を、該接続面に配属された半導体本体(2)と導電接続し、該半導体本体(2)を該構成素子担体結合体(30)に取付け固定し、
e) 多数の光電構成素子(2)を完成し、各光電構成素子(1)に対して一つの構成素子担体(3)が前記構成素子担体結合体(30)から形成される、ことを特徴とする製造方法。 - 請求項1記載の製造方法であって、
・前記半導体本体(2)を前記ステップa)で補助担体(4)に配置し、該補助担体(4)を前記ステップ(c)で前記構成素子担体結合体に対して、前記半導体本体(2)を前記構成素子担体結合体(30)の方に向くように位置決めし、
・前記ステップe)で前記補助担体(4)の上に、前記ステップd)で構成素子担体結合体(30)の上に並置して取付け固定された2つの半導体本体(2)の間に別の半導体本体(2)を配置する製造方法。 - 請求項1または2記載の製造方法であって、
半導体本体(2)は、該半導体本体(2)の半導体層列用の成長基板体(20)の上にそれぞれ形成されており、該成長基板体(20)は前記ステップd)の後に完全にまたは部分的に除去される製造方法。 - 請求項1から3までのいずれか一項記載の製造方法であって、
前記ステップb)で構成素子担体結合体(30)の上に複数の取付け領域(31)を形成し、該取付け領域は半導体本体(2)を取付け固定するために設けられ、
前記ステップc)でそれぞれ取付け領域(31)内に配置され半導体本体(2A)は補助担体(4)から分離され、
取付け領域(31)の外に配置された半導体本体(2B)は補助担体(4)の上に残される製造方法。 - 複数の光電構成素子(1)を製造する方法において、
a) それぞれ一つの半導体層列を備える複数の半導体本体(2)を設け、
このとき該半導体本体(2)を、半導体本体(2)の半導体層列用の成長基板体(20)の上にそれぞれ形成し、
b) それぞれ少なくとも一つの接続面(35)を有する複数の構成素子担体(3)を設け、
c) 前記半導体本体を前記構成素子担体(3)に対して位置決めし、
d) 前記構成素子担体(3)の接続面(35)を、該接続面に配属された半導体本体(2)と導電接続し、該半導体本体(2)を該構成素子担体(3)に取付け固定し、
e) 複数の光電構成素子(1)を完成し、このとき成長基板体(20)は半導体本体(2)からそれぞれ完全にまたは部分的にだけ除去される製造方法。 - 請求項5記載の製造方法であって、
前記構成素子担体(3)は前記ステップb)で、構成素子担体結合体(30)に形成される製造方法。 - 請求項5または6記載の製造方法であって、
半導体本体(2)は前記ステップc)で個別に構成素子担体結合体に配置される製造方法。 - 請求項5または6記載の製造方法であって、
・前記半導体本体(2)を前記ステップa)で補助担体(4)に配置し、該補助担体(4)を前記ステップ(c)で前記構成素子担体(3)に対して、前記半導体本体(2)を前記構成素子担体(3)の方に向くように位置決めし、
・前記ステップe)で前記補助担体(4)の上に、前記ステップd)で構成素子担体(3)の上に並置して取付け固定された2つの半導体本体(2)の間に別の半導体本体(2)を配置する製造方法。 - 請求項2または8記載の製造方法であって、
前記補助担体(4)には前記ステップa)で別個の半導体本体(2)が設けられ、該別個の半導体本体は光電特性に関して前もって選択されている製造方法。 - 請求項2、8または9記載の製造方法であって、
半導体本体(2)は前記ステップd)で選択的に補助担体(4)から解離される製造方法。 - 請求項2、8、9または10記載の製造方法であって、
前記補助担体(4)はシートとして構成されている製造方法。 - 請求項11記載の方法であって、
前記シートの一部は、完成した光電構成素子では半導体本体(2)に残っている製造方法。 - 請求項5または請求項5を引用する請求項記載の方法であって、
前記ステップb)で構成素子担体(3)の上にそれぞれ少なくとも一つの取付け領域(31)を形成し、該取付け領域は半導体本体(2)を取付け固定するために設けられ、
前記ステップc)でそれぞれ取付け領域(31)内に配置され半導体本体(2A)は補助担体(4)から分離され、
取付け領域(31)の外に配置された半導体本体(2B)は補助担体(4)の上に残される製造方法。 - 少なくとも2つの接続面(35,36)を備える構成素子担体(32)と、半導体層列を備える半導体本体(2)とを有する光電構成素子(1)であって、
前記半導体本体(2)の上には少なくとも2つの接触面(25,26)が形成されており、
該接触面はそれぞれ接続面(35,36)と導電接続しており、
半導体本体(2)と構成素子担体(3)との間の中間空間(5)は少なくとも部分的に充填材料(50)によって満たされている光電構成素子。 - 請求項14記載の光電構成素子であって、
前記接触面(25,26)は、活性領域(21)の同じ側に形成されている光電構成素子。
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DE102007043877.1 | 2007-09-14 | ||
PCT/DE2008/000776 WO2009003435A1 (de) | 2007-06-29 | 2008-05-07 | Verfahren zur herstellung von optoelektronischen bauelementen und optoelektronisches bauelement |
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KR20100045980A (ko) | 2010-05-04 |
US20100171215A1 (en) | 2010-07-08 |
WO2009003435A1 (de) | 2009-01-08 |
JP5334966B2 (ja) | 2013-11-06 |
EP2162927B1 (de) | 2018-10-24 |
EP2162927A1 (de) | 2010-03-17 |
TW200905930A (en) | 2009-02-01 |
CN101681964B (zh) | 2013-05-08 |
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