CN101681964A - 用于制造光电子器件的方法以及光电子器件 - Google Patents

用于制造光电子器件的方法以及光电子器件 Download PDF

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Publication number
CN101681964A
CN101681964A CN200880018019A CN200880018019A CN101681964A CN 101681964 A CN101681964 A CN 101681964A CN 200880018019 A CN200880018019 A CN 200880018019A CN 200880018019 A CN200880018019 A CN 200880018019A CN 101681964 A CN101681964 A CN 101681964A
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semiconductor body
device supporting
semiconductor
composite construction
auxiliary bearing
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CN101681964B (zh
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赫尔穆特·菲舍尔
迪特尔·艾斯勒
亚历山大·海因德尔
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Ams Osram International GmbH
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Osram Opto Semiconductors GmbH
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Abstract

本发明提出了一种用于制造光电子器件(1)的方法,其中提供多个分别带有半导体层序列的半导体本体(2)。此外提供带有多个连接面(35)的器件支承复合结构(30)。将半导体本体(2)相对于器件支承复合结构(30)定位。在连接面(35)与关联的半导体本体(2)之间建立导电连接,并且将该半导体本体固定在器件支承复合结构(30)上。光电子器件(2)被制成,其中针对每个光电子器件(1)都构建有器件支承复合结构(30)构成的器件支承体(3),半导体本体(2)固定在该器件支承复合结构上。此外提出了一种光电子器件。

Description

用于制造光电子器件的方法以及光电子器件
本申请涉及一种用于制造多个光电子器件的方法以及一种光电子器件。
光电子器件通常在多个单独步骤中制造。在此,例如通常将设计用于产生辐射的半导体芯片插入壳体中。这例如可以借助所谓的拾放方法(Pick-and-Place-Verfahren)来进行,其中半导体芯片单个地放置在壳体中。光电子器件的这种制造方式比较费事并且成本高昂。
本发明的任务是,提出一种方法,借助该方法可以简化地、优选以批量制造方法制造多个光电子器件。此外,还要说明一种光电子器件,其可以简化地制造。
这些任务通过独立权利要求来解决。有利的扩展方案和改进方案是从属权利要求的主题。
根据一个实施形式,在用于制造多个光电子器件的方法中,提供了多个分别带有半导体层序列的半导体本体。此外,提供了带有多个连接面的器件支承复合结构。半导体本体相对于器件支承复合结构定位。在连接面和关联的半导体本体之间分别建立导电的连接,并且这些半导体本体被固定在器件支承复合结构上。制成多个光电子器件,其中针对每个光电子器件都构建有由器件支承复合结构构成的器件支承体。
于是,在器件支承复合结构的针对器件支承体而设计的区域上已经固定了关联的至少一个半导体本体并且与相应的连接面导电连接之后,由器件支承复合结构构建器件支承体。可以省去用于在分离的器件支承体中安装半导体本体的费事的拾放方法。于是简化了光电子器件的制造。
在一个扩展变形方案中,在辅助支承体上提供半导体本体。半导体本体于是设置在辅助支承体上。该辅助支承体可以相对于器件支承复合结构来定位,使得半导体本体朝向器件支承复合结构。通过这种方式,可以特别是同时将多个半导体本体相对于器件支承复合结构来定位。由此简化了制造。
在一个可替选的扩展变形方案中,半导体本体单独地、譬如以拾放方法来设置在器件支承复合结构上。各个半导体本体可以彼此无关地定位。
在一个优选的扩展方案中,半导体本体分别构建在用于半导体本体的半导体层序列的生长衬底本体上。生长衬底本体可以特别是在建立连接面与半导体本体的导电连接之后被完全去除或者部分去除,譬如整面地或者局部地薄化或者局部去除。生长衬底本体于是可以在制造光电子器件期间特别是用于半导体本体的机械稳定。于是可以省去半导体本体的附加的机械稳定。而在制成的光电子器件中为此不再需要生长衬底本体。更确切地说,生长衬底本体可以在制造期间被完全去除。于是,可以与其光学特性无关地选择生长衬底本体。
根据另一实施形式,在用于制造多个光电子器件的方法中,提供了分别带有半导体层序列的多个半导体本体,其中半导体本体分别构建在用于半导体层序列的生长衬底本体上。此外提供了多个器件支承体,它们分别具有至少一个连接面。半导体本体被相对于器件支承体来定位。器件支承体的连接面与同连接面关联的半导体本体的导电连接被建立,并且该半导体本体被固定在器件支承体上。制成了多个光电子器件,其中在建立导电连接以及将半导体本体固定在器件支承体上之后,将生长衬底本体从相应的半导体本体完全或者部分地去除,譬如整面地或者局部地薄化或者局部地去除。
于是,在半导体本体已经固定在关联的器件支承体上之后进行生长衬底本体的去除。在将半导体本体固定在器件支承体上之前,于是生长衬底本体可以用于将关联的半导体本体机械稳定。在制成的光电子器件中,生长衬底本体不再存在或者仅仅部分地存在。在完全去除生长衬底本体的情况下,光电子器件的光电子特性与生长衬底本体无关。用于半导体本体的半导体层序列的生长衬底本体由此可以独立于其光学特性地选择。特别地,生长衬底本体可以构建为对于半导体本体中产生的辐射是不可透射的。
在另一实施形式的一个扩展变形方案中,在辅助支承体上提供半导体本体。半导体本体于是设置在辅助支承体上。该辅助支承体可以相对于器件支承体定位,使得半导体本体朝向器件支承体。通过这种方式,多个半导体本体可以特别是同时地相对于器件支承体定位。由此简化了制造。
在另一实施形式的一个可替选的扩展变形方案中,半导体本体单独地、譬如以拾放方法来设置在器件支承体上。单个的半导体本体可以彼此独立地定位。
在该方法的另一实施形式的一个优选的扩展方案中,在器件支承复合结构中提供器件支承体。器件支承体可以由器件支承复合结构来构建。特别优选地,在完全或者部分地去除生长衬底本体之后由器件支承复合结构来构建器件支承体。
光电子器件可以通过将器件支承复合结构划分为器件支承体来制成。于是可以省去在将器件支承复合结构分割后针对单个的器件支承体来进行的费事的制造步骤。于是简化了光电子器件的制造。
在将半导体本体固定在器件支承体上的情况下,辅助支承体和器件支承复合结构优选平行或者基本上彼此平行。半导体本体于是可以平面地提供在器件支承复合结构上。
此外优选的是,在已经将生长衬底本体从相应的半导体本体去除之后,由器件支承复合结构来构建器件支承体。于是还可以在复合结构中进行生长衬底本体的去除。
半导体本体优选分别具有至少一个有源区,其设计用于产生辐射。所产生的辐射可以是非相干的、部分相干的或者相干的。特别地,半导体本体可以实施为发光二极管半导体本体,譬如实施为LED半导体本体、RCLED(谐振腔发光二极管)或者实施为激光二极管半导体本体。
在一个优选的扩展方案中,在至少一个半导体本体上构建有接触面,该接触面与器件支承体上的关联的连接面导电相连。此外优选的是,在半导体本体上构建有另一接触面,该接触面与器件支承体上的另一连接面相连。于是,半导体本体可以具有两个接触面,它们分别与连接面相连。在光电子器件的工作中,可以通过在连接面之间施加外部电压来通过接触面将电流注入到半导体本体的设计用于产生辐射的有源区中。
在一个优选的改进方案中,接触面和另外的接触面构建在有源区的相同侧上。半导体本体由此可以从一侧电接触。特别地,接触面和另外的接触面可以形成在共同平面的背离半导体本体的侧上。换言之,接触面的背离半导体本体的边界面可以在一个平面内延伸。由此在很大程度上简化了半导体本体的电接触。
接触面优选包含金属或者金属合金。
在一个优选的扩展方案中,器件支承体分别选自电路板(包括金属芯电路板)、陶瓷体(包括连接面和引线框架)。特别地,器件支承体可以刚性或者柔性地构建。
在制造光电子器件时,例如可以借助机械分割来从器件支承复合结构产生器件支承体。特别地,借助锯割、切割、冲压或者折断来从器件支承复合结构构建器件支承体。
可替选地,为了从器件支承复合结构构建器件支承体,也可以使用电磁辐射、特别是相干辐射,譬如激光辐射。
在另一优选的扩展方案中,辅助支承体设置有独立的半导体本体,这些半导体本体特别优选地关于其功能性以及很大程度上关于其光电子特性(譬如亮度、发射特性或者色度坐标)进行预先选择。特别地,光电子特性可以已经在将半导体本体安装在相应的器件支承体上之前关于这些特性进行了测量。通过这种方式,可以保证器件支承体分别仅仅装配有对应于预先给定的光电子特性的半导体本体。
这些特性的测量可以已在将半导体本体放置在辅助支承体上之前进行。可替选地或者补充地,测量可以在辅助支承体上进行。并不满足预先给定的光电子特性的半导体本体于是可以从辅助支承体去除并且此外优选通过另外的半导体本体来替代。
在一个优选的改进方案中,在将半导体本体固定在器件支承体上之后,将半导体本体选择性地从辅助支承体剥离。特别地,半导体本体可以借助对辅助支承体的选择性曝光、譬如借助相干的辐射譬如激光辐射来从辅助支承体剥离。
设计用于固定在器件支承体或者器件支承复合结构上的半导体本体优选分别关联有器件支承体或者器件支承复合结构上的安装区域。
特别优选的是,如下的半导体本体与辅助支承体分离:这些半导体本体在将辅助支承体定位在安装区域内的情况下设置在器件支承体或者器件支承复合结构上。相对于器件支承体或者相对于器件支承复合结构设置在安装区域之外的半导体本体可以保留在辅助支承体上并且例如在随后的制造步骤中固定在另外的器件支承体或者器件支承复合结构上。特别地,所有安装在辅助支承体上的半导体本体可以安装在器件支承体或者器件支承复合结构上。
此外,在辅助支承体上在两个半导体本体之间可以设置至少一个另外的半导体本体,其中所述两个半导体本体在将半导体本体安装在器件支承体或者器件支承复合结构上时并排固定。在辅助支承体上设置在一个面上的半导体本体的数目于是可以超过在相同大小的面上在器件支承体或者器件支承复合结构上的安装区域的数目。于是,在辅助支承体上的半导体本体的排列密度可以高于器件支承复合结构或者器件支承体上的安装区域的排列密度。
半导体本体例如可以以棋盘状的图案交替地保留在辅助支承体上或者安装在器件支承体或者器件支承复合结构上。
辅助支承体可以刚性地或者机械上柔性地实施。柔性的辅助支承体可以在需要的情况下在背离半导体本体的侧上设置在另一支承体上,该另一支承体使辅助支承体机械稳定。
在一个优选的改进方案中,辅助支承体实施为薄膜。如下的薄膜是特别适合的:该薄膜在半导体本体上的附着特性可以被有针对性地影响、特别是减小。这例如可以借助电磁辐射、特别是相干辐射譬如激光辐射来进行。通过这种方式,可以以简化的方式选择性地将半导体本体从辅助支承体去除。
在将半导体本体固定在器件支承体上之后,辅助支承体、特别是实施为薄膜的辅助支承体可以被完全地从半导体本体去除。
可替选地,辅助支承体的一部分、特别是实施为薄膜的辅助支承体的一部分也可以在制成的光电子器件中保留在半导体本体上。仅仅由于制造而残留在半导体本体上的痕迹譬如连接剂的残留物在此不能理解为辅助支承体的部分。例如,可以借助薄膜来形成半导体本体的包封或者半导体本体的壳体。
在一个优选的扩展方案中,生长衬底本体可以借助相干辐射譬如激光辐射来从相应的半导体本体去除。可替选地,生长衬底本体可以借助化学工艺譬如湿化学或者干化学刻蚀、和/或借助机械工艺譬如磨削、研磨或抛光来从相应的半导体本体去除。
在一个优选的改进方案中,在将相应的半导体本体固定在器件支承体上之后调节至少一个光电子器件的光电子特性。
此外优选的是,可以将辐射转换材料构建在相应的半导体本体上。借助该辐射转换材料,可以调节光电子器件的光谱发射特征。通过辐射转换材料,可以将在半导体本体的有源区中产生的辐射的一部分转换为另一波长的辐射。于是,可以产生混色光,特别是对于人眼表现为白色的光。
特别优选的是,辐射转换材料关于其量和/或其组分选择性地与相应的半导体本体匹配。为此,半导体本体可以已经在固定在辅助支承体上之前或者之后特别是关于功能性和光电子特性方面被表征。可替选地或者补充地,可以在将半导体本体固定在器件支承体上或者固定在器件支承复合结构上之后进行光电子特性的测量,譬如亮度和/或色度坐标的测量。
特别地,可以通过与相应的半导体本体匹配的辐射转换材料的剂量来将光电子器件的色度坐标与预先给定的发射特征匹配。
在一个优选的扩展方案中,设置有至少一个带有光学元件的半导体本体。这优选还在从器件支承复合结构构建器件支承体之前进行。
光学元件可以被预制,并且例如借助机械连接或者粘合连接来固定在器件支承体或者器件支承复合结构上。
可替选地,光学元件可以构建在半导体本体上。在这种情况中,光学元件可以借助造型材料来形成,该造型材料将半导体本体至少局部地变形,并且根据预先给定的发射特性来合适地构建。造型材料例如可以包含塑料或者硅树脂。
光学元件例如可以实施为透镜或者光导体。
在另一优选的扩展方案中,半导体本体设置有结构。该结构特别是可以设计用于提高半导体本体的耦合输出效率。该结构优选构建在半导体本体的背离器件支承体的侧上。例如,半导体本体或者与半导体本体邻接的层可以设置有粗化部。可替选地或者补充地,可以在半导体本体上设置和/或构建光子晶体。
该结构例如可以机械地、譬如借助磨光、研磨或者抛光来制造,或者以化学方式、譬如借助湿化学或者干化学刻蚀来制造。
在另一优选的扩展方案中,在器件支承体或者器件支承复合结构以及关联的半导体本体之间引入填充材料。在将半导体本体固定在器件支承体或者器件支承复合结构上的情况下在半导体本体和器件支承体或器件支承复合结构之间会形成的间隙可以至少局部地被填充。间隙特别是可以在横向方向上、即沿着器件支承体或者器件支承复合结构的主延伸方向地构建在连接面之间和/或在接触面之间。填充材料特别是在剥离相应的生长衬底本体时可以使半导体本体机械地稳定。
填充材料优选实施为使得毛细效应有利于将填充材料引入到间隙中。为此,填充材料优选具有低的粘度。
此外,填充材料合乎目的地电绝缘地实施。通过这种方式,可以避免两个相邻的连接面之间的电短路。
填充材料优选包含有机材料譬如树脂,特别是反应树脂。例如,填充材料可以包含环氧树脂。此外,填充材料可以实施为粘合剂。
特别优选的是,在剥离相应的生长衬底本体之前引入填充材料。通过这种方式,填充材料可以特别是在剥离生长衬底本体的情况下机械地稳定半导体本体。
此外优选的是,填充材料在能够流动的状态中引入间隙中并且随后硬化。硬化特别是可以由热引起或者由电磁辐射、特别是紫外辐射引起地实现。
在一个优选的扩展方案中,在其中执行所描述的制造步骤的装置中制造光电子器件。制造步骤在此可以完全地或者部分地自动化地、特别是相继地执行。由此简化了光电子器件的制造。
根据一个实施形式,光电子器件具有带有至少两个连接面的器件支承体以及带有半导体层序列的半导体本体。半导体本体的半导体层序列优选包括设计用于产生辐射的有源区。在该半导体本体上构建有至少两个接触面,它们分别与连接面导电相连。在半导体本体和器件支承体之间的间隙至少部分地以填充材料来填充。
填充材料特别是用于半导体本体的机械稳定。于是可以借助填充材料在制造光电子器件期间以及在光电子器件的工作中使半导体本体机械稳定。特别地,由此简化了光电子器件的制造,譬如半导体本体的生长衬底本体的剥离。
在一个优选的扩展方案中,间隙在横向方向上、即沿着器件支承体的主延伸方向由连接面和/或接触面来形成边界。特别地,间隙可以在横向方向上在连接面之间和/或在接触面之间延伸。间隙可以完全或者部分地用填充材料填充。
接触面优选构建在有源区的同一侧上。由此,简化了至器件支承体的连接面的导电连接的制造。
在一个优选的扩展方案中,半导体本体、特别是有源区包含III-V半导体材料。借助III-V半导体材料可以在产生辐射时实现高的内部量子效率。
在上面描述的方法特别适于制造光电子器件。结合所描述的方法阐述的特征因此也适用于光电子器件,反之亦然。
其他的特征、有利的扩展方案和合乎目的性由以下结合附图对实施例的描述而得到。
其中:
图1A至1H在示意性截面图中借助中间步骤示出了用于制造光电子器件的方法的第一实施例,
图2A至2G在示意性截面图中借助中间步骤示出了用于制造光电子器件的方法的第二实施例,
图3A至3G在示意性截面图中借助中间步骤示出了用于制造光电子器件的方法的第三实施例,
图4在示意性截面图中示出了半导体本体的一个实施例,
图5在示意性截面图中示出了光电子器件的一个实施例。
在附图中,相同的、类似的以及作用相同的元件设置有相同的附图标记。
附图分别是示意性的视图,并且因此不一定是合乎比例的。更确切地说,比较小的元件以及特别是层厚度可以为了清楚起见而被夸大地示出。
在图1A至1H中在示意性截面图中借助中间步骤示出了用于制造光电子器件的方法的第一实施例。
如在图1A中所示,在辅助支承体4上提供分别带有半导体层序列的多个半导体本体2。半导体层序列形成了半导体本体2。半导体本体2分别设置在生长衬底本体20上。半导体本体的半导体层序列的制造优选以外延方法,譬如MOVPE或者MBE来进行。半导体本体分别设置在生长衬底本体20的背离辅助支承体4的侧上。
在半导体本体2的背离相应生长衬底本体20的侧上分别构建有接触面25和另外的接触面26。接触面25和另外的接触面26于是设置在半导体本体的同一侧上。
接触面25、26合乎目的地导电地实施。优选的是,接触面包含金属,譬如Au、Sn、Ni、Ti、Al或者Pt,或者带有所述金属至少之一的金属合金,譬如AuGe或者AuSn。接触面也可以多层地实施。
在图1A中,带有生长衬底本体20和接触面25、26的半导体本体2为了更清楚而被强烈简化地示出。例如,半导体本体可以分别具有设计用于产生辐射的有源区。这在图1A中并未明确示出。半导体本体例如可以设计为LED半导体本体、RCLED半导体本体或者激光二极管半导体本体。相应地,在工作中发射的辐射可以是非相干的、部分相干的或者相干的。
特别地,半导体本体2和/或生长衬底本体20可以如结合图4所描述的那样来实施或者具有结合图4所描述的特征的至少之一。
在一个扩展变形方案中,辅助支承体4实施为刚性支承体。
在一个可替选的扩展变形方案中,辅助支承体实施为薄膜。辅助支承体于是可以是机械上柔性的。必要时,薄膜可以通过另外的支承体、特别是在背离半导体本体2的侧上机械地稳定。
在图1B中示出了器件支承复合结构30,在其上设置有安装区域31。安装区域分别设计用于固定半导体本体。在安装区域中分别在器件支承复合结构上构建有连接面35和另外的连接面36。
在所示的实施例中,仅仅示例性地示出了器件支承复合结构30,在制造光电子器件时从中得到两个器件支承体,其中由器件支承复合结构区域301分别构建器件支承体。在每个器件支承复合结构区域301上分别设置有两个半导体本体。当然,在器件支承复合结构区域301上也可以设置数目不同于两个的半导体本体2,例如一个半导体本体或者三个或者更多个半导体本体。此外,也可以由器件支承复合结构得到多于两个的器件支承体。
器件支承体3可以刚性地或者柔性地实施。例如,电路板、譬如PCB(印刷电路板)电路板是适合的。也可以使用金属芯电路板(MCPCB,金属芯印刷电路板)。这种电路板的特征尤其在于高的导热能力。在光电子器件的工作中在半导体本体中产生的热于是可以特别有效地散发。
可替选地,器件支承体3也可以含有陶瓷或者例如实施为陶瓷体,在其上可以分别设置有导电的连接面。此外,器件支承体3也可以实施为优选金属的引线框架。在这种情况中,器件支承复合结构30例如可以是金属片,从其中构建引线框架。
辅助支承体4被相对于器件支承复合结构30定位,使得半导体本体2朝向器件支承复合结构30(图1C)。在此,辅助支承体4可以平面地设置在器件支承复合结构30上。
定位合乎目的地进行,使得在俯视图中连接面35、36与关联的半导体本体2A的关联的接触面25、26交迭,并且优选彼此机械接触。在连接面35和接触面25之间以及在另外的连接面36和另外的接触面26之间建立导电连接。这例如可以借助焊接来进行。可替选地或者补充地,也可以使用导电的粘合剂。半导体本体2A于是可以与器件支承复合结构30机械稳定地连接。
半导体本体2于是可以在建立与连接面35、36的导电连接时也机械稳定地固定在器件支承复合结构301上。可替选地或者补充地,半导体本体2也可以独立于导电连接例如借助粘合剂固定在器件支承复合结构上。
在半导体本体2A之间在辅助支承体4上示例性地分别设置有另外的半导体本体2B。该半导体本体2B相对于器件支承复合结构设置为使得它们位于安装区域31之外。这些半导体本体31在所描述的方法步骤中并不与器件支承复合结构30机械连接,并且保留在辅助支承体4上。例如,为了安装而设计的半导体本体2A和保留在辅助支承体上的半导体本体2B可以在辅助支承体上形成棋盘式的图案。与此不同,其他图案也可以是合乎目的的。合乎目的的是,该图案与器件支承复合结构上的安装区域31的布置相匹配。特别地,该图案可以模仿安装区域的布置。
在辅助支承体4上可以在一个面上构建有与器件支承复合结构30在相同大小的面上提供的安装区域相比更多的半导体本体2。相应地,可以在辅助支承体4上设置有具有比器件支承复合结构上的安装区域更高的排列密度的半导体本体2。
为了装备器件支承复合结构30的器件支承复合结构区域301,合乎目的的是,分别将位于器件支承复合结构上的安装区域31内的半导体本体2A与器件支承复合结构30机械稳定地连接,其中特别是它们的接触面25、26可以与器件支承复合结构30上的连接面交迭。换言之,可以从具有较大的排列密度的辅助支承体4上提供的半导体本体2中选择用于安装到器件支承复合结构30上的半导体本体,这些半导体本体相对于安装区域31适当地定位。
带有关联的生长衬底本体20的半导体本体2A随后被选择性地从辅助支承体4去除(图1D)。而半导体本体2B与辅助支承体4保持机械连接并且可以与辅助支承体4一同从器件支承复合结构30去除。
从辅助支承体4选择性地剥离半导体本体2A例如可以通过局部地改变辅助支承体4的附着特性来实现。特别地,其附着特性可以借助曝光而局部减小的辅助支承体是适合的。为此,例如电磁辐射、特别是相干辐射譬如激光辐射是合适的,该辐射有针对性地入射到辅助支承体上的要剥离的半导体本体2A的区域中的辅助支承体上。辅助支承体4例如可以是薄膜,其至半导体本体或者关联的生长衬底本体的附着特性可以借助曝光来减小。
连接面35和另外的连接面36合乎目的地彼此间隔。在将半导体本体2固定在器件支承体上时,在半导体本体和器件支承复合结构30之间可以分别形成间隙5(图1C)。这些间隙5可以借助填充材料50至少局部地填充。填充材料优选实施为使得毛细效应有助于填充材料流入间隙5中。
填充材料合乎目的地在能够流动的状态中引入间隙中。优选的是,填充材料具有低的粘度。由此使得流入小的间隙变得容易。随后,填充材料可以在需要时被硬化。硬化例如可以由热引起或者借助电磁辐射、特别是紫外辐射来引起。此外,填充材料优选电绝缘地实施。
填充材料50优选包含有机材料譬如树脂,特别是反应树脂。例如,填充材料可以包含环氧树脂。此外,填充材料可以实施为粘合剂。
如在图1E中所示的那样,生长衬底本体20可以被从相应的半导体本体2去除。填充材料50在此用于半导体本体2的机械稳定。
生长衬底本体20的去除可以完全地或者部分地进行。优选的是使用激光剥离方法。可替选地,生长衬底本体也可以借助化学工艺譬如湿化学或者干化学刻蚀和/或借助机械工艺譬如磨削、研磨或者抛光来薄化或者完全去除。从半导体本体剥离的生长衬底本体20的材料例如可以被抽吸。
在制造光电子器件期间,生长衬底本体20用于相应半导体本体的机械稳定。借助附加的支承体来进行的进一步的稳定在此是不必要的。在所描述的方法中,在半导体本体2已经固定在器件支承复合结构上之后,生长衬底本体20被去除,其中器件支承体来自该器件支承复合结构。
而在制成的光电子器件1中生长衬底本体不再必须存在(图1H)。由此,可以很大程度上与光电子特性无关地选择用于半导体本体2的半导体层序列的生长衬底。
此外,在制成的光电子器件1中的半导体本体2可以通过器件支承体3来机械稳定。可以省去譬如在半导体本体的背离器件支承体的侧上的附加的支承体。由此,可以减小光电子器件1的结构高度。
如在图1F中所示,半导体本体2可以设置有结构29,通过该结构提高了从半导体本体的耦合输出效率。于是可以提高在光电子器件的工作中在相应的有源区中产生并且从半导体本体出射的辐射的部分。
半导体本体2的结构化或者设置在半导体本体上的层的结构化例如可以以机械方式譬如借助磨削、研磨、抛光或者以化学方式譬如借助湿化学或者干化学刻蚀来进行。该结构在此可以不规则或者规则地实施。由于全反射导致辐射在半导体本体的边界面上的多次反射可以借助该结构来减小。此外,该结构可以根据光子晶体来成形。
为了影响要制造的光电子器件的光谱特征,可以在半导体本体2上构建辐射转换材料,譬如发光转换器或者磷光体。辐射转换材料例如可以构建在用于半导体本体2的包封物6中。在半导体本体2中产生的辐射可以至少部分地被辐射转换材料转换为其他波长的辐射。通过这种方式,可以由光电子器件发射混色光,优选对于人眼显现为白色的光。
与此不同,辐射转换材料也可以构建在不同于包封物6的独立的层中,该层可以在背离器件支承复合结构30的侧上施加到半导体本体上。包封物例如可以包含树脂,特别是反应树脂或者硅树脂。
特别地,在施加辐射转换材料之前可以对从半导体本体发射的辐射的光谱特征进行测量,并且辐射转换材料的量和/或组分可以基于测量结果来调节。通过这种方式,例如可以特别精确地调节光电子器件在CIE图中的色度坐标。
此外,辐射转换材料的量和/或组分可以选择性地与相应的半导体本体匹配。该量和/或组分于是可以因半导体本体而异而在很大程度上彼此独立地调节。
辐射转换材料的施加例如可以针对每个半导体本体分别借助微剂量器(Mikrodosierer)来实现。
相应地,在需要时也可以特别是根据对相应半导体本体发射的辐射功率事先进行的测量来调节光电子器件1的亮度,并且于是与预先给定的值匹配。为此,在半导体本体上例如可以施加层,该层有针对性地吸收半导体本体发射的辐射的一部分。
此外,包封物6可以根据光学元件7来成形。在这种情况中,光学元件于是构建在半导体本体2上。与此不同,光学元件也可以被预制并且固定在器件上。特别地,光学元件可以实施为透镜或者光导体。合乎目的地,光学元件由如下材料制成:该材料对于半导体本体中产生的辐射是透明的或者至少是半透明的。例如,光学元件7可以基于塑料、硅树脂或者玻璃,或者由这种材料构成。
由器件支承复合结构30构建器件支承体3。这例如可以借助机械分离譬如锯割、切割、分裂、冲压或者折断来进行,或者借助相干辐射譬如激光辐射来进行。在图1H中示出了两个制成的光电子器件1。
在所描述的方法中,在由器件支承复合结构30构建器件支承体3之前于是可以执行多个制造步骤。由此简化了光电子器件1的制造。特别地,分别带有生长衬底本体20的半导体本体2可以安装在器件支承复合结构30中。生长衬底本体20随后可以被去除,使得光电子器件1可以没有生长衬底本体。
不同于所描述的方法,替代结合图1C和1D所描述的方法步骤,半导体本体2也可以单独地定位在器件支承复合结构上并且随后固定。该定位例如可以在拾放方法中进行。另外的方法步骤、特别是结合图1E描述的去除生长衬底本体可以如上所述的那样来进行。相应的生长衬底本体20可以在该变形方案中在安装半导体本体期间用于半导体本体的机械稳定,并且随后还被去除。
所描述的方法步骤优选在用于多个光电子器件的装置中执行。特别地,这些方法步骤可以全自动化地或者至少部分自动化地执行。于是进一步简化了光电子器件的制造。
在图2A至2G中示意性地在截面图中借助中间步骤示出了用于制造多个半导体芯片的方法的第二实施例。该第二实施例基本上对应于结合图1A至1H所描述的第一实施例。与其不同,辅助支承体4的一部分41保留在半导体本体2A上,这些半导体本体固定在器件支承复合结构30上。这在图2D中示出。借助辅助支承体4的这些部分,可以如图2E所示的那样形成用于半导体本体2的包封物6。
借助包封物可以将半导体本体2封装,并且于是保护其免受外部影响。可替选地或者补充地,可以借助辅助支承体的这些部分来分别形成半导体本体2的壳体。例如,辅助支承体可以借助薄膜来形成,该薄膜可以模制到半导体本体2上。该模制例如可以热引发地进行。例如,半导体本体可以与器件支承复合结构30一同加热到薄膜熔点之上的温度。可替选地,薄膜也可以局部地、例如借助相干辐射譬如激光辐射来加热。
此外,不同于第一实施例地将预制的光学元件7固定在器件支承复合结构30上。光学元件示例性地实施为平凸透镜。与此不同,根据要实现的发射特征,光学元件的其他形状也可以是有利的。光学元件7例如可以借助粘合来固定在器件支承体3上。
如结合图1A至1H所描述的那样,在半导体本体上、特别是在包封物6上可以施加辐射转换材料(未明确示出)。
在图3A至3G中借助中间步骤示意性地示出了用于制造多个半导体芯片的方法的第三实施例。第三实施例基本上对应于结合图1A至1H所描述的第一实施例。
不同于第一实施例,如在图3B中所示,可以已经预制地提供器件支承体3。为此,可以将器件支承体设置在安装支承体上(未明确示出)。于是不在器件支承复合结构中提供器件支承体3。器件支承体3与器件支承复合结构区域301对应地示例性地分别具有两个安装区域31。在安装区域中分别在器件支承体3上构建有连接面35和另外的连接面36。器件支承体3也可以分别具有与此不同数目的安装区域,譬如一个安装区域或者多于两个的安装区域。
在图3A以及3C至3G中示出的另外的制造步骤可以如结合图1A以及1C至1G中所描述的那样实施。在此,器件支承体3基本上对应于第一实施例的器件支承复合结构区域301。特别地,与安装区域31关联的半导体本体2固定在相应的器件支承体3上(图3D)。
对应于结合图1A至1H所描述的第一实施例,在半导体本体2和器件支承体3之间在将半导体本体固定在器件支承体上时会形成的间隙50可以被填充。
不同于所示的第三实施例,也可以使用结合图2A至2G所描述的第二实施例中所提及的特征。特别地,可以预制光学元件7。此外,可以分别将辅助支承体4的一部分保留在半导体本体2上。
不同于第一实施例,在图1H中所示的由器件支承复合结构构建器件支承体在根据第三实施例的方法中不是必需的。
不同于所描述的根据第三实施例的方法,替代图3C和3D中所示的方法步骤,也可以将半导体本体2单独地定位在器件支承体上并且随后固定。该定位例如可以在拾放方法中进行。另外的方法步骤、特别是结合图3E所描述的生长衬底本体的去除可以如上所述地进行。相应的生长衬底本体20可以在该变形方案中在安装半导体本体期间用于将半导体本体机械稳定,并且此外随后被去除。
在图4中在示意性截面图中示出了半导体本体2的一个实施例,其对于借助图1A至1H、2A至2G或者3A至3G所描述的方法的实施例是特别适合的。
半导体本体2示例性地实施为发光二极管半导体本体,其设计用于产生非相干辐射。具有有源区21、n导电的半导体层22和p导电的半导体层23的半导体层序列形成半导体本体2。半导体本体2的半导体层序列设置在生长衬底本体20上。生长衬底本体20优选通过由生长衬底譬如晶片分割来得到。在生长衬底上可以优选外延地、譬如借助MOVPE或者MBE来制造半导体层序列,其中由该半导体层序列形成半导体本体。
半导体本体2、特别是有源区21优选包含III-V半导体材料。III-V半导体材料特别适于在紫外光谱范围(InxGayAl1-x-yN)经过可见光谱范围(InxGayAl1-x-yN,特别是针对蓝色至绿色辐射,或者InxGayAl1-x-yP,特别是针对黄色至红色辐射)直到红外光谱范围(InxGayAl1-x-yAs)。在此,分别有0≤x≤1,0≤y≤1并且x+y≤1,特别是有x≠1,y≠1,x≠0和/或y≠0。借助特别是来自所提及的材料系的III-V半导体材料,此外可以在产生辐射时实现有利地高的内部量子效率。
作为生长衬底,可以根据针对半导体本体要沉积的材料例如使用衬底,譬如包含GaAs、Si、SiC、GaN、InP或者GaP的衬底,或者由这种材料构成的衬底。也可以使用蓝宝石衬底。
n导电的半导体层22设置在有源区和生长衬底本体20之间。n导电的半导体层和p导电的半导体层23关于有源区21的布置也可以交换,使得p导电的半导体层可以设置在有源区21和生长衬底本体20之间。
在有源区21的背离生长衬底本体20的侧上构建有接触面25和另外的接触面26。接触面25和另外的接触面26于是设置在有源区的相同的侧上。于是,半导体本体的外部的电接触可以由半导体本体的一侧、特别是从有源区的一侧来进行。
接触面25、26合乎目的地导电地实施。优选的是,接触面包含金属,譬如Au、Sn、Ni、Ti、Al或者Pt,或者带有所述金属的至少之一的金属合金,譬如AuSn或者AuGe。接触面例如可以借助溅射或者气相淀积到半导体本体上来制造。
另外,半导体本体2具有至少一个凹处27,其从半导体本体2的背离生长衬底本体20的侧出发通过有源区21而延伸。
在凹处27中,在凹处的侧面上的半导体本体2设置有隔离层28。此外,隔离层构建在另外的接触面26和半导体本体之间。隔离层例如可以包含氧化物譬如氧化硅、氮化物譬如氮化硅、氮氧化物譬如氮氧化硅。
通过凹处27在隔离层28上建立另外的接触面26与n导电的半导体层22的导电连接。通过在接触面25和另外的接触面26之间施加外部的电压,于是可以有电流流过有源区21,并且在那里通过电子-空穴对的复合而导致产生电磁辐射。
在背离半导体本体2的侧上,接触面25和另外的接触面26优选形成平坦的面。于是,半导体本体2可以简化地固定在器件支承体上。
不同于所示的实施例,半导体本体2也可以具有两个或者更多个凹处用于接触n导电的半导体层22。由此可以简化在横向方向上均匀地将载流子注入到有源区21中。
在图5中在示意性截面图中示出了光电子器件的一个实施例。
光电子器件1包括器件支承体3。在器件支承体上固定有两个半导体本体2。其上分别设置有接触面25和另外的接触面26的半导体本体2分别如结合图4所描述的那样来实施。特别地,具有设计用于产生辐射的有源区21的半导体层序列形成半导体本体2。相应的生长衬底本体20(在该生长衬底本体上半导体本体如结合图4所描述的那样构建)在图5中所示的制成的光电子器件中完全地从半导体本体去除。与此不同,生长衬底本体也可以仅仅局部地去除或者薄化。
接触面25和另外的接触面26分别与器件支承体的连接面35以及另外的连接面36导电连接。在半导体本体2和器件支承体3之间构建有间隙5。该间隙在横向方向上局部地由连接面35、36和/或接触面25、26形成边界。
间隙5用填充材料50来填充。填充材料特别是用于使半导体本体2机械地稳定。半导体本体2于是可以特别是在制造光电子器件1期间耐受较高的机械负载。由此简化了光电子器件1的制造。
不同于所示的实施例,间隙5也可以仅仅部分地以填充材料来填充,其中填充材料合乎目的地使半导体本体2充分地机械稳定。
半导体本体2被包封物6包围,该包封物优选将半导体本体封装。借助包封物,可以分别保护半导体本体免受外部影响如湿气。
如结合图1A至1H所描述的那样,在包封物6中可以嵌入辐射转换材料。可替选地或者补充地,辐射转换材料也可以在与包封物6分离的层中构建。
此外,半导体本体至少之一可以如结合图1F所描述的那样设置有结构。
光电子器件1的其他元件、特别是器件支承体3、连接面35、36和光学元件7可以如结合图1A至1H、2A至2G以及3A至3G所描述的那样来实施。
本专利申请要求德国专利申请102007030314.0和102007043877.1的优先权,它们的公开内容通过引用结合于此。
本发明并未通过借助实施例的描述而局限于此。更确切地说,本发明包括任意新的特征以及特征的任意组合,特别是包含权利要求中的特征的任意组合,即使该特征或者该组合本身并未明确地在权利要求或者实施例中说明。

Claims (15)

1.一种用于制造多个光电子器件(1)的方法,包括以下步骤:
a)提供多个分别带有半导体层序列的半导体本体(2);
b)提供带有多个连接面(35)的器件支承复合结构(30);
c)将半导体本体(2)相对于器件支承复合结构(30)定位;
d)建立器件支承复合结构(30)的连接面(35)与关联于所述连接面(35)的半导体本体(2)的导电连接,并且将该半导体本体(2)固定在器件支承复合结构(30)上;以及
e)制成多个光电子器件(2),其中针对每个光电子器件(1)由器件支承复合结构(30)构建器件支承体(3)。
2.根据权利要求1所述的方法,其中:
-在步骤a)中将半导体本体(2)设置在辅助支承体(4)上,并且在步骤c)中将辅助支承体(4)相对于器件支承复合结构定位,使得半导体本体(2)朝向器件支承复合结构(30);并且
-在步骤a)中在辅助支承体(4)上在两个半导体本体(2)之间设置至少一个另外的半导体本体(2),其中在步骤d)中将所述两个半导体本体(2)并排地固定在器件支承复合结构(30)上。
3.根据权利要求1或2所述的方法,其中:
半导体本体(2)分别构建在用于半导体本体(2)的半导体层序列的生长衬底本体(20)上,并且在步骤d)之后将生长衬底本体(20)完全地或者部分地去除。
4.根据权利要求1至3中的任一项所述的方法,其中:
在步骤b)中在器件支承复合结构(30)上构建多个安装区域(31),这些安装区域分别设计用于固定半导体本体(2),并且在半导体本体(2A)的情况下与辅助支承体(4)分离,在步骤c)中将该半导体本体(2A)分别设置在安装区域(31)内,并且设置在安装区域(31)之外的半导体本体(2B)保留在辅助支承体(4)上。
5.一种用于制造多个光电子器件(1)的方法,包括以下步骤:
a)提供多个分别带有半导体层序列的半导体本体(2),其中半导体本体(2)分别构建在用于半导体本体(2)的半导体层序列的生长衬底本体(20)上;
b)提供多个器件支承体(3),它们分别具有至少一个连接面(35);
c)将半导体本体相对于器件支承体(3)来定位;
d)建立器件支承体(3)的连接面(35)与关联于所述连接面(35)的半导体本体(2)的导电连接,并且将该半导体本体(2)固定在器件支承体(3)上;
e)制成多个光电子器件(1),其中将生长衬底本体(20)从相应的半导体本体(2)完全地或者仅仅部分地去除。
6.根据权利要求5所述的方法,其中在步骤b)中在器件支承复合结构(30)中提供器件支承体(3)。
7.根据权利要求5或6所述的方法,其中在步骤c)中将半导体本体(2)单独地设置在器件支承复合结构上。
8.根据权利要求5或6所述的方法,其中:
-在步骤a)中将半导体本体(2)设置在辅助支承体(4)上,并且在步骤c)中将辅助支承体(4)相对于器件支承体(3)定位,使得半导体本体(2)朝向器件支承体(3);并且
-在步骤a)中在辅助支承体(4)上在两个半导体本体(2)之间设置有至少一个另外的半导体本体(2),其中在步骤d)中将所述两个半导体本体(2)并排地固定在器件支承体(3)上。
9.根据权利要求2或8所述的方法,其中辅助支承体(4)在步骤a)中设置有分离的半导体本体(2),这些半导体本体关于其光电子特性被预先选择。
10.根据权利要求2、8或9所述的方法,其中在步骤d)之后将半导体本体(2)选择性地从辅助支承体(4)剥离。
11.根据权利要求2、8、9或10所述的方法,其中辅助支承体(4)实施为薄膜。
12.根据权利要求11所述的方法,其中在制成的光电子器件中,薄膜的一部分保留在半导体本体(20)上。
13.根据权利要求5或者引用权利要求5的权利要求所述的方法,其中在步骤b)中在器件支承体(3)上分别构建有至少一个安装区域(31),该安装区域设计用于固定半导体本体(2)并且在半导体本体(2A)的情况下与辅助支承体(4)分离,在步骤c)中将该半导体本体(2A)分别设置在安装区域(31)内,并且设置在安装区域(31)之外的半导体本体(2B)保留在辅助支承体(4)上。
14.一种光电子器件(1),其具有带有至少两个连接面(35,36)的器件支承体(3)以及带有半导体层序列的半导体本体(2),其中在半导体本体(2)上构建至少两个接触面(25,26),这些接触面分别与连接面(35,36)导电连接,并且在半导体本体(2)和器件支承体(3)之间的间隙(5)至少部分地以填充材料(50)填充。
15.根据权利要求14所述的光电子器件,其中接触面(25,26)构建在有源区(21)的相同侧上。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623583A (zh) * 2011-01-27 2012-08-01 奇景光电股份有限公司 晶片级芯片的封装方法
CN108122732A (zh) * 2016-11-29 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置
CN106605013B (zh) * 2014-01-20 2019-03-22 欧司朗光电半导体有限公司 用于制造横向结构化的磷光层的方法和具有这种磷光层的光电子半导体组件

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008030815A1 (de) 2008-06-30 2009-12-31 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung einer Vielzahl von optoelektronischen Bauelementen
GB2464102A (en) * 2008-10-01 2010-04-07 Optovate Ltd Illumination apparatus comprising multiple monolithic subarrays
JP5590837B2 (ja) * 2009-09-15 2014-09-17 キヤノン株式会社 機能性領域の移設方法
JP5534763B2 (ja) * 2009-09-25 2014-07-02 株式会社東芝 半導体発光装置の製造方法及び半導体発光装置
DE102009048401A1 (de) 2009-10-06 2011-04-07 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen eines optoelektronischen Halbleiterbauteils und optoelektronisches Halbleiterbauteil
KR101601622B1 (ko) 2009-10-13 2016-03-09 삼성전자주식회사 발광다이오드 소자, 발광 장치 및 발광다이오드 소자의 제조방법
DE102010009015A1 (de) 2010-02-24 2011-08-25 OSRAM Opto Semiconductors GmbH, 93055 Verfahren zum Herstellen einer Mehrzahl von optoelektronischen Halbleiterchips
GB2484713A (en) 2010-10-21 2012-04-25 Optovate Ltd Illumination apparatus
US8241932B1 (en) * 2011-03-17 2012-08-14 Tsmc Solid State Lighting Ltd. Methods of fabricating light emitting diode packages
KR101766298B1 (ko) * 2011-03-30 2017-08-08 삼성전자 주식회사 발광소자 및 그 제조방법
US8896010B2 (en) 2012-01-24 2014-11-25 Cooledge Lighting Inc. Wafer-level flip chip device packages and related methods
WO2013112435A1 (en) 2012-01-24 2013-08-01 Cooledge Lighting Inc. Light - emitting devices having discrete phosphor chips and fabrication methods
US8907362B2 (en) 2012-01-24 2014-12-09 Cooledge Lighting Inc. Light-emitting dies incorporating wavelength-conversion materials and related methods
US9269873B2 (en) * 2012-03-13 2016-02-23 Citizen Holdings Co., Ltd. Semiconductor light emitting device and method for manufacturing same
US9847445B2 (en) * 2012-04-05 2017-12-19 Koninklijke Philips N.V. LED thin-film device partial singulation prior to substrate thinning or removal
US20140048824A1 (en) 2012-08-15 2014-02-20 Epistar Corporation Light-emitting device
US9356070B2 (en) 2012-08-15 2016-05-31 Epistar Corporation Light-emitting device
US20140151630A1 (en) * 2012-12-04 2014-06-05 Feng-Hsu Fan Protection for the epitaxial structure of metal devices
DE102013103079A1 (de) * 2013-03-26 2014-10-02 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip und Verfahren zur Herstellung eines optoelektronischen Halbleiterchips
DE102013107531A1 (de) * 2013-07-16 2015-01-22 Osram Opto Semiconductors Gmbh Optoelektronischer Halbleiterchip
DE102013111496A1 (de) * 2013-10-18 2015-04-23 Osram Opto Semiconductors Gmbh Verfahren zum Herstellen von optoelektronischen Halbleiterbauelementen und optoelektronisches Halbleiterbauelement
US9343443B2 (en) 2014-02-05 2016-05-17 Cooledge Lighting, Inc. Light-emitting dies incorporating wavelength-conversion materials and related methods
US11472171B2 (en) * 2014-07-20 2022-10-18 X Display Company Technology Limited Apparatus and methods for micro-transfer-printing
CN105789196B (zh) 2014-12-22 2019-10-08 日月光半导体制造股份有限公司 光学模块及其制造方法
US9972740B2 (en) 2015-06-07 2018-05-15 Tesla, Inc. Chemical vapor deposition tool and process for fabrication of photovoltaic structures
JP6537410B2 (ja) * 2015-08-31 2019-07-03 シチズン電子株式会社 発光装置の製造方法
DE102015116983A1 (de) * 2015-10-06 2017-04-06 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils und optoelektronisches Halbleiterbauteil
WO2017194845A1 (fr) * 2016-05-13 2017-11-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procédé de fabrication d'un dispositif optoélectronique comportant une pluralité de diodes au nitrure de gallium
US9748434B1 (en) 2016-05-24 2017-08-29 Tesla, Inc. Systems, method and apparatus for curing conductive paste
US9954136B2 (en) 2016-08-03 2018-04-24 Tesla, Inc. Cassette optimized for an inline annealing system
US10115856B2 (en) 2016-10-31 2018-10-30 Tesla, Inc. System and method for curing conductive paste using induction heating
DE102017101536B4 (de) 2017-01-26 2022-06-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zum Selektieren von Halbleiterchips
US10937768B2 (en) 2017-03-13 2021-03-02 Seoul Semiconductor Co., Ltd. Method of manufacturing display device
GB201705364D0 (en) 2017-04-03 2017-05-17 Optovate Ltd Illumination apparatus
GB201705365D0 (en) 2017-04-03 2017-05-17 Optovate Ltd Illumination apparatus
FR3065321B1 (fr) * 2017-04-14 2019-06-21 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un dispositif d'affichage emissif a led
FR3066320B1 (fr) * 2017-05-11 2019-07-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de fabrication d'un dispositif d'affichage emissif a led
GB201800574D0 (en) 2018-01-14 2018-02-28 Optovate Ltd Illumination apparatus
GB201803767D0 (en) 2018-03-09 2018-04-25 Optovate Ltd Illumination apparatus
GB201807747D0 (en) 2018-05-13 2018-06-27 Optovate Ltd Colour micro-LED display apparatus
DE102018120881A1 (de) * 2018-08-27 2020-02-27 Osram Opto Semiconductors Gmbh Bauelement und Verfahren zur Herstellung eines Bauelements
DE102019121672A1 (de) * 2019-08-12 2021-02-18 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren und vorrichtung zum aufnehmen und ablegen von optoelektronischen halbleiterchips
US11610868B2 (en) 2019-01-29 2023-03-21 Osram Opto Semiconductors Gmbh μ-LED, μ-LED device, display and method for the same
US11156759B2 (en) 2019-01-29 2021-10-26 Osram Opto Semiconductors Gmbh μ-LED, μ-LED device, display and method for the same
US11302248B2 (en) 2019-01-29 2022-04-12 Osram Opto Semiconductors Gmbh U-led, u-led device, display and method for the same
US11271143B2 (en) 2019-01-29 2022-03-08 Osram Opto Semiconductors Gmbh μ-LED, μ-LED device, display and method for the same
WO2020182278A1 (en) * 2019-03-08 2020-09-17 Osram Opto Semiconductors Gmbh Method for producing optoelectronic semiconductor devices and optoelectronic semiconductor device
US11538852B2 (en) 2019-04-23 2022-12-27 Osram Opto Semiconductors Gmbh μ-LED, μ-LED device, display and method for the same
TW202102883A (zh) 2019-07-02 2021-01-16 美商瑞爾D斯帕克有限責任公司 定向顯示設備
EP4018236A4 (en) 2019-08-23 2023-09-13 RealD Spark, LLC DEVICE FOR DIRECTIONAL LIGHTING AND VISIBILITY DISPLAY
US11163101B2 (en) 2019-09-11 2021-11-02 Reald Spark, Llc Switchable illumination apparatus and privacy display
WO2021050967A1 (en) 2019-09-11 2021-03-18 Reald Spark, Llc Directional illumination apparatus and privacy display
CN114729730A (zh) * 2019-10-03 2022-07-08 瑞尔D斯帕克有限责任公司 包括无源光学纳米结构的照明设备
JP2022550540A (ja) 2019-10-03 2022-12-02 リアルディー スパーク エルエルシー 受動光学ナノ構造を備える照明装置
WO2021168090A1 (en) 2020-02-20 2021-08-26 Reald Spark, Llc Illumination and display apparatus

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5617384A (en) * 1979-07-20 1981-02-19 Tokyo Shibaura Electric Co Production of display device
DE4305296C3 (de) * 1993-02-20 1999-07-15 Vishay Semiconductor Gmbh Verfahren zum Herstellen einer strahlungsemittierenden Diode
DE59814431D1 (de) * 1997-09-29 2010-03-25 Osram Opto Semiconductors Gmbh Halbleiterlichtquelle und Verfahren zu ihrer Herstellung
JP3641122B2 (ja) * 1997-12-26 2005-04-20 ローム株式会社 半導体発光素子、半導体発光モジュール、およびこれらの製造方法
JP4491948B2 (ja) * 2000-10-06 2010-06-30 ソニー株式会社 素子実装方法および画像表示装置の製造方法
US6795751B2 (en) * 2000-12-06 2004-09-21 Honeywell International Inc. System and method to accomplish high-accuracy mixing
JP4461616B2 (ja) * 2000-12-14 2010-05-12 ソニー株式会社 素子の転写方法、素子保持基板の形成方法、及び素子保持基板
JP2002241586A (ja) * 2001-02-19 2002-08-28 Matsushita Electric Ind Co Ltd 波長変換ペースト材料、複合発光素子、半導体発光装置及びそれらの製造方法
US6417019B1 (en) * 2001-04-04 2002-07-09 Lumileds Lighting, U.S., Llc Phosphor converted light emitting diode
JP2003209346A (ja) * 2002-01-16 2003-07-25 Sony Corp 部品の実装方法及び電子装置
WO2004068572A2 (de) * 2003-01-31 2004-08-12 Osram Opto Semiconductors Gmbh Verfahren zur herstellung eines halbleiterbauelements
JP4082242B2 (ja) * 2003-03-06 2008-04-30 ソニー株式会社 素子転写方法
DE102004036295A1 (de) * 2003-07-29 2005-03-03 GELcore, LLC (n.d.Ges.d. Staates Delaware), Valley View Flip-Chip-Leuchtdioden-Bauelemente mit Substraten, deren Dicke verringert wurde oder die entfernt wurden
JP2005093649A (ja) * 2003-09-17 2005-04-07 Oki Data Corp 半導体複合装置、ledプリントヘッド、及び、それを用いた画像形成装置
US7408566B2 (en) * 2003-10-22 2008-08-05 Oki Data Corporation Semiconductor device, LED print head and image-forming apparatus using same, and method of manufacturing semiconductor device
JP4954712B2 (ja) * 2003-12-24 2012-06-20 ジーイー ライティング ソリューションズ エルエルシー 窒化物フリップチップからのサファイヤのレーザ・リフトオフ
NL1029688C2 (nl) * 2005-08-05 2007-02-06 Lemnis Lighting Ip Gmbh Werkwijze voor het vervaardigen van een elektrische schakeling voorzien van een veelvoud van LED's.
US7125734B2 (en) * 2005-03-09 2006-10-24 Gelcore, Llc Increased light extraction from a nitride LED
US7290946B2 (en) * 2005-03-11 2007-11-06 Cortek Opto Corp. Optical subassembly
US7673466B2 (en) * 2005-08-31 2010-03-09 Pacy David H Auxiliary power device for refrigerated trucks
JP4966199B2 (ja) * 2005-09-20 2012-07-04 ルネサスエレクトロニクス株式会社 Led光源
KR100714589B1 (ko) * 2005-10-05 2007-05-07 삼성전기주식회사 수직구조 발광 다이오드의 제조 방법
JP4849866B2 (ja) * 2005-10-25 2012-01-11 京セラ株式会社 照明装置
US20070200063A1 (en) * 2006-02-28 2007-08-30 Virgin Islands Microsystems, Inc. Wafer-level testing of light-emitting resonant structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102623583A (zh) * 2011-01-27 2012-08-01 奇景光电股份有限公司 晶片级芯片的封装方法
CN106605013B (zh) * 2014-01-20 2019-03-22 欧司朗光电半导体有限公司 用于制造横向结构化的磷光层的方法和具有这种磷光层的光电子半导体组件
CN108122732A (zh) * 2016-11-29 2018-06-05 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制造方法和电子装置

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JP5334966B2 (ja) 2013-11-06
DE102007043877A1 (de) 2009-01-08
EP2162927B1 (de) 2018-10-24
CN101681964B (zh) 2013-05-08
KR101433423B1 (ko) 2014-08-27
US20100171215A1 (en) 2010-07-08
TW200905930A (en) 2009-02-01
EP2162927A1 (de) 2010-03-17

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