CN102623583A - 晶片级芯片的封装方法 - Google Patents

晶片级芯片的封装方法 Download PDF

Info

Publication number
CN102623583A
CN102623583A CN2011102612140A CN201110261214A CN102623583A CN 102623583 A CN102623583 A CN 102623583A CN 2011102612140 A CN2011102612140 A CN 2011102612140A CN 201110261214 A CN201110261214 A CN 201110261214A CN 102623583 A CN102623583 A CN 102623583A
Authority
CN
China
Prior art keywords
chip
film
packing
wafer level
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011102612140A
Other languages
English (en)
Inventor
何昕桦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Himax Technologies Ltd
Original Assignee
Himax Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Technologies Ltd filed Critical Himax Technologies Ltd
Publication of CN102623583A publication Critical patent/CN102623583A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0041—Processes relating to semiconductor body packages relating to wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/56—Materials, e.g. epoxy or silicone resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

本发明公开一种晶片级芯片的封装方法，其包括以下步骤：首先，提供多个附接于一第一薄膜上的芯片，其中这些在第一薄膜上的芯片分别对应一基板上的多个电极图样配置。接着，分别于每一芯片的至少一表面形成一磷光层。继之，在磷光层上配置一第二薄膜，且第二薄膜相对第一薄膜。然后，从每一芯片的底面移除第一薄膜。接着，使这些芯片的底面附接于基板上。然后，通过打线接合方式使每一芯片与对应的电极图样电性连接。最后，提供一封装胶体包覆每一芯片，且使封装胶体凝固。上述的晶片级芯片的封装方法能够减少封装时间及制造成本，因而提升制造效率。

Description

晶片级芯片的封装方法
技术领域
本发明涉及一种封装方法，且特别是涉及一种晶片级芯片的封装方法。
背景技术
相比较于白热光等其它光源，发光二极管(light emitting diode，LED)不但耗能较少，且也具有较长的寿命、较快的反应速度、较小的尺寸、较低维护成本以及良好的可靠度等优点。据此，LED已成为在现代生活中，特别是在电子、通讯或消费型产品领域中不可或缺的元件。
图1A至图1E绘示现有的LED芯片(chip)的封装步骤的剖面图。请参照图1A至图1E，首先如图1A所示，提供一基板110，其中基板110具有多个电极层112a及112b。电极层112a及112b用以配置多个LED管芯(die)以形成多个LED芯片。然后，如图1B所示，于多个LED管芯中先选取一个LED管芯120，其中该LED管芯120用以与电极层112b连接。之后，如图1C所示，通过打线接合方式使电极层112b上的LED管芯120与电极层112a电性连接。举例来说，电极层112b上的LED管芯120系通过接合线130与电极层112a电性连接。接着，请参照图1D，于LED管芯120上形成荧光层(fluorescent layer)140。最后，提供封装胶体150以覆盖LED管芯120及LED管芯120所对应的电极层112a及112b。至此，便完成第一个LED芯片100的组装。然而，在上述图1A至图1E的封装步骤中，每完成一个如图1A至图1E的流程，仅能生产一个LED芯片。因此若要制造一千个LED芯片100，每一个封装步骤就必须重复施行一千次。由此可知，现有的LED芯片的封装方法为一个耗时又冗长的制作工艺，而相当不符合成本效益。
发明内容
本发明的目的在于提供一种晶片级芯片的封装方法，其能够减少封装时间及制造成本，因而提升制造效率。
为达上述目的，本发明提出一种晶片级芯片封装方法，其步骤如下。首先，提供多个附接于一第一薄膜上的芯片，其中这些在第一薄膜上的芯片分别对应一基板的多个电极图样配置，且每一芯片的一底面与第一薄膜接触。下一步，分别于每一芯片的至少一表面形成一磷光层。接着，在磷光层上配置一第二薄膜，且第二薄膜相对第一薄膜。再者，从每一芯片的底面移除第一薄膜。然后，使上述芯片的基面附接于基板上。之后，通过打线接合方式使每一芯片与所对应的电极图样电性连接。最后，提供一封装胶体包覆每一芯片，且使封装胶体凝固。
在本发明的一实施例中，晶片级芯片封装方法还包括于通过打线接合方式使每一芯片与对应的电极图样电性连接之前，移除第二薄膜。
在本发明的一实施例中，上述的附接步骤包括于底面配置一附接材料，以使底面通过附接材料附接于基板上。
在本发明的一实施例中，上述的附接步骤还包括一回焊过程，以对底面及基板间的附接材料进行回焊。
在本发明的一实施例中，上述的磷光层通过一涂布制作工艺形成。涂布制作工艺包括一旋转涂布方法(spin-coating method)、一印刷技术(printingtechnique)、一修刮法(scraper method)、一网板印刷法(screen printingmethod)、一喷覆法(spraying method)、一电泳沉积法(electrophoresis depositmethod)、一蒸发法(evaporation method)或一溅镀制作工艺(sputter process)。
在本发明的一实施例中，上述的附接步骤还包括烘烤在底面与基板间的附接材料。
在本发明的一实施例中，上述的附接材料为一锡膏、一银胶或一共析材料(eutectoid material)。
在本发明的一实施例中，上述的每一芯片包括一凸块及一管芯(die)，并且凸块配置于磷光层及管芯之间。
在本发明的一实施例中，上述的每一芯片的凸块通过打线接合方式与对应的电极图样电性连接。
在本发明的一实施例中，上述的第一薄膜与第二薄膜为蓝膜。
在本发明的一实施例中，上述的基板为一硅基板、一陶瓷基板或以树脂射出方法形成的基板。
在本发明的一实施例中，上述的芯片为一发光二极管芯片。
基于上述，在本发明的实施例中，由于基板上的多个电极图样所对应的多个芯片在每个步骤中是同时被处理，故本实施例的晶片级芯片的封装方法能够减少封装时间及制造成本，因而提升制造效率。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附图式作详细说明如下。
附图说明
所附图式为用以对本发明提供进一步理解，此些图式并入并构成此说明书的一部分；其绘示本发明的实施例，并与说明书一同用以解释本发明的原理。
图1A至图1E为现有的LED芯片的封装步骤的剖视图；
图2A至图2H为本发明一实施例的晶片级芯片的封装步骤的剖视图；
图3为说明图2A至图2H的封装步骤的流程图。
主要元件符号说明
100、210：芯片
110、230：基板
112a、112b：电极层
120、214：管芯
130、260：接合线
140：荧光层
150、270：封装胶体
212：凸块
220a：第一薄膜
220b：第二薄膜
232：电极图样
240：磷光层
250：附接材料
S1：底面
S110～S170：步骤
具体实施方式
以下将仔细参照本发明的较佳实施例，其实例绘示所附图式中。于任何可能情况下，图式及说明书中所使用的相同标号表示相同或类似的部分。
此些图式并未依实际比例绘示，而仅用以说明本发明。以下将参照用以说明的例示的实施方式叙述本发明的多个态样。应理解所提供的许多特定细节、关系及方法为用以提供本发明的全面性理解。另外，本发明可以许多不同形式来体现，而不应理解为仅限于以下所提出的实施例。举例而言，本发明可以方法或系统来作为体现。
图2A至图2H绘示本发明一实施例的晶片级芯片的封装步骤的剖视图。图3为说明上述图2A至图2H的封装步骤的流程图。请参照图2A至图2H及图3，首先，如图2A所示，提供多个附接于第一薄膜220a上的芯片210，其中第一薄膜220a上的这些芯片210分别对应的基板230上的多个电极图样232配置，并且每一芯片210的底面S1与第一薄膜220a接触(步骤S110)。再者，如图2A所示，每一芯片210包括至少一个凸块212(仅示意地绘示两个)及一个管芯214，其中管芯214例如是发光二极管(light emitting diode，LED)。于此，基板230为硅基板、陶瓷(ceramic)基板或以树脂射出法(resininjection method)形成的基板，但本发明不限于此。另外，本实施例的第一薄膜220a例如为蓝膜。在本实施例中，芯片210为晶片级芯片。除此之外，位于第一薄膜220a上的芯片210例如为LED芯片，且这些LED芯片是依据个别的光学及电子特性(例如发射波长、电压或辐射通量)而分类好的芯片。
接着，如图2B所示，在每一芯片210的至少一表面形成磷光层(phosphorlayer)240(步骤S120)。详细而言，磷光层240可利用涂布制作工艺形成在除了芯片210的底面S1外的每个表面。另外，本实施例的涂布制作工艺可为旋转涂布法(spin-coating method)、印刷技术(printing technique)、修刮法(scraper method)、网板印刷法(screen printing method)、喷覆法(spraying method)、电泳沉积法(electrophoresis deposit method)、蒸发法(evaporation method)或溅镀制作工艺(sputter process)。在本实施例中，凸块212配置于磷光层240与管芯214之间。另外，凸块例如是金(Au)球或铝(A1)球，但本发明不限于此。
在步骤S120之后，如图2C所示，磷光层240上配置第二薄膜220b，且第二薄膜220b相对第一薄膜220a(步骤S130)。其中第二薄膜220b位于第一薄膜220a的上方，且第二薄膜220b例如为蓝膜。接着，如图2D所示，从每一芯片210的底面S1移除第一薄膜220a(步骤S140)。详细而言，从图2C至图2D，原先图2C的芯片210位于第一薄膜220a及第二薄膜220b间的架构可被先翻转，以使第一薄膜220a位于第二薄膜220b之上且位于图2A的基板230及芯片210之间。除此之外，每一芯片的位置可以根据电极图样232的位置微调。然后，将图2C的第一薄膜220a从每一芯片210的底面S1移除，以形成如图2D的架构。
在步骤S140之后，如图2F所示，将芯片210的底面S1附接于基板230，以使图2C的原本和基板230分离的芯片210与基板230附接(步骤S150)。详细而言，如图2E所示，附接步骤(即步骤S150)可以包括在底面S1上配置附接材料250使底面S1通过附接材料250附接于基板230上。在本实施例中，附接步骤可以在高温下施行(例如从摄氏150度至摄氏280度)，以使得芯片210可还牢固地附接于基板230上。举例来说，本实施例的附接材料250可以是锡膏、银胶或共析材料(eutectoid material)。另外，附接步骤可更包括回焊过程，以对底面S1及基板230间的附接材料250进行回焊。另外，附接材料250可为银胶，且附接步骤更包括烘烤介于底面S1及基板230间的附接材料250。另外，在另一实施例中，附接材料230可为共析材料，且附接步骤还包括加热共析材料。
请参照图2G，在芯片210附接于基板230的电极图样232之后，通过打线接合方式使每一芯片210与对应的电极图样232电性连接(步骤S160)。举例来说，每一芯片210通过接合线260与对应的电极图样232电性连接。详细而言，可藉由对图2F的架构进行翻转，以使芯片210在基板230之上。接着，再移除图2F的第二薄膜220b。然后，如图2G所示，芯片210便能通过凸块212与接合线260与电极图样232电性连接，其中接合线260例如为金线、铝线或金属线。
最后，如图2H所示，提供封装胶体270以包覆芯片210，并使封装胶体凝固(步骤S170)。其中封装胶体270例如包覆芯片210、接合线260及电极图样232。如此一来，便完成晶片级芯片(即芯片210)的封装。值得注意的是，由于在每个步骤(即步骤S110至步骤S170)中，多个芯片210是被同时处理，故当步骤S170执行完毕时，大量的芯片210可被封装完成。因此，当多个晶片级芯片需要被封装时，本实施例的封装方法较现有的封装方法更加快速。也因此，本实施例所提出的晶片级芯片封装方法能有效地减少封装时间及制造成本，从而改善制造效率。
综上所述，通过本发明的实施例的封装方法，基板上的多个电极图样所对应的多个芯片能在每个步骤中同时被处理，故相比较于现有的每一步骤仅能处理一个管芯的封装方法而言，本发明的实施例的封装方法快速许多。因此，本发明的实施例的封装方法能有效地减少封装时间及制造成本，从而有助于大量生产。
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。

Claims (12)

1.一种晶片级芯片的封装方法，包括：
提供多个附接于一第一薄膜上的芯片，其中该些在该第一薄膜上的芯片分别对应一基板的多个电极图样配置，且每一芯片的一底面与该第一薄膜接触；
分别于每一芯片的至少一表面形成一磷光层；
在该磷光层上配置一第二薄膜，且该第二薄膜相对该第一薄膜；
从每一芯片的该底面移除该第一薄膜；
使该些芯片的该些底面附接于该基板上；
通过打线接合方式使每一芯片与对应的电极图样电性连接；以及
提供一封装胶体包覆每一芯片，且使该封装胶体凝固。
2.如权利要求1所述的晶片级芯片的封装方法，还包括于通过打线接合方式使每一芯片与对应的电极图样电性连接之前，移除该第二薄膜。
3.如权利要求1所述的晶片级芯片的封装方法，其中该附接步骤包括于该底面配置一附接材料，以使该底面通过该附接材料附接于该基板上。
4.如权利要求3所述的晶片级芯片的封装方法，其中该附接步骤还包括一回焊过程，以对该底面及该基板间的该附接材料进行回焊。
5.如权利要求1所述的晶片级芯片的封装方法，其中该磷光层通过一涂布制作工艺形成，且该涂布制作工艺包括一旋转涂布法、一印刷技术、一修刮法、一网板印刷法、一喷覆法、一电泳沉积法、一蒸发法或一溅镀制作工艺。
6.如权利要求3所述的晶片级芯片的封装方法，其中该附接步骤还包括烘烤在该底面与该基板间的该附接材料。
7.如权利要求3所述的晶片级芯片的封装方法，其中该附接材料为一锡膏、一银胶或一共析材料。
8.如权利要求1所述的晶片级芯片的封装方法，其中每一芯片包括一凸块及一管芯，并且该凸块配置于该磷光层及该管芯之间。
9.如权利要求7所述的晶片级芯片的封装方法，其中每一芯片的该凸块通过打线接合方式与对应的电极图样电性连接。
10.如权利要求1所述的晶片级芯片的封装方法，其中该第一薄膜与该第二薄膜为蓝膜。
11.如权利要求1所述的晶片级芯片的封装方法，其中该基板为一硅基板、一陶瓷基板或以树脂射出方法形成的基板。
12.如权利要求1所述的晶片级芯片的封装方法，其中该芯片为一发光二极管芯片。
CN2011102612140A 2011-01-27 2011-09-06 晶片级芯片的封装方法 Pending CN102623583A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161436605P 2011-01-27 2011-01-27
US61/436,605 2011-01-27
US13/166,167 US8227271B1 (en) 2011-01-27 2011-06-22 Packaging method of wafer level chips
US13/166,167 2011-06-22

Publications (1)

Publication Number Publication Date
CN102623583A true CN102623583A (zh) 2012-08-01

Family

ID=46513022

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011102612140A Pending CN102623583A (zh) 2011-01-27 2011-09-06 晶片级芯片的封装方法

Country Status (3)

Country Link
US (1) US8227271B1 (zh)
CN (1) CN102623583A (zh)
TW (1) TW201232677A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103395571A (zh) * 2013-08-13 2013-11-20 肇庆爱晟电子科技有限公司 基于托盘排列的热敏电阻芯片的包装方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101881446B1 (ko) 2013-01-25 2018-07-24 삼성전자주식회사 발광 소자 패키지의 제조 방법
TWI601225B (zh) * 2013-10-07 2017-10-01 晶元光電股份有限公司 發光二極體組件及製造方法
KR101584201B1 (ko) 2014-01-13 2016-01-13 삼성전자주식회사 반도체 발광소자 및 이의 제조방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040032013A1 (en) * 2002-08-15 2004-02-19 Cobbley Chad A. Semiconductor dice packages employing at least one redistribution layer and methods of fabrication
US20050029638A1 (en) * 2000-04-27 2005-02-10 Ahn Byung Hoon Leadframe and semiconductor package made using the leadframe
US20080142817A1 (en) * 2005-06-30 2008-06-19 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
CN101681964A (zh) * 2007-06-29 2010-03-24 欧司朗光电半导体有限公司 用于制造光电子器件的方法以及光电子器件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7083993B2 (en) * 2003-04-15 2006-08-01 Luminus Devices, Inc. Methods of making multi-layer light emitting devices
US7372198B2 (en) * 2004-09-23 2008-05-13 Cree, Inc. Semiconductor light emitting devices including patternable films comprising transparent silicone and phosphor
US7932111B2 (en) * 2005-02-23 2011-04-26 Cree, Inc. Substrate removal process for high light extraction LEDs
US20080121911A1 (en) * 2006-11-28 2008-05-29 Cree, Inc. Optical preforms for solid state light emitting dice, and methods and systems for fabricating and assembling same
TWI325644B (en) * 2007-01-03 2010-06-01 Chipmos Technologies Inc Chip package and manufacturing thereof
TWI396298B (zh) * 2007-08-29 2013-05-11 Everlight Electronics Co Ltd 發光半導體元件塗佈螢光粉的方法及其應用
US20100279437A1 (en) * 2009-05-01 2010-11-04 Koninklijke Philips Electronics N.V. Controlling edge emission in package-free led die
US8236582B2 (en) * 2008-07-24 2012-08-07 Philips Lumileds Lighting Company, Llc Controlling edge emission in package-free LED die
US20100038670A1 (en) * 2008-08-18 2010-02-18 Luminus Devices, Inc. Illumination assembly including chip-scale packaged light-emitting device
CN102332522A (zh) * 2010-07-15 2012-01-25 展晶科技(深圳)有限公司 发光二极管封装结构及封装方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050029638A1 (en) * 2000-04-27 2005-02-10 Ahn Byung Hoon Leadframe and semiconductor package made using the leadframe
US20040032013A1 (en) * 2002-08-15 2004-02-19 Cobbley Chad A. Semiconductor dice packages employing at least one redistribution layer and methods of fabrication
US20080142817A1 (en) * 2005-06-30 2008-06-19 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
CN101681964A (zh) * 2007-06-29 2010-03-24 欧司朗光电半导体有限公司 用于制造光电子器件的方法以及光电子器件

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103395571A (zh) * 2013-08-13 2013-11-20 肇庆爱晟电子科技有限公司 基于托盘排列的热敏电阻芯片的包装方法

Also Published As

Publication number Publication date
TW201232677A (en) 2012-08-01
US20120196393A1 (en) 2012-08-02
US8227271B1 (en) 2012-07-24

Similar Documents

Publication Publication Date Title
CN101755347B (zh) 发光装置及其制造方法
CN202084524U (zh) 封装板
CN101728470B (zh) 发光二极管装置及其制造方法
US20100012957A1 (en) Light-emitting diode device and method for fabricating the same
US10847691B2 (en) LED flip chip structures with extended contact pads formed by sintering silver
US20140120641A1 (en) Flip chip light emitting device package and manufacturing method thereof
CN102800778B (zh) 一种芯片倒装的发光二极管及其制造方法
JP5550886B2 (ja) Ｌｅｄ発光装置
JP2007227919A (ja) 発光ダイオードパッケージの製造方法
US20120305971A1 (en) Light emitting device lens, light emitting device module including light emitting device lens and method for manufacturing light emitting device module using light emitting device lens
CN102270653A (zh) 发光二极管阵列及其制造方法
WO2021129361A1 (zh) 一种阵列集成微型led芯片及其制作方法
KR20070045461A (ko) 발광 다이오드 및 그 제조 방법
JP2007258701A (ja) 発光ダイオードのパッケージ構造及びその製造方法
CN103378273B (zh) 发光二极管封装方法
CN102623583A (zh) 晶片级芯片的封装方法
CN102194801A (zh) 正向发光的发光二极管封装结构及其形成方法
CN108352423A (zh) 半导体器件
KR102486735B1 (ko) 미세 led 패키지 및 그의 생산방법
CN102044624A (zh) 一种可发复合光的led器件、发光元件及制造方法
CN202159699U (zh) 一种芯片倒装的发光二极管
JP2013115070A (ja) 半導体パッケージ及びその製造方法
US8866268B2 (en) Semiconductor package structure and manufacturing method thereof
JP7475735B2 (ja) ダイパッケージの接合及び移載方法
CN110428749A (zh) 一种按块堆叠封装的led显示屏模块和封装方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20120801