CN202084524U - 封装板 - Google Patents
封装板 Download PDFInfo
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- CN202084524U CN202084524U CN2010206476165U CN201020647616U CN202084524U CN 202084524 U CN202084524 U CN 202084524U CN 2010206476165 U CN2010206476165 U CN 2010206476165U CN 201020647616 U CN201020647616 U CN 201020647616U CN 202084524 U CN202084524 U CN 202084524U
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- 238000004806 packaging method and process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000013078 crystal Substances 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 238000009413 insulation Methods 0.000 claims description 37
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 229920000642 polymer Polymers 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
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- 238000003466 welding Methods 0.000 claims description 3
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- 230000017525 heat dissipation Effects 0.000 abstract description 2
- 239000007787 solid Substances 0.000 abstract 3
- 239000010408 film Substances 0.000 description 105
- 238000000034 method Methods 0.000 description 26
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 229910052802 copper Inorganic materials 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 12
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000005518 electrochemistry Effects 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
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- 229910052759 nickel Inorganic materials 0.000 description 4
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
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Abstract
一种封装板,此封装板安装于一电路载板上,且于封装板上安装有至少一半导体晶粒,该封装板包括:一基板、多个导电薄膜图案、与一绝缘薄膜图案。基板主要是由导电材质或半导体材质所构成,而其表面包括一固晶区与多个导电区。每个导电薄膜图案是分别分布在不同的导电区上,而绝缘薄膜图案是位于导电薄膜图案与基板间,但绝缘薄膜图案并未设置于固晶区上。其中,半导体晶粒是安装于固晶区上且与导电薄膜图案电连接。由于封装板的固晶区未涂布有绝缘薄膜图案,故藉由封装板可增加半导体封装结构的散热效果。
Description
技术领域
本实用新型是关于一种封装板,且特别是一种用于半导体封装的封装板。
背景技术
随着技术发展的日新月异,半导体的应用领域愈来愈广,除了逻辑运算(如:CPU)与数据储存(如:DRAM)外,发光二极管(Light Emitting Diode,俗称:LED)的应用也愈来愈普遍。然而,随着半导体的功效愈来愈强大,其发热量也随着增加,故散热技术也愈来愈重要。
就以发光二极管为例,发光二极管的发光效率与亮度已达到可被大众接受的水平,因此目前发光二极管已被应用在背光模块、汽车灯头与路灯等上。然而,随着发光二极管的亮度的提高,其庞大的发热量也困扰着本领域的技术人员。若无法将热量有效地排除,则发光二极管的亮度将会降低且使用寿命也会变短。
目前,于发光二极管装置中,其所使用的封装板主要可分为四种:印刷电路板(Print Circuit Board,简称PCB)、金属基印刷电路板(Metal Core Print Circuit Board,简称MCPCB)、陶瓷基板(Ceramic Substrate)、与硅基板(Silicon Substrate)。在这四种封装板中以印刷电路板的成本最低,然而其散热能力并不佳。另外,由于技术与成本上的限制,硅基板上的绝缘薄膜往往较薄,这样容易造成介电崩溃(Dielectrical Breakdown)。此外,目前市面上的陶瓷基板主要为Al2O3基板,Al2O3基板的散热能力较差。另外,同属于陶瓷基板的AlN基板虽然散热能力较佳,但却有成本较高的缺点。
MCPCB基板虽然比PCB基板有较高的散热能力,但在金属层与发光二极管晶粒之间仍有介电层的存在,故在散热能力的提升上仍是相当有限。
请参照图1,图1所绘示为习知的发光二极管装置的侧视图。此发光二极管装置100是安装在一电路载板10上,发光二极管装置100包括一发光二极管110与一封装板102,其中封装板102包括一基板120、一反射件130与一绝缘体140,其中基板120则为MCPCB基板。发光二极管110与反射件130皆设置在基板120上,反射件130则构成一杯状的凹穴132,发光二极管110是位于凹穴132中。该凹穴132的壁面为光滑的反射面,可将发光二极管110所发出的光进行反射,以增加光线的指向性。然而,由于反射件130与基板120是属于两个不同的个体,故随着使用时间的增长,反射件130与基板120间可能会产生异位或脱离的现象。
另外,发光二极管110上还连接有接线112与接线114,其中接线112是连接到基板120的正导电区121,而接线114则是连接到基板120的负导电区122,而发光二极管110则是位于基板120的固晶区123上,其中正导电区121、负导电区122、与固晶区123是藉由绝缘体140而相隔离。由于绝缘体140是以灌胶的方式而形成于基板120的开孔中,故该开孔需具有一定的宽度大小,否则胶体便不易流入,但这样一来除了增加基板120的宽度外,还分别增加了正导电区121及负导电区122与发光二极管110的距离,也因此接线112,114的长度需较长。而且,当发光二极管装置100安装到电路载板10上时,其也是利用打线接合(wire bonding)的方式与电路载板10电连接,这会增加发光二极管装置100在电路载板10上所占据的面积。
因此,如何设计出一种用于发光二极管装置或其它半导体装置的封装板,其具有较佳的散热效果、较长的使用寿命、且所占据的面积较小,已成为本领域具有通常知识者值得去思量的问题。
实用新型内容
本实用新型的主要目的在于提供一种封装板,该封装板具有较佳的散热效果、较长的使用寿命、与所占据的面积较小等优点。
根据上述目的与其它目的,本实用新型提供一种封装板,此封装板安装于一电路载板上,且于封装板上安装有至少一半导体晶粒,该封装板包括:一基板、多个导电薄膜图案、与一绝缘薄膜图案。基板主要是由导电材质或半导体材质所构成,而其表面包括一固晶区与多个导电区。每个导电薄膜图案是分别分布在不同的导电区上,而绝缘薄膜图案是位于导电薄膜图案与基板间,但绝缘薄膜图案并未设置于固晶区上。其中,半导体晶粒是安装于固晶区上且与导电薄膜图案电连接。
于上述的封装板中,半导体晶粒为发光二极管,而导电区则包括一第一导电区与一第二导电区。导电薄膜图案包括一第一导电薄膜图案与一第二导电薄膜图案,该第一导电薄膜图案与该第二导电薄膜图案是分别位于第一导电区与第二导电区上,且第一导电薄膜图案与第二导电薄膜图案彼此并不相接触。
于上述的封装板中,于基板上设置有多个穿孔,这些穿孔是贯穿基板且分别位于不同的导电区上,且这些穿孔的孔壁上分布有导电薄膜。
于上述的封装板中,更包括一凹穴,该凹穴是位于固晶区且是一体成形于基板上,且半导体晶粒是位于凹穴内。
于上述的封装板中,导电薄膜图案更包括一第三导电薄膜图案,第三导电薄膜图案是涂布在固晶区,且第三导电薄膜图案是直接与基板相接触。此外,第三导电薄膜图案例如是与第二导电薄膜图案电连接,且半导体晶粒的其中一电极是与第三导电薄膜图案直接接触,而半导体晶粒的另外一电极则是藉由一第一接线而与第一导电薄膜图案相接触。
于上述的封装板中,基板的材质为铜或铝,或含铜与铝的任一成份的合金。或者也可为半导体材质,例如:硅。另外,导电薄膜图案的材质主要为铜,但也可包括其它的材质,例如:镍、金、或银,或者是含以上任一成份的合金。
于上述的封装板中,绝缘薄膜图案的材质为聚合物,此聚合物例如为环氧树脂(Epoxy)、硅胶(Silicone)、聚亚酰胺(Polyimide)、或防焊漆等,且其厚度较佳是大于2μm。
上述的封装板中,该封装板例如是利用表面黏着技术与母板进行电连接。
由于封装板的固晶区未涂布有绝缘薄膜图案,故藉由封装板可增加半导体封装结构的散热效果。
附图说明
图1所绘示为习知的发光二极管装置的侧视图。
图2A~图2E所绘示为本实用新型的发光二极管装置的制造方法的实施例。
图3A~图3C所绘示为绝缘薄膜图案的其中一种制造过程。
图4A~图4C所绘示为绝缘薄膜图案的另一种制造过程。
图5A~图5D所绘示为导电薄膜图案的其中一种制造过程。
图6A~图6D所绘示为导电薄膜图案的另一种制造过程。
图7A与图7B所绘示为本实用新型的发光二极管装置的第一实施例的示意图,图7A所绘示为剖面图,图7B所绘示为上视图。
图8A所绘示为本实用新型的发光二极管装置的第二实施例的示意图。
图8B所绘示为本实用新型的发光二极管装置的第三实施例的示意图。
图9所绘示为本实用新型的发光二极管装置的第四实施例的示意图。
图10所绘示为本实用新型的发光二极管装置的第五实施例的示意图。
具体实施方式
为让本实用新型的上述目的、特征和优点更能明显易懂,下文将以实施例并配合所附图式,作详细说明如下。
请参照图2A~图2E,图2A~图2E所绘示为本实用新型的发光二极管装置的制造方法的实施例。首先,如图2A所示,提供一基板220,此基板220的材质为铜。于基板220上设置有一凹穴221与多个穿孔222(于本实施例中为两个),其中凹穴221是一体成型于基板220上,且穿孔222是贯穿基板220。此外,基板220的表面被分成一固晶区223、一第一导电区224、与一第二导电区225,其中凹穴221是位于固晶区223,而两个穿孔222则分别位于第一导电区224与第二导电区225。关于固晶区223、第一导电区224、与第二导电区225如何划分,于下文中将有较详细的说明。
再来,如图2B所示,利用电镀法、电泳法、或电化学沈积法于基板220上形成有一绝缘薄膜图案240。其中,基板220的固晶区223并未被绝缘薄膜图案240所覆盖。所谓电镀法、电泳法、或电化学沈积法是指在基板220上施加一电压,让基板220本身带有正电或负电,而使带有相反电荷的粒子或离子沉积于基板220上。由于电镀法与电泳法是本领域具有通常知识者所孰悉的技术,故在此便不再详述。相较于习知的溅镀、阳极氧化、或热氧化法,本实施例的制造方法所采用的电镀法、电泳法、或电化学沈积法具有较高的成形速率,故能于较短的时间内形成厚度较厚的绝缘薄膜图案240。在本实施例中,绝缘薄膜图案240的厚度是大于2μm,较佳则是大于5μm。也因为绝缘薄膜图案240有较大的厚度,故其后在使用时较不容易产生介电崩溃的现象。
接着,如图2C所示,于基板220上形成导电薄膜图案230,其中导电薄膜图案230包括:一第一导电薄膜图案231、一第二导电薄膜图案232、与一第三导电薄膜图案233。其中,第一导电薄膜图案231与第二导电薄膜图案232是分别涂布在基板220的第一导电区224与第二导电区225上,而第三导电薄膜图案233则是涂布在固晶区223。由图2C可知,第一导电薄膜图案231与第二导电薄膜图案232是覆盖在绝缘薄膜图案240上。而且,第一导电薄膜图案231、第二导电薄膜图案232、与第三导电薄膜图案233并不互相接触。如此一来,便完成封装板202的制作。
请同时参照图2A与图2C,本领域具有通常知识者应可了解,基板220上的第一导电区224是指被第一导电薄膜图案231所覆盖的区域,而基板220上的第二导电区225则是指被第二导电薄膜图案232所覆盖的区域,而固晶区223则是位于第一导电区224与第二导电区225间。而且,在本实施例中,固晶区223上未涂布有绝缘薄膜图案240。
再来,请参照图2D,将一发光二极管210安装于凹穴221内,此发光二极管210为发光二极管(Light Emitting Diode)。然后,连接一第一接线211于发光二极管210与第一导电薄膜图案231间,同时也连接一第二接线212于发光二极管210与第二导电薄膜图案232间。此外,于发光二极管210上还涂布有一荧光粉层260。接着,请参照图2E,将透镜270安装在发光二极管210上方,此透镜270是藉由注胶成型的方式所制成。如此一来,便完成了发光二极管装置200的制作。
接下来,将对绝缘薄膜图案240的形成方式作较详细的介绍。请参照图3A~图3C,图3A~图3C所绘示为绝缘薄膜图案的形成过程。首先,请参照图3A,利用电镀法、电泳法、或电化学沈积法于基板220上形成一绝缘薄膜240’,在本实施例中,绝缘薄膜240’的材质为聚合物,例如为环氧树脂、硅胶、聚亚酰胺、或防焊漆。接着,请参照图3B,于绝缘薄膜240’上涂布一光阻层50,其中于固晶区223上的绝缘薄膜240’并未被光阻层50所覆盖。然后,进行蚀刻的制程,将未被光阻层50覆盖的绝缘薄膜240’清除。再来,如图3C所示,将光阻层50除去,便形成绝缘薄膜图案240。
或者,也可如图4A~图4C所示,先于不欲形成绝缘薄膜图案的地方(在图4A中为固晶区223)形成光阻层50。然后如图4B所示,利用电镀法、电泳法、或电化学沈积法于基板220上进行绝缘薄膜240’的沉积,由于绝缘薄膜240’不会形成在光阻层50上,故将光阻层50除去后,便形成绝缘薄膜图案240(如图4C所示)。
以下,将对导电薄膜图案230的制造过程作较详细地介绍。请参照图5A~图5D,图5A~图5D所绘示为导电薄膜图案的制造过程。首先,如图5A所示,于基板220上形成一晶种层230”,此晶种层230”的材质为铜,其分布在整个基板220上且覆盖整个绝缘薄膜图案240。于本实施例中,是利用浸镀法(immersionplating)或溅镀法而形成晶种层230”,此晶种层230”的材质例如为铜。再来,如图5B所示,于晶种层230”上涂布一光阻层50’,其中有部分的晶种层230”未被光阻层50’所覆盖。然后,进行蚀刻的制程,将未被光阻层50’覆盖的晶种层230”清除,便形成如图5C所示的晶种层图案230’。将光阻层50’去除后,便可利用电镀法、电泳法、或电化学沈积法,于晶种层图案230’上继续进行铜的沉积,以形成如图5D所示的导电薄膜图案230。另外,本领域具有通常知识者,也可于沉积铜后,另外沉积其它种类的金属,如:镍、金、和银或含以上任一成分的合金等,以增进导电薄膜图案230的物理性质。
另外,导电薄膜图案230的形成方式也不限于图5A~图5D所绘示的制造过程。请参照图6A~图6D,图6A~图6D所绘示为导电薄膜图案的另一种制造过程。首先,如图6A所示,于基板220上形成一晶种层230”,此晶种层230”的材质为铜,其覆盖整个绝缘薄膜图案240。再来,如图6B所示,于晶种层230”上涂布一光阻层50’,其中有部分的晶种层230”未被光阻层50’所覆盖。然后,利用电镀法或电泳法,于未被光阻层50”所覆盖的晶种层230”上继续进行铜及其它种类金属(如:镍和金)的沉积,使其增厚,而增厚的部份即为导电薄膜图案230。接着,将光阻层50’去除后,便可进行蚀刻制程,以将残余的晶种层230”移除,便形成如图6D所示的导电薄膜图案230。
需注意的是,图5A~图5D与图6A~图6D皆仅是示意,并未按照真实的比例尺进行绘制,例如导电薄膜图案230实际上就比晶种层图案230’或晶种层230”还要厚上许多。丨般来说,晶种层图案230’或晶种层230”是小于1μm,而导电薄膜图案230则是大于10μm。此外,本领域具有通常知识者也可于晶种层230”上直接以电镀、电泳、或电化学沈积的方式形成一导电薄膜,然后在于导电薄膜上涂布光阻层并进行蚀刻,以形成导电薄膜图案230。
图7A与图7B所绘示为本实用新型的发光二极管装置的第一实施例的示意图,图7A所绘示为剖面图,图7B所绘示为上视图。此发光二极管装置200是藉由图2A~图2D所绘示的制造方法所制成,且其是安装在一电路载板20上。此电路载板20例如为印刷电路板,于电路载板20上除了安装有发光二极管装置200外,还可安装其它的电子零件(未绘示),或安装更多的发光二极管装置200。
由图7A可知,发光二极管210的正下方并未涂布任何的绝缘薄膜图案240,由于第三导电薄膜图案233为铜、镍、金、或银等金属所构成,而基板220的材质为铜,故发光二极管210所产生的热量可轻易地由第三导电薄膜图案233与基板220传导出去,而使发光二极管210较不会有过热的情形产生。另外,涂布于发光二极管210上的荧光粉层260则是用于控制发光二极管装置200所发出的色光,例如当发光二极管210所发出的光为蓝光,而荧光粉层260是由黄色荧光粉所制成,则发光二极管装置200即可产生出白光。
由于凹穴221是一体成型在基板220上,故不会发生如图1的发光二极管装置100所会产生的问题,即:当使用时间增长后,反射件130与基板120间可能会产生脱离的现象。因此,相较于发光二极管装置100,发光二极管装置200可具有较长的使用寿命。此外,凹穴221的孔壁上涂布有第三导电薄膜图案233,其表面具有反射的效果,故发光二极管210所发出的光线会被其反射,且透镜270也具有聚光的作用,这些都能使发光二极管装置200的发光质量提高。
请参照图1、图7A及图7B,由于在封装板202上无需如封装板102般设置绝缘体140,故其基板220的面积较小,且第一接线211及第二接线212的长度会比接线112与接线114还要短,故发光二极管装置200可有较小的面积。此外,封装板102是利用打线接合的方式与电路载板10相连接,而封装板202则是利用表面黏着技术(surface mount technology)与电路载板20电连接,因此比较图1与图7A可清楚地看出:发光二极管装置200于电路载板20上所占据的面积会小于发光二极管装置100于电路载板10上所占据的面积。也因为发光二极管装置200于电路载板20上所占据的面积较小,故于电路载板20上可安装更多其它的电子零件或更多的发光二极管装置200。
在上述的实施例中,固晶区223是位于基板220表面的中央处,但本领域具有通常知识者应可明白固晶区223并不限设置在中央处。另外,基板220的材质为铜,但本领域具有通常知识者也可以使用其它的材质制作基板220,例如铝,或含铜与铝的任一成份的合金。此外,基板220的材质也可为半导体材质,例如硅,只要使基板220具有导电的性质即可。此外,固晶区223上也可不需设置凹穴221,而呈一平面状。
请参照图8A,图8A所绘示为本实用新型的发光二极管装置的第二实施例的示意图。相较于图7A的发光二极管装置200,图8A的发光二极管装置200’并未设置第三导电薄膜图案233,也就是说发光二极管210是直接与基板220相接触。
此外,在图7A中,第一导电薄膜图案231、第二导电薄膜图案232、与第三导电薄膜图案233彼此并不互相接触,且发光二极管210是以打线的方式分别与第一导电薄膜图案231及第二导电薄膜图案232电连接。然而,请参照图8B,图8B所绘示为本实用新型的发光二极管装置的第三实施例的示意图。在本实施例中,第二导电薄膜图案232与第三导电薄膜图案233是一体成形,也就是说彼此是互相连接在一起。此外,发光二极管装置200”的发光二极管210的其中一电极(在本实施例为正极)是与第三导电薄膜图案直接接触,而发光二极管210的另外一电极(在本实施例为负极)则是藉由第一接线211而与第一导电薄膜图案231相接触。
请参照图9,图9所绘示为本实用新型的发光二极管装置的第四实施例的示意图,发光二极管装置300的封装板302是安装在一电路载板30上。相较于图7A,封装板302的基板310并未设置凹穴221与任何穿孔222,且发光二极管装置300更包括一第三接线303与一第四接线304。第三接线303是连接于一第一导电薄膜图案331与电路载板30间,而第四接线304则是连接于一第二导电层图案332与电路载板30间。
由于于基板310上并未设置任何凹穴221与穿孔222,其表面为一平坦的表面,故在本实施例中,除了可使用电泳法、电镀法、或电化学沈积法外,还可使用印刷涂布法、溅镀法、或喷雾法等方式,而于基板310上形成绝缘薄膜图案340及导电薄膜图案330。
请参照图10,图10所绘示为本实用新型的发光二极管装置的第五实施例的示意图,发光二极管装置400的封装板402是安装在电路载板20上。相较于图7A,发光二极管装置400的基板410并未设置任何穿孔,其第一导电薄膜图案431与第二导电薄膜图案432除了分布于基板410的上表面与下表面外,还分布在基板410的侧壁上。因此,位于基板410上表面的导电薄膜430是藉由位于侧壁上的导电薄膜430,而与位于下表面的导电薄膜430相导通。在本实施例中,封装板402是利用表面黏着技术(surface mount technology)与电路载板20电连接。
在上述的实施例中,所有的发光二极管装置皆只有安装一发光二极管,但本领域具有通常知识者也可依情况安装更多的发光二极管,这些发光二极管可利用并联的方式连接在一起。
而且,除了上述的发光二极管外,封装板还可应用在其它半导体封装结构上。也就是说,于封装板的固晶区上,除了可安装发光二极管外,还可安装其它型态的半导体晶粒,例如:逻辑IC、内存IC、模拟IC、或CMOS影像感测组件。此外,随着所安装的半导体晶粒的不同,导电薄膜图案的个数也会不同,其主要是取决于半导体晶粒的接脚数,例如接脚的数目若为10个,则导电薄膜图案的个数则为10个。由于封装板的固晶区未涂布有绝缘薄膜图案,故藉由封装板可增加半导体封装结构的散热效果。
本实用新型以实施例说明如上,然其并非用以限定本实用新型所主张的专利权利范围。其专利保护范围当视后附的申请专利范围及其等同领域而定。凡本领域具有通常知识者,在不脱离本专利精神或范围内,所作的更动或润饰,均属于本实用新型所揭示精神下所完成的等效改变或设计,且应包含在下述的申请专利范围内。
Claims (14)
1.一种封装板,其特征在于,安装于一电路载板上,于该封装板上安装有至少一半导体晶粒,该封装板包括:
一基板,该基板主要是由导电材质或半导体材质所构成,该基板的表面包括一固晶区与多个导电区;
多个导电薄膜图案,这些导电薄膜图案是分别分布在不同的导电区上;及
一绝缘薄膜图案,该绝缘薄膜图案是位于该导电薄膜图案与该基板间,但该绝缘薄膜图案并未设置于该固晶区上;
其中,该半导体晶粒是安装于该固晶区上且与该导电薄膜图案电连接。
2.如权利要求1所述的封装板,其特征在于,其中该半导体晶粒为发光二极管,该导电区包括一第一导电区与一第二导电区,而该导电薄膜图案包括一第一导电薄膜图案与一第二导电薄膜图案,该第一导电薄膜图案与该第二导电薄膜图案是分别位于该第一导电区与该第二导电区上,且该第一导电薄膜图案与该第二导电薄膜图案彼此并不相接触。
3.如权利要求1或权利要求2所述的封装板,其特征在于,其中于该基板上设置有多个穿孔,这些穿孔是贯穿该基板且分别位于不同的导电区上,且该穿孔的孔壁上分布有该导电薄膜。
4.如权利要求2所述的封装板,其特征在于,其中该基板更包括一凹穴,该凹穴位于该固晶区且是一体成形于该基板上,且该半导体晶粒是位于该凹穴内。
5.如权利要求2所述的封装板,其特征在于,其中该导电薄膜图案更包括一第三导电薄膜图案,该第三导电薄膜图案是位于该 固晶区上,且该第三导电薄膜图案是直接与该基板相接触。
6.如权利要求5所述的封装板,其特征在于,其中该第三导电薄膜图案是与该第二导电薄膜图案电连接,且该半导体晶粒的其中一电极是与该第三导电薄膜图案直接接触,而该半导体晶粒的另外一电极则是藉由一第一接线而与该第一导电薄膜图案相接触。
7.如权利要求1或权利要求2所述的封装板,其特征在于,其中该基板的材质为硅。
8.如权利要求1或权利要求2所述的封装板,其特征在于,其中该绝缘薄膜图案的材质为聚合物。
9.如权利要求8所述的封装板,其特征在于,其中该绝缘薄膜图案的材质为环氧树脂、硅胶、聚亚酰胺、或防焊漆。
10.如权利要求1或权利要求2所述的封装板,其特征在于,其中该绝缘薄膜图案的厚度大于2μm。
11.如权利要求1或权利要求2所述的封装板,其特征在于,其中该封装板是利用表面黏着技术与该电路载板进行电连接。
12.如权利要求2所述的封装板,其特征在于,其中于该半导体晶粒上连接有一第一接线与一第二接线,该第一接线是连接于该第一导电薄膜图案与该半导体晶粒间,而该第二接线则是连接于该第二导电薄膜图案与该半导体晶粒间。
13.如权利要求2所述的封装板,其特征在于,更包括一第三接线与一第四接线,该第三接线是连接于该第一导电薄膜图案与该电路载板间,而该第四接线则是连接于该第二导电薄膜图案与该电路载板间。
14.如权利要求1或权利要求2所述的封装板,其特征在于,其中于该基板的侧壁上是分布有该导电薄膜图案。
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2011
- 2011-03-25 JP JP2011068063A patent/JP5640281B2/ja not_active Expired - Fee Related
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CN102606937B (zh) * | 2012-03-13 | 2014-03-26 | 深圳市华星光电技术有限公司 | 一种发光二极管灯条及背光模块 |
EP2645436A1 (fr) * | 2012-03-28 | 2013-10-02 | Commissariat à l'Énergie Atomique et aux Énergies Alternatives | Composant LED a faible résistance thermique avec chemins électrique et thermique dissocies |
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CN102456634A (zh) | 2012-05-16 |
JP5640281B2 (ja) | 2014-12-17 |
TWI414050B (zh) | 2013-11-01 |
JP2012089816A (ja) | 2012-05-10 |
US20120091496A1 (en) | 2012-04-19 |
TW201218338A (en) | 2012-05-01 |
US8723214B2 (en) | 2014-05-13 |
US20140045302A1 (en) | 2014-02-13 |
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