JP5640281B2 - パッケージ基板及びその製造方法 - Google Patents
パッケージ基板及びその製造方法 Download PDFInfo
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- JP5640281B2 JP5640281B2 JP2011068063A JP2011068063A JP5640281B2 JP 5640281 B2 JP5640281 B2 JP 5640281B2 JP 2011068063 A JP2011068063 A JP 2011068063A JP 2011068063 A JP2011068063 A JP 2011068063A JP 5640281 B2 JP5640281 B2 JP 5640281B2
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- thin film
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- 239000000758 substrate Substances 0.000 title claims description 173
- 238000004519 manufacturing process Methods 0.000 title claims description 32
- 239000010409 thin film Substances 0.000 claims description 176
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 20
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- 238000009713 electroplating Methods 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000001962 electrophoresis Methods 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000956 alloy Substances 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 7
- 238000007740 vapor deposition Methods 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 229920000642 polymer Polymers 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 239000003973 paint Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 2
- 238000007639 printing Methods 0.000 claims description 2
- 238000005507 spraying Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 230000017525 heat dissipation Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- -1 For example Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001652 electrophoretic deposition Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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Description
(a)基板を提供し、該基板は、主に導電材質又は半導体材質で構成される。更に、基板上に、複数の貫通孔を有し、且つ基板は、ダイ固定領域及び複数の導電領域に分けられる。
(b)基板上に絶縁薄膜パターンを形成し、該絶縁薄膜パターンは、ダイ固定領域上に形成されず、この絶縁薄膜パターンは、電気メッキ(Electrolytic deposition)、電気泳動(Electrophoretic deposition)、又は電気化学蒸着(Electrical Chemical Deposition)により基板上に形成される。
(c) 複数の導電薄膜パターンを形成し、これら導電薄膜パターンは、異なる導電領域上に分布される。
(d) 半導体チップをダイ固定領域内に取り付ける。
(e) 半導体チップ及び導電薄膜パターンを電気接続する。
100 発光ダイオード装置
102 パッケージ基板
110 発光ダイオード
112,114 接続線
120 基板
121 正導電領域
122 負導電領域
123 ダイ固定領域
130 反射部材
132 凹穴
140 絶縁体
<実施方式>
200,200'、200'' 発光ダイオード
202 パッケージ基板
220 基板
221 凹穴
222 貫通孔
223 ダイ固定領域
224 第1導電領域
225 第2導電領域
230 導電薄膜パターン
231 第1導電薄膜パターン
232 第2導電薄膜パターン
233 第3導電薄膜パターン
230' シード層パターン
230'' シード層
240 絶縁薄膜パターン
240' 絶縁薄膜
260 蛍光粉層
270 レンズ
20 回路基板
50,50',50'' フォトレジスト層
300 発光ダイオード装置
302 パッケージ基板
303 第3接続線
304 第4接続線
330 導電薄膜パターン
331 第1導電層パターン
332 第2導電層パターン
30 回路基板
400 発光ダイオード装置
402 パッケージ基板
410 基板
430 導電薄膜
Claims (25)
- 回路基板上に取り付けられるパッケージ基板であって、
該パッケージ基板上に少なくとも1つの半導体チップを取り付け、
該パッケージ基板は、導電材質から構成され、表面にダイ固定領域及び複数の導電領域を含み、更に凹穴を含み、該凹穴は、該ダイ固定領域に位置し、且つ該基板上に一体に成形され、且つ該半導体チップは、該凹穴内に位置する基板と、
それぞれ異なる導電領域に分布する複数の導電薄膜パターンと、
該導電薄膜パターンと該基板との間に位置するが、該ダイ固定領域には設置されず、且つ該基板の側壁を覆う絶縁薄膜パターンと、
を含み、
該半導体チップは、該ダイ固定領域上に取り付けられ、且つ該導電薄膜パターンと電気接続され、前記基板上に複数の貫通孔を設置し、この貫通孔は、該基板を貫通し、且つ異なる導電領域上に位置し、且つ該貫通孔の孔壁上に該導電薄膜を分布するパッケージ基板。 - 前記半導体チップが発光ダイオードであり、該導電領域は、第1導電領域及び第2導電領域を含み、該導電薄膜パターンは、第1導電薄膜パターン及び第2導電薄膜パターンを含み、該第1導電薄膜パターン及び該第2導電薄膜パターンは、それぞれ該第1導電領域及び該第2導電領域上にそれぞれ位置し、且つ該第1導電薄膜パターン及び該第2導電薄膜パターンは、相互に接触せず、該半導体チップのうち1つの電極は、該第2導電薄膜パターンと電気接続し、該半導体チップのもう1つの電極は、該第1導電薄膜パターンと電気接続する請求項1に記載のパッケージ基板。
- 前記導電薄膜パターンは、第3導電薄膜パターンを含み、該第3導電薄膜パターンは、該ダイ固定領域上に位置し、且つ該第3導電パターンは、該基板と直接接触する請求項2に記載のパッケージ基板。
- 前記第3導電薄膜パターンは、該第2導電薄膜パターンと電気接続し、且つ該半導体チップのうちの1つの電極は、該第3導電薄膜パターンと直接接触し、該半導体チップのもう1つの電極は、第1接続線により該第1導電薄膜パターンと接触する請求項3に記載のパッケージ基板。
- 前記基板の材質は、銅又はアルミニウム又は以上の何れか1つの成分を含む合金である請求項1又は2に記載のパッケージ基板。
- 前記導電薄膜パターンの材質が主に銅、ニッケル、金、銀、又は以上の何れか1つの成分を含む合金を含む請求項1又は2に記載のパッケージ基板。
- 前記絶縁薄膜パターンが重合物である請求項1又は2に記載のパッケージ基板。
- 前記絶縁薄膜パターンの材質がエポキシ樹脂、シリコンゲル、ポリイミド、又ははんだ塗料である請求項7に記載のパッケージ基板。
- 前記絶縁薄膜パターンの厚さが2μmより大きい請求項1又は2に記載のパッケージ基板。
- 前記パッケージ基板は、表面実装技術を利用し、回路基板と電気接続する請求項1又は2に記載のパッケージ基板。
- 前記半導体チップ上に第1接続線及び第2接続線を接続し、該第1接続線は、該第1導電層パターン及び該半導体チップの間に接続され、該第2接続線は、該第2導電層パターン及び該半導体チップの間に接続される請求項2に記載のパッケージ基板。
- 回路基板上に取り付けられるパッケージ基板であって、該パッケージ基板上に少なくとも1つの半導体チップを取り付け、該パッケージ基板は、
導電材質又は半導体材質から構成され、表面にダイ固定領域及び複数の導電領域を含む基板と、
それぞれ異なる導電領域に分布する複数の導電薄膜パターンと、
該導電薄膜パターンと該基板との間に位置するが、該ダイ固定領域には設置されない絶縁薄膜パターンと、
を含み、該半導体チップは、該ダイ固定領域上に取り付けられ、且つ該導電薄膜パターンと電気接続され、
前記半導体チップが発光ダイオードであり、該導電領域は、第1導電領域及び第2導電領域を含み、該導電薄膜パターンは、第1導電薄膜パターン及び第2導電薄膜パターンを含み、該第1導電薄膜パターン及び該第2導電薄膜パターンは、それぞれ該第1導電領域及び該第2導電領域上にそれぞれ位置し、且つ該第1導電薄膜パターン及び該第2導電薄膜パターンは、相互に接触せず、
更に、第3接続線及び第4接続線を含み、該第3接続線は、該第1導電層パターン及び該回路基板の間に接続され、該第4接続線は、該第2導電層パターン及び該回路基板の間に接続されるパッケージ基板。 - 該基板の側壁上に該導電薄膜を分布する請求項1又は2に記載のパッケージ基板。
- (a)基板を提供し、該基板は、主に導電材質から構成され、該基板の表面は、ダイ固定領域及び複数の導電領域に分けられ、且つ前記基板には、更に、凹穴及び複数の貫通孔を含み、該凹穴は、該ダイ固定領域に位置し、且つ該基板上に一体に成形され、且つ該半導体チップは、該凹穴内に位置し、前記貫通孔は、該基板を貫通し、且つ異なる導電領域上にそれぞれ位置し、且つ該貫通孔の孔壁上に該導電薄膜を分布し、
(b)該基板上に絶縁薄膜パターンを形成し、該絶縁薄膜パターンは、該基板の側壁を覆い、該絶縁薄膜パターンは、該ダイ固定領域上に形成されず、
(c)複数の導電薄膜パターンを形成し、これら導電薄膜パターンは、異なる導電領域上に分布され、
(d)半導体チップを該ダイ固定領域内に取り付けられ、
(e)該半導体チップを該導電薄膜パターンと電気接続する、
ことを含むパッケージ基板の製造方法。 - 前記ステップ(b)において、該絶縁薄膜パターンは、電気メッキ、電気泳動、又は電気化学蒸着を利用し、該基板上に形成される請求項14に記載のパッケージ基板の製造方法。
- 前記導電領域は、第1導電領域及び第2導電領域を含み、該導電薄膜パターンは、第1導電薄膜及び第2導電薄膜パターンを含み、該第1導電薄膜パターン及び該第2導電薄膜パターンは、それぞれ該第1導電領域及び該第2導電領域上に分布され、該半導体チップは、発光ダイオードである請求項14に記載のパッケージ基板の製造方法。
- 前記(d)のステップの前に、更に下記のステップ:
第3導電薄膜パターンを該ダイ固定領域に形成する、を含む請求項16に記載のパッケージ基板の製造方法。 - 前記(c)のステップ中に更に以下のステップ:
(c1)シード層を形成し、
(c2)該シード層を基底とし、電気メッキ又は電気泳動を利用し、導電薄膜パターンを形成する、
を含む請求項14〜16の何れか1項に記載のパッケージ基板の製造方法。 - 前記(c1)のステップに置いて、該シード層は、浸せきメッキ法又はスパッタリング法で形成される請求項17に記載のパッケージ基板の製造方法。
- 前記基板の材質が銅又はアルミニウム又は以上の何れか1つの成分を含む合金である請求項14〜16の何れか1項に記載のパッケージ基板の製造方法。
- 前記導電薄膜パターンの材質が銅、ニッケル、金、又は銀又は以上の何れか1つの成分を含む合金である請求項14〜16の何れか1項に記載のパッケージ基板の製造方法。
- 前記絶縁薄膜パターンの材質が重合物である請求項14〜16の何れか1項に記載のパッケージ基板の製造方法。
- 前記絶縁薄膜パターンの材質がエポキシ樹脂、シリコンゲル、ポリイミド、又ははんだ塗料である請求項21に記載のパッケージ基板の製造方法。
- 前記絶縁薄膜パターンの厚さが2μmより大きい請求項14〜16の何れか1項に記載のパッケージ基板の製造方法。
- 前記(b)のステップにおいて、前記絶縁薄膜パターンを形成する方法は、印刷塗布法、スパッタリング法、又は噴霧法を含む請求項14に記載のパッケージ基板の製造方法。
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