201218338 六、發明說明： 【發明所屬之技術領域】 本發明是關於一種封裝板與其製造方法，且特別是一種用於 半導體封裝的封裝板與其製造方法。 【先前技術】 隨著技術發展的日新月異，半導體的應用領域愈來愈廣，除 了邏輯運算（如：CPU)與資料儲存（如：DRAM)外，發光二 極體（Light Emitting Diode，俗稱：LED)的應用也愈來愈普遍。 然而，隨著半導體的功效愈來愈強大，其發熱量也隨之增加，故 散熱技術也愈來愈重要。 就以發光二極體為例，發光二極體的發光效率與亮度已達到 可被大眾接受的水平，因此目前發光二極體已被應用在背光模 組、>又車燈頭與路燈等上。然而，隨著發光二極體之亮度的提高， 其魔大的發熱量也困擾著本領域的技術人員。若無法將熱量有效 地排除，則發光一極體之免度將會降低且使用壽命也會變短。 目前，於發光二極體裝置中，其所使用的封裝板主要可分為 四種：印刷電路板(Print Circuit Board，簡稱PCB)、金屬基印刷電 路板(Metal Core Print Circuit Board，簡稱 MCPCB)、陶瓷基板 (Ceramic Substrate)、與矽基板(Silicon Substrate)。在這四種封裝板 中以印刷電路板的成本最低’然而其散熱能力並不佳。另外，由 於技術與成本上的限制’矽基板上的絕緣薄膜往往較薄，這樣容 易造成介電崩潰(Dielectrical Breakdown)。此外，目前市面上之陶 瓷基板主要為Al2〇3基板，八丨2〇3基板的散熱能力較差。另外，同 屬於陶瓷基板的A1N基板雖然散熱能力較佳，但卻有成本較高的 缺點。 MCPCB基板雖然比PCB基板有較高的散熱能力，但在金屬 201218338 層與發光二極體晶粒之_有介電層的存在，故在散熱能力的提 升上仍是相當有限。 清參照圖1 ’圖1所緣示為習知的發光二極體裝置之侧視圖。 此發光二極體裝置励是安裝在—電路載板1〇上，發光二極體裝 置100包括一發光二極體110與一封餘1〇2，其中封裝板包 括一基板120、一反射件130與一絕緣體14〇，其中基板12〇則為 MCPCB基板。發光二極體110與反射件13〇皆設置在基板12〇上， 反射件130則構成一杯狀的凹穴132,發光二極體11〇是位於凹穴 132中。該凹穴132的壁面為光滑的反射面，可將發光二極體11〇 擊所發出的光進行反射，以增加光線的指向性。然而，由於反射件 130與基板120是屬於二個不同的個體，故隨著使用時間的增長， 反射件130與基板120間可能會產生異位或脫離的現象。 另外，發光二極體110上還連接有接線112與接線 114^其中 接線112是連接到基板120的正導電區121，而接線114則是連接 到基板120的負導電區122 ’而發光二極體11〇則是位於基板12〇 的固晶區123上’其中正導電區121、負導電區122、與固晶區123 是藉由絕緣體140而相隔離。由於絕緣體14〇是以灌膠的方式而 鲁形成於基板120的開孔中，故該開孔需具有一定的寬度大小否 則膠體便不易流入’但這樣一來除了增加基板12〇的寬度外，還 分別增加了正導電區121及負導電區122與發光二極體11〇的距 離，也因此接線112, 114的長度需較長。而且，當發光二極體裝 置1〇〇安裝到電路載板ίο上時，其也是利用打線接合(wire b〇nding) 的方式與電路載板10電性連接，這會增加發光二極體裝置1〇〇在 電路载板10上所佔據的面積。 因此，如何設計出一種用於發光二極體裝置或其他半導體裝 置的封裝板，其具有較佳的散熱效果、較長的使用壽命、且所佔 201218338 據的$較小，已成為本賴具有通常知識者值得去思 【發明内容】 主要目的在於提供—種封練及其製造方法，該封 熱效果、較長的制壽命、與所佔據的面積較 ㈣，與其他目的，本發明提供—種封裝板，此 封裝板女裝於-電路載板上，且於封裝板上安裝有至少一半導體 晶粒’該封裝板包括：—基板、多個導電薄膜圖案、與一絕緣薄 膜圖案。基板主要是由導電材質或料體材f所構成，而其表面 包括-固與多辦電區。每縛電_職是分別分佈在不 同的導電區上，而絕緣__是位於導電__與基板之 間，但絕緣薄膜®案並未設置於固晶區上。其中，半導體晶粒是 安裝於固晶區上且與導電薄膜圖案電性連接。 於上述之封裝板巾，轉體晶粒為發光二極體，而導電區則 包括-第-導電區與-第二導電區^導電薄賴案包括—第 電薄膜圖案與-第二導電薄膜_，該第—導㈣膜圖案與該第 二導電薄膜圖案是分別位於第一導電區與第二導電區上，且第一 導電薄膜圖案與第二導電薄膜圖案彼此並不相接觸。 於上述之封裝板中，於基板上設置有多個穿孔，這些穿孔是 貫穿基板且分別位於不同的導電區上，且這些穿孔的孔壁上分佈 有導電薄膜。 於上述之封裝板中’更包括-凹穴’該凹穴是位於固晶區且 是一體成形於基板上，且半導體晶粒是位於凹穴内。 於上述之封裝板中，導電薄膜圖案更包括一第三導電薄膜圖 案，第二導電薄膜圖案是塗佈在固晶區，且第三導電薄膜圖案是 直接與基板相接觸。此外，第三導電薄膜圖案例如是與第二導= 201218338 薄臈圖案紐連接’且半導體晶粒的其中—電较與第三 ，圖案直接接觸’而半導體晶粒的另外_電_是藉由—第一接 線而與第一導電薄膜圖案相接觸。 —於上述之封裝板中，基板的材質為銅或紹，或含銅與紹之任 了成份的合金^者也可為半導體材f，例如：^另外，導電 薄膜圖案的材質主要為銅，但也可包括其他的材質，例如：錄、 金、或銀，或者是含以上任一成份的合金。 ’、 於上述之封裝板中，絕緣薄膜圖案的材質為聚合物，此聚合 #物例如為環氧樹脂狗㈣、石夕膠(驗㈣、聚亞酿胺(P〇lyimide)、 或防銲漆等’且其厚度較佳是大於2//m。 上述之封裝板中，該封裝板例如是利用表面黏著技術與母板 進行電性連接。 … &根據上述目的與其他目的，本發明提供一種封裝板的製 造方法，該製造方法包括以下⑻〜(e)所述之步驟： (a)提供一基板，該基板主要是由導電材質或半導體材質所構 成。而且，基板上具有多個穿孔，且基板被分成一固晶區與多個 導電區。 ~ 鲁 （b)於基板上形成一絕緣薄膜圖案’該絕緣薄膜圖案未形成於 固曰日區上’此絕緣薄膜圖案是利用電鑛法如卩仍出⑽）、 電泳法(Electrophoretic deposition)、或電化學沈積法(Electrical Chemical Deposition)而形成於基板上。 (c)形成多個導電薄膜圖案，這些導電薄膜圖案是分佈在不同 的導電區上。 (Φ安裝一半導體晶粒於固晶區内。 (e)使半導體晶粒與導電薄膜圖案電性連接。 由於封裝板的固晶區未塗佈有絕緣薄膜圖案，故藉由封裝板 201218338 可增加半導體封裝結構的散熱效果。 【實施方式】 為讓本發明之上述目的、特徵和優點更能明顯易懂，下 文將以實施例並配合所附圖式，作詳細說明如下。 凊參照圖2A〜圖2E，圖2A〜圖2E所繪示為本發明之發光二 極體裝置的製造方法之實施例。首先，如圖2A所示，提供一基板 220，此基板220的材質為銅。於基板220上設置有一凹穴221與 多個穿孔222 (於本實施例中為二個），其中凹穴221是一體成型 於基板220上，且穿孔222是貫穿基板22〇。此外，基板22〇的表 面被分成一固晶區223、一第一導電區224、與一第二導電區225， 其中凹穴221是位於固晶區223，而二個穿孔222則分別位°^第一 導電區224與第二導電區225。關於固晶區223、第一導電區224、 與第二導電區225如何劃分’於下文中將有較詳細的說明。 冉來，如圖2B所示，利用電鍵法、電泳法、或電化學沈積法 於基板220上形成有一絕緣薄膜圖案24〇。其中，基板22〇的固晶 區223並未被絕緣薄膜圖案240所覆蓋。所謂電鍍法、電泳法曰、曰 或電化學沈積法是指在基板220上施加一電壓，讓基板22〇本 帶有正電或負電’而使帶有相反電荷的粒子或離子^積於基板22〇 上。由於紐賴法是本賴具錢常知識麵孰悉 術，故在此便不再詳述。她於習知的濺鑛、陽極氧化、^ 化法、’本實施例之製造方法所採用之f鍍法、電泳法、或電p 沈積法具有較高的成形速率，故能於較短的時間内形 : 的絕緣薄麵# 240。在本實施例中，絕緣薄膜圖案24()的^声， 大於’較細是大於5//m。也因為絕緣薄糊案⑽= 大的厚度’故其之後在制時較不料產生介電崩潰的現象。 接著’如圖2C所示，於基板220上形成導電薄膜圖案2°3〇， 201218338 其中導電細®^23G包括第—導電薄糊案23卜一第二導 電薄膜圖案232、與一第三導電薄膜圖案233。其中，第一導電薄 膜圖案231與第二導電薄麵案232是分別塗飾在基板22〇的第 曰導電區224與第一導電區225 _L ’而第三導電薄膜圖案如則 是塗佈在固晶區223。由目I可知，第一導電薄麵案231與第 一導電薄膜圖案232是覆蓋在絕緣薄臈圖案24〇上。而且，第一 導電薄膜圖案23卜第二導電薄膜圖案232、與第三導電薄膜圖案 233並不互相接觸。如此一來’便完成封裝板2〇2的製作。 請同時參照目2A與圖2C，本賴具有通常知識者應可了解， ，板220上的第-導電區224是指被第一導電薄顚案231所覆 蓋的區域’而基板22G上的第二導電區225則是指被第二導電薄 膜圖案232所覆蓋的區域，而固晶區223則是位於第一導電區故 與第-導電區225之間。而且’在本實施例中，固晶區223上未 塗佈有絕緣薄膜圖案240。 再來’請參照圖2D，將一發光二極體21〇安裝於凹穴221内， 此發光二極體210為發光二極體(Light Emitting Diode)。之後，連 接第接線211於發光二極體210與第一導電薄膜圖案231間， 同時也連接一第二接線212於發光二極體21〇與第二導電薄膜圖 案f2間。此外，於發光二極體210上還塗佈有一螢光粉層260。 接著’請參照圖2E，將透鏡270安裝在發光二極體210上方，此 透鏡270疋藉由注膠成型的方式所製成。如此一來，便完成了發 光二極體裝置200的製作。 枝接下來’將對絕緣薄膜圖案24〇的形成方式作較詳細的介紹。 j照圖3A〜圖3C’圖3A〜圖3C所繪示為絕緣薄膜圖案的形成 過&。首先’請參照圖3A，利用電鍍法、電泳法、或電化學沈積 去於基板220上形成一絕緣薄膜24〇，，在本實施例中，絕緣薄膜 201218338201218338 VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a package board and a method of fabricating the same, and more particularly to a package board for a semiconductor package and a method of fabricating the same. [Prior Art] With the rapid development of technology, the application fields of semiconductors are becoming more and more extensive. In addition to logic operations (such as CPU) and data storage (such as DRAM), Light Emitting Diode (commonly known as LED) The application is also becoming more and more common. However, as semiconductors become more powerful and their heat generation increases, heat dissipation technology is becoming more and more important. Taking the light-emitting diode as an example, the luminous efficiency and brightness of the light-emitting diode have reached a level acceptable to the public. Therefore, the current light-emitting diode has been applied to the backlight module, > the lamp head and the street lamp, and the like. on. However, as the brightness of the light-emitting diode increases, its large heat generation also plagues those skilled in the art. If the heat cannot be effectively removed, the immunity of the light-emitting body will be reduced and the service life will be shortened. At present, in the light-emitting diode device, the package boards used can be mainly divided into four types: a printed circuit board (PCB), and a metal-based printed circuit board (MCPCB). , ceramic substrate (Ceramic Substrate), and silicon substrate (Silicon Substrate). The cost of printed circuit boards is lowest in these four package boards' however, their heat dissipation capability is not good. In addition, due to technical and cost constraints, the insulating film on the substrate tends to be thin, which easily causes Dielectrical Breakdown. In addition, the ceramic substrates currently on the market are mainly Al2〇3 substrates, and the heat dissipation capability of the eight-inch 2〇3 substrate is poor. In addition, the A1N substrate, which is also a ceramic substrate, has a heat dissipation capability, but has a disadvantage of high cost. Although the MCPCB substrate has a higher heat dissipation capability than the PCB substrate, there is a dielectric layer in the metal layer of the 201218338 layer and the light-emitting diode die, so the heat dissipation capability is still quite limited. 1 is a side view of a conventional light-emitting diode device as shown in FIG. The light-emitting diode device is mounted on the circuit carrier board 1 , and the light-emitting diode device 100 includes a light-emitting diode 110 and a drain 1 , wherein the package board includes a substrate 120 and a reflector. 130 and an insulator 14, wherein the substrate 12 is an MCPCB substrate. The light-emitting diode 110 and the reflecting member 13 are all disposed on the substrate 12, and the reflecting member 130 constitutes a cup-shaped recess 132, and the light-emitting diode 11 is located in the recess 132. The wall surface of the recess 132 is a smooth reflecting surface for reflecting the light emitted by the illuminating diode 11 to increase the directivity of the light. However, since the reflector 130 and the substrate 120 belong to two different individuals, the use of the time may increase, and the phenomenon of ectopic or detachment between the reflector 130 and the substrate 120 may occur. In addition, the light emitting diode 110 is further connected with a wiring 112 and a wiring 114. The wiring 112 is connected to the positive conductive region 121 of the substrate 120, and the wiring 114 is connected to the negative conductive region 122' of the substrate 120 and the light emitting diode The body 11 is located on the solid crystal region 123 of the substrate 12', wherein the positive conductive region 121, the negative conductive region 122, and the solid crystal region 123 are isolated by the insulator 140. Since the insulator 14 is formed in the opening of the substrate 120 by means of glue filling, the opening needs to have a certain width or the colloid is not easy to flow in. However, in addition to increasing the width of the substrate 12, The distance between the positive conductive region 121 and the negative conductive region 122 and the light emitting diode 11A is also increased, and thus the lengths of the wires 112, 114 need to be long. Moreover, when the light emitting diode device 1 is mounted on the circuit carrier ίο, it is also electrically connected to the circuit carrier 10 by means of wire bonding, which increases the light emitting diode device 1 The area occupied by the circuit board 10 . Therefore, how to design a package board for a light-emitting diode device or other semiconductor device, which has better heat dissipation effect, long service life, and a smaller amount of 201218338, has become a Usually the knowledge is worth thinking about [invention] The main purpose is to provide a kind of sealing and its manufacturing method, the heat sealing effect, the long life, and the occupied area (four), and other purposes, the present invention provides - A package board, the package board is mounted on a circuit carrier board, and at least one semiconductor die is mounted on the package board. The package board comprises: a substrate, a plurality of conductive film patterns, and an insulating film pattern. The substrate is mainly composed of a conductive material or a material body f, and the surface thereof includes a solid-state and a plurality of electrical regions. Each of the wires is distributed on a different conductive area, and the insulation __ is located between the conductive __ and the substrate, but the insulating film® case is not disposed on the solid crystal region. The semiconductor die is mounted on the die bonding region and electrically connected to the conductive film pattern. In the above packaged board towel, the rotating die is a light emitting diode, and the conductive region includes a -first conductive region and a second conductive region. The conductive thin film includes a first electric film pattern and a second conductive film. _, the first (four) film pattern and the second conductive film pattern are respectively located on the first conductive region and the second conductive region, and the first conductive film pattern and the second conductive film pattern are not in contact with each other. In the above package board, a plurality of through holes are formed on the substrate, and the through holes are penetrated through the substrate and respectively located on different conductive regions, and the conductive film is distributed on the holes of the holes. In the package board described above, the recess further comprises a recess which is located in the die bond region and is integrally formed on the substrate, and the semiconductor die is located in the recess. In the above package board, the conductive film pattern further includes a third conductive film pattern, the second conductive film pattern is coated on the die bonding region, and the third conductive film pattern is directly in contact with the substrate. In addition, the third conductive thin film pattern is, for example, connected to the second conductive layer = 201218338 thin germanium pattern and the semiconductor crystal grain is electrically connected to the third, the pattern is in direct contact with the semiconductor wafer die. - the first wiring is in contact with the first conductive film pattern. - In the above-mentioned package board, the material of the substrate is copper or sinter, or the alloy containing copper and sinter can also be a semiconductor material f, for example: ^ In addition, the material of the conductive film pattern is mainly copper. However, other materials may be included, such as: gold, silver, or silver, or alloys containing any of the above ingredients. In the above package board, the material of the insulating film pattern is a polymer, and the polymer material is, for example, an epoxy resin dog (four), a stone enamel gel (test (4), poly styrene (P〇lyimide), or solder resist. The lacquer or the like 'and the thickness thereof is preferably more than 2 / / m. In the above package board, the package board is electrically connected to the mother board by, for example, surface adhesion technology. & A method of manufacturing a package board comprising the steps of (8) to (e): (a) providing a substrate mainly composed of a conductive material or a semiconductor material, and having a plurality of substrates thereon Perforation, and the substrate is divided into a solid crystal region and a plurality of conductive regions. ~ Lu (b) forming an insulating film pattern on the substrate 'The insulating film pattern is not formed on the solid day zone' The ore method is formed on the substrate by (10)), electrophoretic (Electrophoretic deposition), or electrochemical deposition (Electrical Chemical Deposition). (c) forming a plurality of conductive film patterns which are distributed over different conductive regions. (Φ) mounting a semiconductor die in the die-bonding region. (e) electrically connecting the semiconductor die to the conductive film pattern. Since the die-bonding region of the package board is not coated with the insulating film pattern, the package board 201218338 can be used. The above-mentioned objects, features, and advantages of the present invention will become more apparent from the following description of the embodiments of the invention. 2E, FIG. 2A to FIG. 2E illustrate an embodiment of a method for fabricating a light-emitting diode device according to the present invention. First, as shown in FIG. 2A, a substrate 220 is provided, which is made of copper. The substrate 220 is provided with a recess 221 and a plurality of through holes 222 (two in this embodiment), wherein the recess 221 is integrally formed on the substrate 220, and the through hole 222 is penetrated through the substrate 22. Further, the substrate 22〇 The surface is divided into a solid crystal region 223, a first conductive region 224, and a second conductive region 225, wherein the recess 221 is located in the solid crystal region 223, and the two through holes 222 are respectively located in the first conductive region. 224 and second conductive region 225. The crystal region 223, the first conductive region 224, and the second conductive region 225 are divided into 'described in more detail below. Hereinafter, as shown in FIG. 2B, using an electric bond method, an electrophoresis method, or an electrochemical deposition method. An insulating film pattern 24 is formed on the substrate 220. The solid crystal region 223 of the substrate 22 is not covered by the insulating film pattern 240. The electroplating method, the electrophoresis method, the germanium or the electrochemical deposition method refers to the substrate. A voltage is applied to 220 to cause the substrate 22 to be positively or negatively charged, and the oppositely charged particles or ions are accumulated on the substrate 22. As the New Zealand method is known to Therefore, it will not be described in detail here. She has a f-plating method, an electrophoresis method, or an electric p-deposition method which is used in the conventional method of sputtering, anodizing, chemical conversion, and the manufacturing method of the present embodiment. The high forming rate can be formed in a shorter time: the insulating thin surface #240. In the present embodiment, the insulating film pattern 24() has a sound greater than 'thinness is greater than 5//m. Because the insulating thin paste case (10) = large thickness, it is less likely to cause dielectric collapse later. Then, as shown in FIG. 2C, a conductive thin film pattern is formed on the substrate 220 by 2° 3 〇, 201218338, wherein the conductive thin film ^^23G includes a first conductive thin paste case 23 and a second conductive thin film pattern 232, and one The third conductive film pattern 233, wherein the first conductive thin film pattern 231 and the second conductive thin surface case 232 are respectively printed on the second conductive region 224 of the substrate 22 and the first conductive region 225 _L ' and the third conductive film pattern For example, it is coated on the solid crystal region 223. As can be seen from the above, the first conductive thin film 231 and the first conductive thin film pattern 232 are overlaid on the insulating thin pattern 24 。. Moreover, the first conductive thin film pattern 23 The second conductive film pattern 232 and the third conductive film pattern 233 are not in contact with each other. In this way, the fabrication of the package board 2〇2 is completed. Please refer to both FIG. 2A and FIG. 2C. It should be understood by those having ordinary knowledge that the first conductive region 224 on the board 220 refers to the region covered by the first conductive thin film 231 and the first on the substrate 22G. The second conductive region 225 refers to a region covered by the second conductive thin film pattern 232, and the solid crystal region 223 is located between the first conductive region and the first conductive region 225. Further, in the present embodiment, the insulating film pattern 240 is not coated on the solid crystal region 223. Referring to FIG. 2D, a light-emitting diode 21 is mounted in the cavity 221, and the light-emitting diode 210 is a Light Emitting Diode. Then, the second wiring 212 is connected between the LED 210 and the first conductive film pattern 231, and a second wiring 212 is connected between the LED 21 and the second conductive film pattern f2. In addition, a phosphor layer 260 is further coated on the LED 210. Next, referring to Fig. 2E, the lens 270 is mounted above the light-emitting diode 210, and the lens 270 is formed by injection molding. In this way, the fabrication of the light-emitting diode device 200 is completed. The branch next will describe the formation of the insulating film pattern 24A in more detail. 3A to 3C', FIG. 3A to FIG. 3C show the formation of an insulating film pattern. First, referring to FIG. 3A, an insulating film 24 is formed on the substrate 220 by electroplating, electrophoresis, or electrochemical deposition. In the present embodiment, the insulating film 201218338
2=〇’ =質為聚合物，例如為環氧樹脂，、聚亞酿胺、或防鲜 漆。接者’凊參照圖3B，於絕緣薄膜24〇,上塗佈一光阻層5〇 中於固:日區223上的絕緣薄膜24。’並未被光阻層50所覆蓋。之 後進行姓刻的製程，將未被光阻層5〇覆蓋的絕緣薄膜搬清除。 再來二圖3C所示，將光阻層5〇除去，便形成絕緣薄膜圖案跡 J者二也可如圖4A〜圖4C所示，先於*欲形成絕緣薄膜圖案 ’一 圖4A中為固晶區223)形成光阻層50。之後如圖4B 所不:利用電鑛法、電泳法、或電化學沈積法於基板上進行 絕緣薄膜240,的沉積，由於絕緣薄膜，不會形成在光阻層刈 上，故將光阻層50除去後，便形成絕緣薄膜 所示）。 m 以下，將對導電薄膜圖案23〇的製造過程作較詳細地介紹。 請f照圖5A〜圖5D，圖5A〜圖犯靖示為導電薄膜圖案的製造 過程。首先’如圖5A所示’於基板22〇上形成一晶種層23〇”， 此晶種層23〇”的材質為銅，其分佈在整個基板2如上且覆蓋整個 絕緣薄膜職240。於本實_巾，是_魏却__ p 或賴法而形成晶種層23G”，此晶種層縱，的材質例如為銅。再 來，如圖5B所示，於晶種層23〇，，上塗佈一光阻層5〇，，其中 分的晶種層230”未被光阻層5〇，所覆蓋。之後，進行飯刻的°， 將未被光阻層50,輕的晶_现”清除，便軸蝴冗所示之 晶種層圖案230,。將光阻層5〇,去除後，便可利用電餘、電泳法、 或電化學沈積法，於晶種層_ 23G，上繼續進行銅軌積，以形 成如圖SD所示之導電薄膜圖案23〇。另外，本領域具有通常知識 者，也可於沉義後，科_其__金屬，如：錦、金、2 = 〇' = the mass is a polymer, such as an epoxy resin, a poly-branched amine, or a varnish. Referring to Fig. 3B, an insulating film 24 on the solid: day region 223 is coated on the insulating film 24A. ' is not covered by the photoresist layer 50. Thereafter, the process of surname engraving is carried out to remove the insulating film not covered by the photoresist layer 5〇. Further, as shown in FIG. 3C, the photoresist layer 5 is removed, and the insulating film pattern trace J is formed. As shown in FIG. 4A to FIG. 4C, the pattern of the insulating film is formed prior to FIG. 4A. The solid crystal region 223) forms the photoresist layer 50. Then, as shown in FIG. 4B, the deposition of the insulating film 240 on the substrate by electro-minening, electrophoresis, or electrochemical deposition is not formed on the photoresist layer due to the insulating film, so the photoresist layer is formed. After 50 is removed, an insulating film is formed). m Hereinafter, the manufacturing process of the conductive thin film pattern 23A will be described in more detail. Please refer to FIG. 5A to FIG. 5D, and FIG. 5A to FIG. 5A show the manufacturing process of the conductive film pattern. First, as shown in Fig. 5A, a seed layer 23"" is formed on the substrate 22, and the material of the seed layer 23" is copper, which is distributed over the entire substrate 2 as above and covers the entire insulating film 240. In the present invention, the seed layer 23G is formed by the _Wei __ p or the Lai method, and the material of the seed layer is, for example, copper. Further, as shown in FIG. 5B, in the seed layer 23 Then, a photoresist layer 5 is coated thereon, and the seed crystal layer 230" is not covered by the photoresist layer 5. After that, the rice is cut, the photoresist layer 50 is removed, and the light crystal layer pattern 230 is removed. The photoresist layer 5 is removed and removed. The copper track product is continued on the seed layer _ 23G by means of a power reserve, an electrophoresis method, or an electrochemical deposition method to form a conductive thin film pattern 23 如图 as shown in FIG. SD. Further, those having ordinary knowledge in the art, Can also be after Shen Yi, Branch _ its __ metal, such as: Jin, Jin,
和銀或含以上任-成分之合金等，明進導電薄_案Μ 理性質。 J 201218338 徐-ft導電薄膜圖案230的形成方式也不限於圖5A〜圖5£)所 電^獅ί過程。請參照圖6A〜圖6D ’圖6A〜圖6D所緣示為導 ，=圖案的另—種製造過程。首先’如圖认所示，於基板22〇 23G” ’此晶_⑽’㈣質為鋼，其覆蓋整舰 =圖：24〇。再來’如圖6B所示’於晶種層23〇”上塗佈一光 t部*的晶種層23〇，，未被光阻層5()’所覆蓋。之後， 1電錄法或電泳法，於未被光阻層5 =銅及其他麵金屬(如:錄和金)的沉積，使；增厚上 份即為導電薄關案23G。接著，將光阻層训去除後，And silver or an alloy containing the above-mentioned components, etc., and the conductivity is thin. J 201218338 The formation manner of the Xu-ft conductive film pattern 230 is not limited to the process of the electric lion ί of FIG. 5A to FIG. Please refer to FIG. 6A to FIG. 6D'. FIG. 6A to FIG. 6D show another manufacturing process of the pattern and the pattern. First, as shown in the figure, on the substrate 22〇23G” 'this crystal_(10)' (four) is made of steel, which covers the whole ship=图:24〇. Then 'as shown in Fig. 6B' on the seed layer 23〇 The seed layer 23〇 coated with a light t portion* is not covered by the photoresist layer 5()'. After that, 1 electro-acoustic method or electrophoresis method is not deposited by the photoresist layer 5 = copper and other surface metals (such as recording and gold); the thicker upper part is the conductive thin film 23G. Then, after removing the photoresist layer,
Ϊ了ίΓ刻製程，以將殘餘的晶種層23〇”移除，便形成如圖6D 所不的導電薄膜圖案230。 U 按昭= ’圖5A〜圖5D與圖6A〜圖6D皆僅是示意，並未 行繪製’例如導電薄膜圖案230實際上就比 圖荦Li)，j0或晶種層230”還要厚上許多。一般來說，晶種層 士二in $晶種層230”是小於1/Zm，而導電薄膜圖案230則是 古il、此外’本領域具有通常知識者也可於晶種層23〇”上 、電泳、或f化學沈積的方式形成—導膜，之後 230;。/膜上塗佈光阻層並進雜刻，以形成導電薄膜圖案 你丨夕圖_1顿圖7BWf示為本發明之發光二極體裝置的第-實施 射:’圖7A所緣示為剖面圖，圖7精繪示為上視圖。此 ^先j體裝置是藉_ 2A〜圖2D靖補製造方法所製 Ϊ齡^安裝在—電路載板2G上。此電路載板2G例如為印刷 άτ，祐甘；電路載板2〇上除了安裝有發光二極體裝置200外，還 ;〇Γ。、他的電子零件（未料），或安裝更多的發光二極體裝置 201218338 由圖7A可知’發光二極體210的正下方並未塗佈任何的絕緣 薄膜圖案240，由於第三導電薄膜圖案233為銅、鎳、金、或銀等 金屬所構成，而基板220的材質為銅，故發光二極體210所產生 的熱量可輕易地由第三導電薄膜圖案233與基板220傳導出去， 而使發光二極體210較不會有過熱的情形產生。另外，塗佈於發 光二極體210上的螢光粉層260則是用於控制發光二極體裝置2〇〇 所發出的色光，例如當發光二極體210所發出的光為藍光，而螢 光粉層260是由黃色螢光粉所製成，則發光二極體裝置200即可 產生出白光。 由於凹穴221是一體成型在基板220上，故不會發生如圖1 魯 之發光二極體裝置100所會產生的問題，即：當使用時間增長後， 反射件130與基板120間可能會產生脫離的現象。因此，相較於 發光二極體裝置1〇〇，發光二極體裝置2〇〇可具有較長的使用壽 命。此外，凹穴221的孔壁上塗佈有第三導電薄膜圖案233，其表 面具有反射的效果，故發光二極體21〇所發出的光線會被其反射， 且透鏡270也具有聚光的作用，這些都能使發光二極體裝置2〇〇 的發光品質提高。 請參照圖1、圖7A及圖7B，由於在封裝板202上無需如封鲁 裝板102般設置絕緣體HO，故其基板220的面積較小，且第一接 線211及第二接線212的長度會比接線112與接線114還要短， 故發光二極體裝置200可有較小的面積。此外，封裝板1〇2是利 用打線接合的方式與電路載板1G相連接，而封裝板2G2則是利用 表面黏著技術(surface mount technology)與電路載板20電性連接， 因此比較圖1與圖7八可清楚地看出：發光二極體裝置2〇〇於電路 載板20上所佔據的面積會小於發光二極體裝置]〇〇於電路載板⑴ 上所佔據的面積。也a為發光二極體裝置於電路載板2〇上所 12 201218338 佔據的面積較小，故於電路載板20上可安裝更多其他的電子零 或更多的發光二極體裝置200。After the etching process is performed to remove the remaining seed layer 23", a conductive film pattern 230 as shown in FIG. 6D is formed. U Pressing FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6D are only It is indicated that the drawing "for example, the conductive film pattern 230 is actually larger than the pattern Li", and the j0 or the seed layer 230" is much thicker. In general, the seed layer 2 in $ seed layer 230" is less than 1 / Zm, and the conductive film pattern 230 is ancient il, in addition, 'the general knowledge in the field can also be on the seed layer 23 〇" , electrophoresis, or f chemical deposition to form a film, followed by 230; / coating the photoresist layer on the film and engraving to form a conductive film pattern. Figure 7BWf shows the first implementation of the light-emitting diode device of the present invention: 'Figure 7A shows the profile Figure 7, Figure 7 is shown in a top view. This first-stage j-body device is mounted on the circuit carrier board 2G by the _ 2A~ Figure 2D Jingbu manufacturing method. The circuit carrier 2G is, for example, a printed άτ, 佑甘; the circuit carrier 2 is mounted on the circuit board 2 in addition to the light-emitting diode device 200; , his electronic parts (unexpected), or install more light-emitting diode devices 201218338. As can be seen from FIG. 7A, 'the insulating film pattern 240 is not coated directly under the light-emitting diode 210, because the third conductive film The pattern 233 is made of a metal such as copper, nickel, gold, or silver, and the material of the substrate 220 is copper. Therefore, the heat generated by the light-emitting diode 210 can be easily conducted from the third conductive film pattern 233 and the substrate 220. The light-emitting diode 210 is less likely to be overheated. In addition, the phosphor layer 260 coated on the LED 210 is used to control the color light emitted by the LED device 2, for example, when the light emitted by the LED 210 is blue light, The phosphor layer 260 is made of yellow phosphor, and the light-emitting diode device 200 can generate white light. Since the recess 221 is integrally formed on the substrate 220, the problem that occurs in the LED device 100 as shown in FIG. 1 does not occur, that is, after the use time increases, the reflector 130 and the substrate 120 may Produce a phenomenon of detachment. Therefore, the light-emitting diode device 2 can have a longer service life than the light-emitting diode device. In addition, the wall of the hole of the recess 221 is coated with a third conductive film pattern 233, the surface of which has a reflective effect, so that the light emitted by the light-emitting diode 21 is reflected by the light, and the lens 270 also has a concentrated light. In effect, these can improve the light-emitting quality of the light-emitting diode device 2〇〇. Referring to FIG. 1 , FIG. 7A and FIG. 7B , since the insulator HO is not required to be disposed on the package board 202 as the seal plate 102 , the area of the substrate 220 is small, and the lengths of the first wire 211 and the second wire 212 are long. It will be shorter than the wiring 112 and the wiring 114, so the light-emitting diode device 200 can have a small area. In addition, the package board 1〇2 is connected to the circuit carrier 1G by means of wire bonding, and the package board 2G2 is electrically connected to the circuit carrier 20 by surface mount technology, thus comparing FIG. 1 with FIG. As can be clearly seen in Fig. 7-8, the area occupied by the LED device 2 on the circuit carrier 20 is smaller than the area occupied by the LED device (1). Also, a is a light-emitting diode device on the circuit board 2 12 201218338 occupies a small area, so more electronic zero or more light-emitting diode devices 200 can be mounted on the circuit carrier 20.
在上述的實施例中，固晶區223是位於基板220表面的中央 處，但本領域具有通常知識者應可明白固晶區223並不限設置在 中央處。另外，基板220的材質為銅，但本領域具有常 也可以使用其他的材質製作基板220，例如鋁，或含銅與鋁之任一 成份的合金。此外，基板220的材質也可為半導體材質，例如矽， 要使基板220具有導電的性質即可。此外，固晶區us上也 不需設置凹穴221，而呈一平面狀。 請參照圖8A ’圖8A所繪示為本發明之發光二極體裝置的第 二實施例之示意圖。相較於圖7A之發光二極體裝置2〇〇,圖8a之 發光二極體裝置2GG，並未設置第三導電薄膜_ 233，也就是 光二極體210是直接與基板220相接觸。 此外，在圖7A中，第-導電薄膜圖案23卜第二導電薄膜圖 案232、與第三導電薄膜圖案233彼此並不互相接觸，且發光二極 體2io是以打線的方式分別與第一導電薄膜圖案231及第二導電 薄膜圖案232電性連接。然而，請參照圖8B，圖8b所繪示為本 發明之縣二極體裝置的第三實_之示意圖。在本實施例中， 第二導電薄膜圖案232與第三導電薄膜圖案233是一體成形，也 就是說彼此是互相連接在—起。此外，發光二極體裝置·，，之發 光二極體21G的其中-電極（在本實施例為正極）是與第三導電 薄膜圖案直接接觸’而發光二極體21G的另外—電極^在 例為負極）則是藉由第-接線211而與第一導電薄膜圖案231相 接觸。 請參照圖9,圖9所繪示為本發日月之發光二極體裝置的第四實 “二立㈤’發光二極體裝置3〇〇的封裝板3〇2是安裝在一電 13 201218338 路載板30上。相較於圖7A，封裝板3〇2的基板31〇並未設置凹 穴221與任何穿孔222，且發光二極體裝置300更包括一第三接線 303與一第四接線3〇4。第三接線303是連接於一第一導電薄膜圖 案331與電路載板3〇之間’而第四接線3〇4則是連接於一第二導 電層圖案332與電路載板30之間。 由於於基板310上並未設置任何凹穴221與穿孔222,其表面 為一平坦的表面，故在本實施例中，除了可使用電泳法、電鍍法、 或電化學沈積法外，還可使用印刷塗佈法、濺鍍法、或噴霧法等 方式’而於基板310上形成絕緣薄膜圖案34〇及導電薄臈圖案33〇。 請參照圖10，圖10所繪示為本發明之發光二極體裝置的第 五實施例之示意圖，發光二極體裝置400的封裝板402是安裝在 電路載板20上。相較於圖7A，發光二極體裝置400的基板410 並未设置任何穿孔，其第一導電薄膜圖案431與第二導電薄膜圖 案432除了分佈於基板41〇的上表面與下表面外，還分佈在基板 410的側壁上。因此’位於基板41〇上表面的導電薄膜43〇是藉由 位於侧壁上的導電薄膜430，而與位於下表面的導電薄膜43〇相導 通在本實施例中’封裝板402是利用表面黏著技術(surface m〇unt technology)與電路載板2〇電性連接。 在上述之實施例中，所有的發光二極體裝置皆只有安裝一發 光二極體，但本領域具有通常知識者也可依情況安裝更多的發光 二極體，這些發光二極體可利用並聯的方式連接在一起。 而且，除了上述之發光二極體外，封裝板還可應用在其他半 導體封裝結構上。也就是說，於封裝板的固晶區上，除了可安裝 發光二極體外，還可安裝其他型態的半導體晶粒，例如：邏輯ic、 記憶體1C、類比1C、或CM0S影像感測元件。此外，隨著所安裝 之半導體晶粒的不同，導電薄膜圖案的個數也會不同，其主要是 201218338 數由:如接_數目若為_，則導電 ===半= 或範園内，所作之知識者’在不_本專利精神 成之箅效二’均屬於本發明所揭示精神下所完 【=^，聰訂帅糊_内 =所繪不為習知的發光二極體裝置的側視圖。 實施例。_2Ε所綠示為本發明之發光二極體裝置的製造方法之 圖3A〜圖3C所緣示為絕緣薄麵案的 ，〜圖絕緣薄膜圖案的另一種=知。 〜圖5D_示為導電薄膜圖案的其中一種製造過程。 圖〜圖6D所繪示為導電薄膜圖案的另一種製造過程。 例之圖73崎示為本發明之發光二極難置的第一實施 不思圖，圖7A所繪示為剖面圖，圖7B所繪示為上視圖。 意«圖8A所綠示為本發明之發光二極體裝置的第二實施例之示 意圖圖8B所繪示為本發明之發光二極體裝置的第三實施例之示 圖 圖9所綠示為本發明之發光二極體裝置的第四實施例之示意 圖 圖10所繪示為本發明之發光二極體裝置的第五實施例之示意 15 201218338 【主要元件符號說明】 <先前技術> ίο:母板 100 :發光二極體裝置 102 :封裝板 110 :發光二極體 112、114 :接線 120 :基板 <實施方式> 200、200’、200’ ：發光二極體 裝置 202 :封裝板 220 :基板 221 :凹穴 222 :穿孔 223 .固晶區 224 :第一導電區 225 :第二導電區 230 :導電薄膜圖案 231 :第一導電薄膜圖案 232 :第二導電薄膜圖案 233 :第三導電薄膜圖案 230’ ：晶種層圖案 230” ：晶種層 240 :絕緣薄膜圖案 240’ ：絕緣薄膜 121 :正導電區 122 :負導電區 123 ·固晶區 130 :反射件 132 :凹穴 140 :絕緣體 260 :螢光粉層 270 :透鏡 20 :電路載板 50、50’、50” ：光阻層 300 :發光二極體裝置 302 :封裝板 303 :第三接線 304 :第四接線 330 :導電薄膜圖案 340 :絕緣薄膜圖案 331 :第一導電薄膜圖案 332 :第二導電層圖案 30 :電路載板 400 :發光二極體裝置 402 :封裝板 410 :基板 430 :導電薄膜圖案In the above embodiment, the die bonding region 223 is located at the center of the surface of the substrate 220, but those skilled in the art should understand that the die bonding region 223 is not limited to being disposed at the center. Further, the material of the substrate 220 is copper. However, it is also common in the art to fabricate the substrate 220 using another material such as aluminum or an alloy containing any of copper and aluminum. In addition, the material of the substrate 220 may be a semiconductor material, such as germanium, to make the substrate 220 conductive. In addition, the solid crystal region us does not need to be provided with a recess 221, but has a flat shape. Referring to Fig. 8A, Fig. 8A is a schematic view showing a second embodiment of the light emitting diode device of the present invention. Compared with the LED device 2 of FIG. 7A, the LED device 2GG of FIG. 8a is not provided with the third conductive film _233, that is, the photodiode 210 is directly in contact with the substrate 220. In addition, in FIG. 7A, the first conductive film pattern 23, the second conductive film pattern 232, and the third conductive film pattern 233 are not in contact with each other, and the light emitting diodes 2o are respectively electrically connected to the first conductive line. The thin film pattern 231 and the second conductive thin film pattern 232 are electrically connected. However, please refer to FIG. 8B, which is a schematic diagram of the third embodiment of the county diode device of the present invention. In the present embodiment, the second conductive film pattern 232 and the third conductive film pattern 233 are integrally formed, that is, they are connected to each other. Further, in the light-emitting diode device, the -electrode (positive electrode in the present embodiment) is in direct contact with the third conductive thin film pattern, and the other electrode of the light-emitting diode 21G is For example, the negative electrode is brought into contact with the first conductive thin film pattern 231 by the first wiring 211. Referring to FIG. 9 , FIG. 9 illustrates that the package board 3〇2 of the fourth real “two vertical (five)” light-emitting diode device of the light-emitting diode device of the present invention is mounted on a battery 13 . 201218338 is mounted on the carrier board 30. Compared with FIG. 7A, the substrate 31 of the package board 3〇2 is not provided with the recess 221 and any of the through holes 222, and the LED device 300 further includes a third connection 303 and a first The fourth wiring 3〇4. The third wiring 303 is connected between a first conductive film pattern 331 and the circuit carrier 3〇', and the fourth wiring 3〇4 is connected to a second conductive layer pattern 332 and the circuit Between the plates 30. Since no recess 221 and perforations 222 are provided on the substrate 310, the surface thereof is a flat surface, so in this embodiment, in addition to electrophoresis, electroplating, or electrochemical deposition. In addition, an insulating film pattern 34 and a conductive thin pattern 33A may be formed on the substrate 310 by a printing coating method, a sputtering method, or a spray method. Referring to FIG. 10, FIG. A schematic diagram of a fifth embodiment of the light-emitting diode device of the present invention, a package board of the light-emitting diode device 400 402 is mounted on the circuit board 20. Compared to FIG. 7A, the substrate 410 of the LED device 400 is not provided with any perforations, and the first conductive film pattern 431 and the second conductive film pattern 432 are distributed on the substrate 41. The upper surface and the lower surface of the crucible are also distributed on the sidewall of the substrate 410. Therefore, the conductive film 43 located on the upper surface of the substrate 41 is electrically conductive on the lower surface by the conductive film 430 on the sidewall. The film 43 is turned on in the present embodiment. In the present embodiment, the package board 402 is electrically connected to the circuit board 2 by surface m〇unt technology. In the above embodiments, all the light emitting diode devices are used. Only one light-emitting diode is installed, but those skilled in the art can also install more light-emitting diodes according to the situation, and these light-emitting diodes can be connected in parallel. Moreover, in addition to the above-mentioned light-emitting diodes Outside the pole, the package board can also be applied to other semiconductor package structures. That is to say, in the die-bonding area of the package board, in addition to the installation of the light-emitting diode, other types can be installed. Conductor dies, such as: logic ic, memory 1C, analog 1C, or CMOS image sensing elements. In addition, the number of conductive film patterns will vary with the semiconductor die mounted, mainly 201218338 If the number is _, then the number is _, then the conduction === half = or within the Fan Park, the knowledge made by the person who does not _ the spirit of this patent becomes the second one is all under the spirit of the invention. =^, 聪订帅糊_内=A side view of a light-emitting diode device that is not conventionally known. Embodiments _2 Ε 绿 绿 为本 为本 图 图 图 图 图 图 图 图 图 图 图 图 图3C is shown as an insulating thin-film case, and another type of insulating film pattern is known. ~ Figure 5D_ shows one of the manufacturing processes for the conductive film pattern. FIG. 6D illustrates another manufacturing process of the conductive film pattern. FIG. 73 is a first embodiment of the illuminating diode of the present invention. FIG. 7A is a cross-sectional view, and FIG. 7B is a top view. Figure 8A is a schematic view showing a second embodiment of the light-emitting diode device of the present invention. Figure 8B is a diagram showing a third embodiment of the light-emitting diode device of the present invention. FIG. 10 is a schematic view showing a fifth embodiment of the light-emitting diode device of the present invention. FIG. 10 is a schematic diagram of a fifth embodiment of the light-emitting diode device of the present invention. 201218338 [Explanation of main component symbols] <Prior Art> Ίο: mother board 100: light emitting diode device 102: package board 110: light emitting diode 112, 114: wiring 120: substrate <embodiment> 200, 200', 200': light emitting diode device 202 : package board 220 : substrate 221 : recess 222 : perforation 223 . solid crystal region 224 : first conductive region 225 : second conductive region 230 : conductive thin film pattern 231 : first conductive thin film pattern 232 : second conductive thin film pattern 233 : Third conductive film pattern 230 ′: seed layer pattern 230 ”: seed layer 240 : insulating film pattern 240 ′: insulating film 121 : positive conductive region 122 : negative conductive region 123 • solid crystal region 130 : reflective member 132 : Pocket 140: Insulator 260: Fluorescent powder layer 270: transparent 20: circuit carrier 50, 50', 50": photoresist layer 300: light emitting diode device 302: package board 303: third wiring 304: fourth wiring 330: conductive film pattern 340: insulating film pattern 331: A conductive film pattern 332: a second conductive layer pattern 30: a circuit carrier 400: a light emitting diode device 402: a package board 410: a substrate 430: a conductive film pattern