CN103915394B - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
- Publication number
- CN103915394B CN103915394B CN201210593014.XA CN201210593014A CN103915394B CN 103915394 B CN103915394 B CN 103915394B CN 201210593014 A CN201210593014 A CN 201210593014A CN 103915394 B CN103915394 B CN 103915394B
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- packaging body
- semiconductor chip
- electrode structure
- conducting layer
- welding pad
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 128
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000004806 packaging method and process Methods 0.000 claims abstract description 77
- 238000003466 welding Methods 0.000 claims abstract description 56
- 238000005253 cladding Methods 0.000 claims abstract description 15
- 238000005538 encapsulation Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 13
- 230000004308 accommodation Effects 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 11
- 230000005611 electricity Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 230000001052 transient effect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Wire Bonding (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of semiconductor package and preparation method thereof, semiconductor package includes: a chip unit, an encapsulation unit and an electrode unit.Chip unit includes at least semiconductor chip, has an end face, a bottom surface and is connected between end face and bottom surface has one first conductive welding pad and one second conductive welding pad on side, and the bottom surface of semiconductor chip.Encapsulation unit includes end face and the packaging body around side of a covering semiconductor chip.One first side end and one second side end it is respectively provided with on two contrary sides of packaging body.Electrode unit includes the first electrode structure of the first side end of a cladding packaging body and the second electrode structure of the second side end of a cladding packaging body.First electrode structure and the second electrode structure preset distance separated from one another, and the first electrode structure and the second electrode structure the first conductive welding pad in electrical contact and the second conductive welding pad respectively.
Description
Technical field
The present invention relates to a kind of encapsulating structure and preparation method thereof, espespecially a kind of semiconductor package and
Its manufacture method.
Background technology
In the prior art, design one is faced directly on the two-way obstruction formula Transient Voltage Suppressor of manufacture
Facing a technical bottleneck, this technical bottleneck is exactly that the base stage of two-way obstruction formula Transient Voltage Suppressor is
It is connected to a floating-potential end.Specifically, two-way obstruction formula TVS be utilization have identical emitter-base bandgap grading-
Base stage is constituted with the symmetrical NPN/PNP framework of collector-base breakdown voltage.But, such structure
One-tenth mode often results in drift base, and then makes the change in voltage (such as dv/dt) in elapsed time
Increasingly difficult.The change in voltage in this elapsed time more causes leakage current relation, and it mainly originates from works as base
Pole is drift, and the change of voltage dv/dt will cause equal electric capacity, fills and discharge stream to produce,
In turn result in the increase of leakage current.
About Transient Voltage Suppressor (Transient Voltage Suppressor, TVS), typically should
For protecting integrated circuit, with the damage avoiding integrated circuit can cause because bearing excessive voltage
Wound.Integrated circuit is typically designed under a normal voltage range running.But, at such as static discharge
(ESD) under situation, electricity transition rapidly lightning, now cannot expect and uncontrollable height
Voltage may unexpectedly puncture circuit.This kind of damage of load excessive voltage is there is at similar integrated circuit
During situation, it is necessary to use TVS to provide protection against.When the parts number implemented in integrated circuit
When amount increases, integrated circuit will be made to be easier to cause damage, now when running into excessive voltage damage
The demand of TVS protection is the most more increased.The exemplary applications of TVS such as USB power source and data line protection,
Numeral movie news interface, Fast Ethernet network, notebook computer, display and flat-panel screens etc..
But, as a example by TVS, traditional chip package mode needs to hold via a bearing substrate
Carry functional chip, and need via routing to reach electrically connecting between functional chip and bearing substrate
Connect, thus result in that conventional package volume is excessive, cost of manufacture increases, electric current transfer rate reduces and
Interference it is easily subject to and the problem such as cause electrical property efficiency the best when being used in high frequency.
Summary of the invention
The embodiment of the present invention is to provide a kind of semiconductor package and preparation method thereof, and it can be effective
" traditional chip package mode needs to carry out bearing function chip via a bearing substrate, and needs in solution
To reach the electric connection between functional chip and bearing substrate via routing " defect.
A kind of semiconductor package that a present invention wherein embodiment is provided, comprising: a chip
Unit (alternatively referred to as " wafer cell "), an encapsulation unit and an electrode unit.Described chip unit
Including at least semiconductor chip, semiconductor chip described at least a part of which one have an end face, one back to
Be connected between described end face and described bottom surface in the bottom surface of described end face and one around side, and
There is on the described bottom surface of semiconductor chip described at least one one first conductive welding pad and one second conduction
Weld pad.Described encapsulation unit includes that the described end face of semiconductor chip described in a covering at least is with described
Around the packaging body of side, two contrary sides of wherein said packaging body are respectively provided with one first side
End and one second side end.Described electrode unit includes described first side of a described packaging body of cladding
First electrode structure of end and one is coated with the second electrode of described second side end of described packaging body
Structure, wherein said first electrode structure and a described second electrode structure preset distance separated from one another,
And described first electrode structure and described second electrode structure the most in electrical contact described first conduct electricity and weld
Pad and described second conductive welding pad.
The manufacture method of a kind of semiconductor package that the other embodiment of the present invention is provided, its bag
Include the following step: first, cut a wafer, to form multiple semiconductor chip being separated from each other, its
In each described semiconductor chip there is an end face, one back in the bottom surface of described end face and even
Be connected between described end face and described bottom surface around side, and the institute of each described semiconductor chip
State and there is on bottom surface one first conductive welding pad and one second conductive welding pad；Then, each is described partly
Conductor chip is inverted and is positioned in an accommodation space, so that described first conductive welding pad and described the
Two conductive welding pad are all hidden by corresponding described semiconductor chip；Then, fill encapsulating material in
In described accommodation space, to cover multiple described semiconductor chip；It follows that cut described encapsulation material
Material, to form multiple packaging body, it is corresponding described that packaging body described in each of which covers each
The described end face of semiconductor chip is with described around side, and two of each described packaging body are on the contrary
One first side end and one second side end it is respectively provided with on side；Finally, multiple first electrode is formed
Structure and multiple second electrode structure, the institute that the first electrode structure surrounding phase described in each of which is corresponding
State described first side end of packaging body and be electrically connected with the described of corresponding described semiconductor chip
First conductive welding pad, and the institute of described packaging body corresponding to each described second electrode structure surrounding phase
State the second side end and be electrically connected with described second conductive welding pad of corresponding described semiconductor chip.
Beneficial effects of the present invention can be, the semiconductor package that the embodiment of the present invention is provided
And preparation method thereof, it can be by " the described end face of semiconductor chip described in a covering at least one and institute
State the packaging body around side " with " filling encapsulating material is in described accommodation space, multiple to cover
Described semiconductor chip " design so that semiconductor package of the present invention and preparation method thereof
Can effectively solve " traditional chip package mode needs to carry out bearing function chip via a bearing substrate,
And need via routing to the electric connection reaching between functional chip and bearing substrate " defect.
It is further understood that inventive feature and technology contents for enabling, refers to below in connection with this
Bright detailed description and accompanying drawing, but institute's accompanying drawings only provides reference and explanation use, is not used for this
The invention person of being any limitation as.
Accompanying drawing explanation
Fig. 1 is the flow chart of the manufacture method of semiconductor package of the present invention.
Fig. 2 A is the making signal of step S100 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 B is the making signal of step S102 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 C is the making signal of step S104 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 D is the making signal of step S106 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 E is the making signal of step S108 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 F is the making signal of step S110 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 G is the making signal of step S112 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 H is the making signal of step S114 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 2 I is the making signal of step S116 of the manufacture method of semiconductor package of the present invention
Figure.
Fig. 3 A provides the side-looking of semiconductor chip in the manufacture method for semiconductor package of the present invention
Schematic diagram.
Fig. 3 B be semiconductor package of the present invention manufacture method in formed packaging body side-looking signal
Figure.
Fig. 3 C be semiconductor package of the present invention manufacture method in form the first inner conducting layer and
The schematic side view of two inner conducting layers.
Fig. 3 D be semiconductor package of the present invention manufacture method in form in first conductive layer and the
The schematic side view of conductive layer in two.
Fig. 3 E be semiconductor package of the present invention manufacture method in form the first outer conducting layer and
Two outer conducting layers are to complete the schematic side view of the manufacturing process of semiconductor package.
Fig. 4 is the side elevational cross-section schematic diagram that semiconductor package of the present invention is arranged in substrate body.
Fig. 5 A is the schematic side view of packaging body coats semiconductor chip of the present invention.
Fig. 5 B is that the present invention mode via plating is to form the schematic side view of multiple conductive material.
Fig. 5 C is the schematic side view that the present invention forms multiple insulant.
Fig. 5 D is that the present invention removes in each conductive material the most corresponding via the mode of etching
The schematic side view of a part that is coated with of insulant.
Fig. 5 E is the schematic side view that the present invention removes multiple insulant.
Fig. 5 F is that the present invention forms in multiple first the side of conductive layer in conductive layer and multiple second respectively
Depending on schematic diagram.
Fig. 5 G is that the present invention forms multiple first outer conducting layer and the side of multiple second outer conducting layer respectively
Depending on schematic diagram.
[main element symbol description]
Semiconductor package Z
Chip unit 1
Semiconductor chip 10
First conductive welding pad 10A
Second conductive welding pad 10B
End face 100
Bottom surface 101
Around side 102
Rounding 103
Encapsulation unit 2
Encapsulating material 20 '
Cutting track 200 '
Packaging body 20
First side end 20A
Second side end 20B
Upper surface 200
Around surface 201
Lower surface 202
Electrode unit 3
Conductive material 300 '
Insulant 301 '
First electrode structure 31
First inner conducting layer 310
Conductive layer 311 in first
First outer conducting layer 312
First bottom 3120
Second electrode structure 32
Second inner conducting layer 320
Conductive layer 321 in second
Second outer conducting layer 322
Second bottom 3220
Base board unit 4
Substrate body 40
Scolding tin S
Wafer W
Stick together substrate H
Around shape barricade D
Accommodation space R
Detailed description of the invention
Referring to shown in Fig. 1, Fig. 2 A to Fig. 2 I and Fig. 3, the present invention provides a kind of semiconductor package
The manufacture method of assembling structure Z, it comprises the following steps:
First, coordinate shown in Fig. 1 Yu Fig. 2 A, it is provided that a wafer W, it includes multiple quasiconductors
Chip 10(S100), plurality of semiconductor chip 10 not yet cuts down from wafer W, and
Each semiconductor chip 10 can be one in advance with the diode completed made by semiconductor fabrication program
Chip or any functional chip, such as Transient Voltage Suppressor (Transient Voltage
Suppressor, TVS).
Then, coordinate shown in Fig. 1 Yu Fig. 2 B, via screen printing (screen printing), with
Each semiconductor chip 10 is formed one first conductive welding pad 10A and one second conductive welding pad
10B(S102).But, the present invention does not limit to the mode being merely able to use screen printing and forms first
Conductive welding pad 10A and one second conductive welding pad 10B, the most any can be used to form the first conductive welding pad
10A and the production method of one second conductive welding pad 10B, all can be applicable to the present invention.
Then, coordinating shown in Fig. 1, Fig. 2 B, Fig. 2 C and Fig. 3 A, cutting crystal wafer W(is along in advance
The Virtual cropping line being first defined on the wafer W of Fig. 2 B), with formed multiple be separated from each other partly lead
Body chip 10(S104), the most as shown in Figure 2 C, each semiconductor chip 10 has an end face
100, one it is connected between end face 100 and bottom surface 101 back to the bottom surface 101 and in end face 100
Around having one first conduction weldering on side 102, and the bottom surface 101 of each semiconductor chip 10
Pad 10A and one second conductive welding pad 10B.
It follows that coordinate shown in Fig. 1, Fig. 2 C and Fig. 2 D, each semiconductor chip 10 is fallen
Put and be positioned in an accommodation space R, so that the first conductive welding pad 10A and the second conductive welding pad
10B is all hidden (S106) by corresponding semiconductor chip 10.In other words, in step S106
In, can first semiconductor chip 10 be taken out (such as Fig. 2 C from the described wafer W cut
Shown in), then semiconductor chip 10 is turned upside down and paste and stick together on substrate H one, Qi Zhongduo
Individual semiconductor chip 10 preset distance separated from one another.For example, can set on substrate H sticking together
Putting one then can be by sticking together substrate H around the contained space size covered of shape barricade D, accommodation space R
Define with around coordinating of shape barricade D.
And then, coordinate shown in Fig. 1, Fig. 2 D, Fig. 2 E and Fig. 3 B, fill encapsulating material 20 '
In accommodation space R, to cover multiple semiconductor chip 10(S108).For example, encapsulation material
Material 20 ' can be the packaging adhesive material of any not light-permeable, such as epoxy resin or silica gel etc..
Then, coordinate shown in Fig. 1 Yu Fig. 2 F, form multiple cutting track 200 ' in encapsulating material
The upper surface (S110) of 20 '.
Then, coordinate shown in Fig. 1, Fig. 2 F and Fig. 2 G, cut along multiple cutting tracks 200 '
Cutting encapsulating material 20 ', to form multiple packaging body 20, each of which packaging body 20 covers each
The end face 100 of individual corresponding semiconductor chip 10 with around side 102(S112).
And then, coordinate shown in Fig. 1, Fig. 2 G and Fig. 2 H, each packaging body 20 is carried out down
Fillet processes, and is respectively provided with one first side end on two contrary sides of each packaging body 20
20A and one second side end 20B(S114).For further, at the outer rim of packaging body 20
After carrying out rounding process, multiple rounding 103, this rounding at the outer rim of packaging body 20, can be formed
103 will assist in the adhesive ability after subsequent electrode structure is formed.
It follows that coordinate shown in Fig. 1, Fig. 2 H and Fig. 2 I, form multiple first electrode structure 31
And multiple second electrode structure 32, each of which the first electrode structure 31 can be because of rounding 103
Formation and the first side end 20A and electric connection of packaging body 20 that more securely surrounding phase is corresponding
First conductive welding pad 10A of corresponding semiconductor chip 10, and each second electrode structure 32
Can because of the formation of rounding 103 second side of the packaging body 20 that more securely surrounding phase is corresponding
Portion 20B and be electrically connected with the second conductive welding pad 10B(S116 of corresponding semiconductor chip 10).
For further, coordinating shown in Fig. 2 I and Fig. 3 C to Fig. 3 E, above-mentioned steps S114 can
Further include: first, as shown in Figure 3 C, formed respectively multiple first inner conducting layer 310 and
Multiple second inner conducting layer 320(are such as formed in the way of being stained with silver), lead in each of which first
First side end 20A of the packaging body 20 that electric layer 310 surrounding phase is corresponding and in electrical contact corresponding
First conductive welding pad 10A of semiconductor chip 10, and each second inner conducting layer 320 surrounding phase
Second side end 20B of corresponding packaging body 20 and corresponding semiconductor chip 10 in electrical contact
Second conductive welding pad 10B；Then, as shown in Figure 3 D, conductive layer 311 in multiple first is formed respectively
And conductive layer 321(is such as formed in the way of electronickelling in multiple second), each of which first
The first inner conducting layer 310 that middle conductive layer 311 surrounding phase is corresponding, and each conductive layer 321 in second
The second inner conducting layer 320 that surrounding phase is corresponding；Finally, as shown in FIGURE 3 E, multiple is formed respectively
One outer conducting layer 312 and multiple second outer conducting layer 322(are such as formed in the way of electrotinning),
Each of which the first outer conducting layer 312 surrounding phase corresponding first in conductive layer 311, and each
Second outer conducting layer 322 surrounding phase corresponding second in conductive layer 321.
Therefore, via the production method of above-mentioned steps S100 to step S116, coordinate Fig. 2 I and figure
Shown in 3, the present invention can provide a kind of semiconductor package Z, comprising: a chip unit 1,
One encapsulation unit 2 and an electrode unit 3.
First, chip unit 1 includes at least semiconductor chip 10, and wherein semiconductor chip 10 has
An end face 100, one is had to be connected to end face 100 and the end back to the bottom surface 101 and in end face 100
Leading around having one first on side 102, and the bottom surface 101 of semiconductor chip 10 between face 101
Electric welding pad 10A and one second conductive welding pad 10B.Furthermore, encapsulation unit 2 includes a covering quasiconductor
The end face 100 of chip 10 and the packaging body 20 around side 102, wherein two phases of packaging body 20
Toss about and be respectively provided with one first side end 20A and one second side end 20B on holding.For example, half
The bottom surface 101 of conductor chip 10 can be exposed out from packaging body 20, and at the outer rim of packaging body 20
There is multiple rounding 103.Furthermore, packaging body 20 has a top corresponding to semiconductor chip 10
The upper surface 200, one in face 100 downwardly extends and corresponding to semiconductor chip 10 from upper surface 200
Around side 102 around surface 201 and from extending internally around surface 201 and only making half
First conductive welding pad 10A of conductor chip 10 and the exposed lower surface 202 of the second conductive welding pad 10B.
Additionally, electrode unit 3 includes first electricity of the first side end 20A of a cladding packaging body 20
Second electrode structure 32 of the second side end 20B of electrode structure 31 and a cladding packaging body 20, its
In the first electrode structure 31 and the second electrode structure 32 preset distance separated from one another, and the first electrode
Structure 31 and the second electrode structure 32 first conductive welding pad 10A in electrical contact respectively and the second conduction weldering
Pad 10B.For example, the first electrode structure 31 is coated with the upper surface 200 of packaging body 20 wherein
A part, the lower surface of a portion around surface 201 of packaging body 20, packaging body 20
A portion of the bottom surface 101 of a portion and semiconductor chip 10, and the second electrode knot
Structure 32 be coated with the another part of upper surface 200 of packaging body 20, packaging body 20 around surface
The another part of 201, the another part of the lower surface 202 of packaging body 20 and semiconductor chip
The another part of the bottom surface 101 of 10.Furthermore, the first electrode structure 31 includes a cladding packaging body
The first side end 20A of 20 and the of the first conductive welding pad 10A of semiconductor chip in electrical contact 10
One inner conducting layer 310, in the first of cladding the first inner conducting layer 310 conductive layer 311 and
One for being coated with the first outer conducting layer 312 of conductive layer 311 in first, and the second electrode structure 32
The second side end 20B and the second of semiconductor chip in electrical contact 10 including a cladding packaging body 20
Second inner conducting layer 320, of conductive welding pad 10B is for the second of cladding the second inner conducting layer 320
Middle conductive layer 321 and is used for the second outer conducting layer 322 of conductive layer 321 in cladding second.
For further, as shown in Figure 4, semiconductor package Z of the present invention can be further
Including: a base board unit 4, it includes a substrate body 40, wherein the of the first electrode structure 31
One bottom 3120 and the second bottom 3220 substrate body the most in electrical contact 40 of the second electrode structure 32,
And first electrode structure 31 with the second electrode structure 32 respectively via two scolding tin S to be electrically connected at
Substrate body 40 and being positioned in substrate body 40.
Referring to shown in Fig. 5 A to Fig. 5 G, the present invention can provide another to perform above-mentioned steps
The method of S116, as described below:
First, coordinate shown in Fig. 5 A and Fig. 5 B, form multiple conduction material via the mode of plating
Material 300 ', packaging body 20 corresponding to the complete surrounding phase of each of which conductive material 300 ' is with relative
The semiconductor chip 10 answered.
Then, coordinate shown in Fig. 5 B and Fig. 5 C, form multiple insulant 301 ' and (such as have
The macromolecular material of Sprouting resistance function), wherein each two insulant 301 ' is respectively coated by corresponding
Two opposite ends portions of conductive material 300 '.
Then, coordinate shown in Fig. 5 C and Fig. 5 D, remove each conduction material via the mode of etching
The part not being coated with by corresponding insulant 301 ' in material 300 ', multiple to be formed
First inner conducting layer 310 and multiple second inner conducting layer 320, each of which the first inner conducting layer 310
First side end 20A of the packaging body 20 that surrounding phase is corresponding and corresponding semiconductor core in electrical contact
First conductive welding pad 10A of sheet 10, and the envelope that each the second inner conducting layer 320 surrounding phase is corresponding
Second side end 20B of dress body 20 and the second conduction of corresponding semiconductor chip 10 in electrical contact
Weld pad 10B.
It follows that coordinate shown in Fig. 5 D and Fig. 5 E, remove multiple insulant 301 ', with exposed
Multiple first inner conducting layers 310 and multiple second inner conducting layer 320.
And then, coordinate shown in Fig. 5 E and Fig. 5 F, form conductive layer 311 in multiple first respectively
And conductive layer 321 in multiple second, that in each of which first, conductive layer 311 surrounding phase is corresponding
One inner conducting layer 310, and each second inner conducting layer that conductive layer 321 surrounding phase is corresponding in second
320。
Finally, coordinate shown in Fig. 5 F and Fig. 5 G, formed respectively multiple first outer conducting layer 312 and
Multiple second outer conducting layers 322, each of which the first outer conducting layer 312 surrounding phase corresponding first
Middle conductive layer 311, and each second outer conducting layer 322 surrounding phase corresponding second in conductive layer
321。
(the possible effect of embodiment)
Beneficial effects of the present invention can be, the semiconductor package that the embodiment of the present invention is provided
Z and preparation method thereof, it can be by " one covers the end face 100 of semiconductor chip 10 and around side
The packaging body 20 in face 102 " with " filling encapsulating material 20 ' is in accommodation space R, many to cover
Individual semiconductor chip 10 " design so that the semiconductor package Z of the present invention and making thereof
Method can effectively solve that " traditional chip package mode needs to carry out bearing function core via a bearing substrate
Sheet, and needing via routing to the electric connection reaching between functional chip and bearing substrate " lack
Fall into.
The foregoing is only the preferred possible embodiments of the present invention, the non-patent model therefore limiting to the present invention
Enclose, therefore the equivalence techniques change such as using description of the invention and graphic content to do, it is both contained in
In the scope of the present invention.
Claims (11)
1. a semiconductor package, it is characterised in that including:
One chip unit, described chip unit includes at least semiconductor chip, at least a part of which
Semiconductor chip described in one has an end face, one back in the bottom surface of described end face and even
Be connected between described end face and described bottom surface around side, and semiconductor core described at least
There is on the described bottom surface of sheet one first conductive welding pad and one second conductive welding pad；
One encapsulation unit, described encapsulation unit includes semiconductor chip described in a covering at least
Described end face and the described packaging body around side, two of wherein said packaging body are contrary
Side on be respectively provided with one first side end and one second side end；And
One electrode unit, described electrode unit includes described the first of a described packaging body of cladding
First electrode structure of side end and one is coated with the of described second side end of described packaging body
Two electrode structures, wherein said first electrode structure is separated from one another with described second electrode structure
One preset distance, and described first electrode structure is electrically connected with respectively with described second electrode structure
Touch described first conductive welding pad and described second conductive welding pad；
Wherein, described packaging body has the described end face of semiconductor chip described in one and at least
Corresponding upper surface, one downwardly extend from described upper surface and with quasiconductor described at least
Described corresponding inwardly the prolonging around surface from described around surface and one around side of chip
Stretch and only make described first conductive welding pad of semiconductor chip described at least lead with described second
The lower surface that electric welding pad exposes；
Wherein, described first electrode structure is coated with the described upper surface of described packaging body wherein
Described a portion around surface of packaging body a part of, described, described packaging body
The described bottom surface of semiconductor chip described in a portion and at least of described lower surface
A portion, and the described upper surface of the described second electrode structure described packaging body of cladding
Another part, the described another part around surface of described packaging body, described encapsulation
The described end of semiconductor chip described in the another part and at least of the described lower surface of body
The another part in face.
Semiconductor package the most according to claim 1, it is characterised in that described at least one
The described bottom surface of semiconductor chip is exposed out from described packaging body, and outside described packaging body
There is at edge multiple rounding.
Semiconductor package the most according to claim 1, it is characterised in that described first electricity
Electrode structure includes described first side end and in electrical contact at least of a described packaging body of cladding
First inner conducting layer of described first conductive welding pad of described semiconductor chip, one it is used for being coated with
In the first of described first inner conducting layer, conductive layer and is used for being coated with in described first conduction
First outer conducting layer of layer, and described second electrode structure includes a described packaging body of cladding
Described second conduction of semiconductor chip described in described second side end and in electrical contact at least
Second inner conducting layer of weld pad, one for be coated with described second inner conducting layer second in conduct electricity
Layer and one is for being coated with the second outer conducting layer of conductive layer in described second.
Semiconductor package the most according to claim 1, it is characterised in that bag the most further
Including: a base board unit, described base board unit includes a substrate body, wherein said first electricity
The bottom of electrode structure is all electrically connected with described substrate body with the bottom of described second electrode structure
Touch, and described first electrode structure and described second electrode structure respectively via two scolding tin with
It is electrically connected with described substrate body.
5. the manufacture method of a semiconductor package, it is characterised in that comprise the following steps:
One wafer is carried out cutting process, to form multiple semiconductor chip being separated from each other,
Semiconductor chip described in each of which have an end face, one back in the bottom surface of described end face,
And one be connected between described end face and described bottom surface around side, and each described half
There is on the described bottom surface of conductor chip one first conductive welding pad and one second conductive welding pad；
Each described semiconductor chip is inverted and is positioned in an accommodation space, so that
Described first conductive welding pad with described second conductive welding pad all by corresponding described semiconductor core
Sheet is hidden；
Encapsulating material is filled in described accommodation space, to cover multiple described semiconductor core
Sheet；
Described encapsulating material is carried out cutting process, to form multiple packaging body, each of which
Individual described packaging body covers described end face and the institute of each corresponding described semiconductor chip
State around side, and be respectively provided with one on two contrary sides of each described packaging body
First side end and one second side end；And
Form multiple first electrode structure and multiple second electrode structure, described in each of which
Described first side end of the described packaging body that the first electrode structure surrounding phase is corresponding and electrically connecting
Connect described first conductive welding pad of corresponding described semiconductor chip, and each described
Described second side end of the described packaging body that two electrode structure surrounding phase are corresponding and electric connection
Described second conductive welding pad of corresponding described semiconductor chip；
Wherein, described packaging body has the described end face of semiconductor chip described in one and at least
Corresponding upper surface, one downwardly extend from described upper surface and with quasiconductor described at least
Described corresponding inwardly the prolonging around surface from described around surface and one around side of chip
Stretch and only make described first conductive welding pad of semiconductor chip described at least lead with described second
The lower surface that electric welding pad exposes；
Wherein, described first electrode structure is coated with the described upper surface of described packaging body wherein
Described a portion around surface of packaging body a part of, described, described packaging body
The described bottom surface of semiconductor chip described in a portion and at least of described lower surface
A portion, and the described upper surface of the described second electrode structure described packaging body of cladding
Another part, the described another part around surface of described packaging body, described encapsulation
The described end of semiconductor chip described in the another part and at least of the described lower surface of body
The another part in face.
The manufacture method of semiconductor package the most according to claim 5, it is characterised in that
Before the described step that described wafer is carried out cutting process, may further comprise: via web plate
Printing, to form described first conductive welding pad with described second conductive welding pad in corresponding institute
State on the described bottom surface of semiconductor chip.
The manufacture method of semiconductor package the most according to claim 5, it is characterised in that
Described by each described semiconductor chip be inverted and be positioned at the step in described accommodation space
In, may further comprise: and first described semiconductor chip is taken out from described wafer, then
Described semiconductor chip is turned upside down and paste one be arranged in described accommodation space glutinous
On substrate, a plurality of described semiconductor chip preset distance separated from one another.
The manufacture method of semiconductor package the most according to claim 5, it is characterised in that
In the described step that described encapsulating material is carried out cutting process, may further comprise: first shape
Become multiple cutting track in the upper surface of described encapsulating material, then along the plurality of cutting
Track cuts encapsulating material.
The manufacture method of semiconductor package the most according to claim 5, it is characterised in that
Multiple described first electrode structure of described formation and the step of multiple described second electrode structure
Before, may further comprise: and packaging body each described is carried out rounding process.
The manufacture method of semiconductor package the most according to claim 5, it is characterised in that
Multiple described first electrode structure of described formation and the step of multiple described second electrode structure
In, may further comprise:
Form multiple first inner conducting layer and multiple second inner conducting layer, each of which respectively
Described first side end of the described packaging body that described first inner conducting layer surrounding phase is corresponding and electricity
Property the corresponding described semiconductor chip of contact described first conductive welding pad, and each institute
State described second side end and electrically of described packaging body corresponding to the second inner conducting layer surrounding phase
Contact described second conductive welding pad of corresponding described semiconductor chip；
Form in multiple first conductive layer, each of which in conductive layer and multiple second respectively
Described first inner conducting layer that in described first, conductive layer surrounding phase is corresponding, and described in each
Described second inner conducting layer that in second, conductive layer surrounding phase is corresponding；And
Form multiple first outer conducting layer and multiple second outer conducting layer, each of which respectively
Described first outer conducting layer surrounding phase corresponding described first in conductive layer, and described in each
Second outer conducting layer surrounding phase corresponding described second in conductive layer.
The manufacture method of 11. semiconductor packages according to claim 5, it is characterised in that
Multiple described first electrode structure of described formation and the step of multiple described second electrode structure
In, may further comprise:
Forming multiple conductive material, the complete surrounding phase of conductive material described in each of which is corresponding
Described packaging body and corresponding described semiconductor chip；
Forming multiple insulant, wherein insulant described in each two is respectively coated by corresponding
Two contrary terminal parts of described conductive material；
Remove in each described conductive material and be not coated with by corresponding insulant
A part, to form multiple first inner conducting layer and multiple second inner conducting layer, the most often
Described first side end of the described packaging body that one described first inner conducting layer surrounding phase is corresponding
And described first conductive welding pad of corresponding described semiconductor chip in electrical contact, and each
Described second side end of the described packaging body that individual described second inner conducting layer surrounding phase is corresponding and
Described second conductive welding pad of corresponding described semiconductor chip in electrical contact；
Remove multiple described insulant, with exposed multiple described first inner conducting layers and multiple
Described second inner conducting layer；
Form in multiple first conductive layer, each of which in conductive layer and multiple second respectively
Described first inner conducting layer that in described first, conductive layer surrounding phase is corresponding, and described in each
Described second inner conducting layer that in second, conductive layer surrounding phase is corresponding；And
Form multiple first outer conducting layer and multiple second outer conducting layer, each of which respectively
Described first outer conducting layer surrounding phase corresponding described first in conductive layer, and described in each
Second outer conducting layer surrounding phase corresponding described second in conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210593014.XA CN103915394B (en) | 2012-12-31 | 2012-12-31 | Semiconductor package and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210593014.XA CN103915394B (en) | 2012-12-31 | 2012-12-31 | Semiconductor package and preparation method thereof |
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| CN103915394A CN103915394A (en) | 2014-07-09 |
| CN103915394B true CN103915394B (en) | 2016-12-28 |
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| TWI664683B (en) * | 2017-03-16 | 2019-07-01 | 佳邦科技股份有限公司 | Method of manufacturing semiconductor package |
| CN112652619B (en) * | 2020-12-22 | 2022-08-09 | 长江存储科技有限责任公司 | Gasket and manufacturing method thereof, and packaging structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102456634A (en) * | 2010-10-19 | 2012-05-16 | 联京光电股份有限公司 | Packaging board and manufacturing method thereof |
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| JP2001313350A (en) * | 2000-04-28 | 2001-11-09 | Sony Corp | Chip-shaped electronic component and its manufacturing method, and pseudo-wafer used for manufacture of chip- shaped electronic component and its manufacturing method |
| US7884462B2 (en) * | 2008-09-30 | 2011-02-08 | Inpaq Technology Co., Ltd. | Insulation covering structure for a semiconductor element with a single die dimension and a manufacturing method thereof |
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