JP2009088360A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 239000000758 substrate Substances 0.000 claims abstract description 74
- 230000015556 catabolic process Effects 0.000 claims abstract description 33
- 239000012212 insulator Substances 0.000 claims description 23
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 13
- 239000012535 impurity Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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Abstract
【解決手段】半導体装置1は、平面方形状の基板2と、基板2主面の素子領域10において、平面ストライプ形状を有する第1のリサーフ構造3と、基板2主面の素子領域10において、第1のリサーフ構造3間に配設されたトランジスタTと、基板2主面の周辺領域において、平面ストライプ形状を有する第2のリサーフ構造3aを用いた第1の耐圧部11と、基板2主面の角領域において、基板2主面の対角線Dに対して左右対称に配設された第3のリサーフ構造3bを用いた第2の耐圧部12とを備える。
【選択図】図1
Description
本発明の第1の実施の形態は、縦型パワートランジスタを搭載する電力用半導体装置に本発明を適用した例を説明するものである。
本発明の第2の実施の形態は、前述の第1の実施の形態に係る半導体装置1において、第2の耐圧部12のリサーフ層の平面形状を代えた例を説明するものである。
本発明の第3の実施の形態は、前述の第1の実施の形態又は第2の実施の形態に係る半導体装置1において、第2の耐圧部12のリサーフ層の配列方式を代えた例を説明するものである。
このように構成される第3の実施の形態に係る半導体装置1においては、第2の耐圧部12の空乏層の伝わり方をより一層向上することができるので、耐圧を向上することができる。
上記のように、本発明を一実施の形態及びその変形例によって記載したが、この開示の一部をなす論述及び図面はこの発明を限定するものでない。本発明は様々な代替実施の形態、実施例及び運用技術に適用することができる。例えば、本発明は、素子領域10の半導体素子として、縦型パワーMOSFETを例に実施の形態を説明したが、素子領域10には縦型IGBT、トランジスタ、ダイオード等が搭載されていてもよい。
10…素子領域
11…第1の耐圧部
12…第2の耐圧部
2…基板
2S…n型の第1の半導体領域
2E…n型の第2の半導体領域
21−24…辺
3…第1のリサーフ構造
3a…第2のリサーフ構造
3b…第3のリサーフ構造
31、41、51…トレンチ
32、42、52…p型半導体領域
33、43、53…絶縁体
6…p型ベース領域
7…n型ソース領域
8…ゲート絶縁膜
9…ゲート電極
T…トランジスタ
Claims (9)
- 第1の方向において対向する第1の辺及び第2の辺と前記第1の方向と交差する第2の方向において対向する第3の辺及び第4の辺とを有する平面方形状の基板と、
前記基板主面の素子領域において、前記基板の前記第1の辺から前記第2の辺に向かう前記第1の方向に沿って長手方向が延在し、前記基板の前記第3の辺から前記第4の辺に向かう前記第2の方向に複数配列された平面ストライプ形状を有するリサーフ領域と、
前記基板主面の前記素子領域において、前記リサーフ領域間に配設された半導体素子と、
前記基板主面の前記第3の辺側及び前記第4の辺側であって、前記素子領域の外側の周辺領域において、前記第2の方向に沿って長手方向が延在し、前記第1の方向に複数配列された平面ストライプ形状を有する第1のトレンチを用いた第1の耐圧部と、
前記基板主面の前記第1の耐圧部よりも前記第1の辺側及び前記第2の辺側の角領域において、前記基板主面の前記角領域を通る対角線に対して左右対称に複数配設された第2のトレンチを用いた第2の耐圧部と、
を備えたことを特徴とする半導体装置。 - 前記第1の耐圧部は、前記基板主面から深さ方向に配設された前記第1のトレンチと、この第1のトレンチ内部に埋設された絶縁体と、前記第1のトレンチに沿って前記基板表面に構成された前記基板の導電型とは反対導電型の第1の半導体領域とを備え、前記リサーフ領域は、前記基板主面から深さ方向に配設された前記第3のトレンチと、この第3のトレンチ内部に埋設された絶縁体と、前記第3のトレンチに沿って前記基板表面に構成された前記基板の導電型とは反対導電型の第2の半導体領域とを備え、前記第2の半導体領域の一端は前記第1の半導体領域に接続されていることを特徴とする請求項1に記載の半導体装置。
- 前記第2の耐圧部は、前記基板主面から深さ方向に配設された前記第2のトレンチと、この第2のトレンチ内部に埋設された絶縁体と、前記第2のトレンチに沿って前記基板表面に構成された前記基板の導電型とは反対導電型の第3の半導体領域とを備え、前記第3の半導体領域は前記第1の半導体領域及び前記第2の半導体領域に接続されていないことを特徴とする請求項2に記載の半導体装置。
- 前記第2のトレンチは、前記第1の方向に延在する第3のトレンチと、この第3のトレンチに対して前記対角線を中心に左右対称に配設され、前記第2の方向に延在する第4のトレンチと、を備え、前記第3のトレンチの延伸線と前記第4のトレンチの延伸線とを結んだ平面形状が前記対角線に沿って折れ曲がる平面L字形状を有することを特徴とする請求項3に記載の半導体装置。
- 前記第2の耐圧部において、前記第3のトレンチ同士と前記第4のトレンチ同士との間は離間され、前記第3のトレンチに沿って構成された前記第3の半導体領域と前記第4のトレンチに沿って構成された前記第3の半導体領域との間が相互に連結されていることを特徴とする請求項4に記載の半導体装置。
- 前記第2の耐圧部の前記第2のトレンチの平面形状は正方形、長方形、四角形以上の多角形、円形又は楕円形であることを特徴とする請求項2又は請求項3に記載の半導体装置。
- 前記第3の半導体領域の間隔は、前記基板主面の角から前記基板主面中心に向かって等しいか、又は徐々に大きく設定されていることを特徴とする請求項4又は請求項5に記載の半導体装置。
- 前記第3の半導体領域の間隔は、前記第1の半導体領域の間隔以下に設定されていることを特徴とする請求項3又は請求項7に記載の半導体装置。
- 前記第2の耐圧部の前記第2のトレンチの深さは、前記第1の耐圧部の前記第1のトレンチの深さと同一であることを特徴とする請求項1乃至請求項7のいずれかに記載の半導体装置。
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JP2007258086A JP5228430B2 (ja) | 2007-10-01 | 2007-10-01 | 半導体装置 |
US12/212,735 US7964931B2 (en) | 2007-10-01 | 2008-09-18 | Semiconductor device |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010147176A (ja) * | 2008-12-17 | 2010-07-01 | Rohm Co Ltd | 半導体装置 |
WO2013076820A1 (ja) | 2011-11-22 | 2013-05-30 | トヨタ自動車株式会社 | 半導体装置 |
JP2014013894A (ja) * | 2012-06-20 | 2014-01-23 | Oxford Instruments Analytical Oy | 2次元ガード構造およびそれを用いた放射線検出器 |
Families Citing this family (9)
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JP5543758B2 (ja) * | 2009-11-19 | 2014-07-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN102479800B (zh) * | 2010-11-23 | 2013-10-23 | 上海华虹Nec电子有限公司 | 超级结器件的终端保护结构 |
JP5719167B2 (ja) * | 2010-12-28 | 2015-05-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
CN103035723A (zh) * | 2012-10-26 | 2013-04-10 | 上海华虹Nec电子有限公司 | 一种超级结深沟槽结构 |
US9184277B2 (en) * | 2012-10-31 | 2015-11-10 | Infineon Technologies Austria Ag | Super junction semiconductor device comprising a cell area and an edge area |
KR102014437B1 (ko) * | 2013-10-17 | 2019-10-21 | 에스케이하이닉스 주식회사 | 다원화된 측벽 산화막 구조를 갖는 반도체 장치 및 그 제조 방법 |
CN105161518B (zh) * | 2015-06-18 | 2018-03-06 | 中航(重庆)微电子有限公司 | 超级结布局结构 |
CN104916700B (zh) * | 2015-06-18 | 2018-05-25 | 中航(重庆)微电子有限公司 | 超级结布局结构 |
CN105529363A (zh) * | 2016-01-29 | 2016-04-27 | 上海华虹宏力半导体制造有限公司 | 超级结及其制造方法 |
Citations (2)
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JP2003086800A (ja) * | 2001-09-12 | 2003-03-20 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007227620A (ja) * | 2006-02-23 | 2007-09-06 | Toyota Central Res & Dev Lab Inc | 半導体装置とその製造方法 |
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JP4765012B2 (ja) * | 2000-02-09 | 2011-09-07 | 富士電機株式会社 | 半導体装置及びその製造方法 |
EP1267415A3 (en) * | 2001-06-11 | 2009-04-15 | Kabushiki Kaisha Toshiba | Power semiconductor device having resurf layer |
JP4943639B2 (ja) * | 2004-08-31 | 2012-05-30 | 株式会社豊田中央研究所 | 半導体装置 |
US7595542B2 (en) * | 2006-03-13 | 2009-09-29 | Fairchild Semiconductor Corporation | Periphery design for charge balance power devices |
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003086800A (ja) * | 2001-09-12 | 2003-03-20 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2007227620A (ja) * | 2006-02-23 | 2007-09-06 | Toyota Central Res & Dev Lab Inc | 半導体装置とその製造方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010147176A (ja) * | 2008-12-17 | 2010-07-01 | Rohm Co Ltd | 半導体装置 |
WO2013076820A1 (ja) | 2011-11-22 | 2013-05-30 | トヨタ自動車株式会社 | 半導体装置 |
US9082842B2 (en) | 2011-11-22 | 2015-07-14 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
JP2014013894A (ja) * | 2012-06-20 | 2014-01-23 | Oxford Instruments Analytical Oy | 2次元ガード構造およびそれを用いた放射線検出器 |
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JP5228430B2 (ja) | 2013-07-03 |
US7964931B2 (en) | 2011-06-21 |
US20090085146A1 (en) | 2009-04-02 |
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