CN107924940B - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN107924940B
CN107924940B CN201580082520.4A CN201580082520A CN107924940B CN 107924940 B CN107924940 B CN 107924940B CN 201580082520 A CN201580082520 A CN 201580082520A CN 107924940 B CN107924940 B CN 107924940B
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工藤智人
友松佳史
春口秀树
阿多保夫
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Mitsubishi Electric Corp
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Abstract

第三伪沟槽(11)在衬底端部的伪单元区域与第一以及第二伪沟槽(9、10)正交。层间绝缘膜(13)使由第一以及第二伪沟槽(9、10)夹持的衬底中央部的伪单元区域的p型扩散层(3、4)与发射极电极(14)绝缘。第三伪沟槽(11)将衬底中央部的伪单元区域的p型扩散层(3、4)、和与发射极电极(14)连接的衬底端部的伪单元区域的p型扩散层(3、4、15)分离。p型阱层(15)在衬底端部设置为比第三伪沟槽(11)深。第三伪沟槽(11)与p型阱层(15)相比设置于衬底中央侧。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
使用具有栅极沟槽和伪沟槽的电力用半导体装置，其中，该栅极沟槽具有MOS栅极功能，该伪沟槽不具有MOS栅极功能。在上述装置中，将被伪沟槽夹持的伪单元区域与发射极电极的接触仅设置于衬底端部(例如，参照专利文献1)。
专利文献1：日本特开2009-277792号公报
发明内容
通过伪单元区域的空穴蓄积效果能够改善导通电压与通断损耗的折衷关系。但是，由于伪单元区域的电位在衬底端部和衬底中央部不同，因此空穴蓄积效果在衬底端部和衬底中央部不同。由此产生的导通电阻的差诱发衬底内的电流不平衡。
本发明就是为了解决上述课题而提出的，其目的在于得到能够抑制衬底内的电流不平衡的半导体装置。
本发明涉及的半导体装置的特征在于，具有：n型衬底，其具有有源单元区域和伪单元区域；p型扩散层，其设置于所述n型衬底的上表面侧；n型发射极层，其在所述有源单元区域设置于所述p型扩散层之上的一部分；栅极沟槽，其在所述有源单元区域将所述p型扩散层和所述n型发射极层贯穿；第一以及第二伪沟槽，它们在所述伪单元区域将所述p型扩散层贯穿，是在俯视观察时与所述栅极沟槽平行地设置的；第三伪沟槽，其在衬底端部的所述伪单元区域将所述p型扩散层贯穿，与所述第一以及第二伪沟槽正交；发射极电极，其与所述n型发射极层、所述有源单元区域的所述p型扩散层、以及所述衬底端部的所述伪单元区域的所述p型扩散层连接；层间绝缘膜，其使由所述第一以及第二伪沟槽夹持的衬底中央部的所述伪单元区域的所述p型扩散层与所述发射极电极绝缘；p型集电极层，其设置于所述n型衬底的下表面侧；以及集电极电极，其与所述p型集电极层连接，所述第三伪沟槽将所述衬底中央部的所述伪单元区域的所述p型扩散层、和与所述发射极电极连接的所述衬底端部的所述伪单元区域的所述p型扩散层分离，所述p型扩散层在所述衬底端部具有比所述第三伪沟槽深地设置的p型阱层，所述第三伪沟槽与所述p型阱层相比设置于衬底中央侧。
发明的效果
在本发明中，第三伪沟槽将衬底中央部的伪单元区域的p型扩散层、和与发射极电极连接的衬底端部的伪单元区域的p型扩散层分离。另外，第三伪沟槽与p型阱层相比设置于衬底中央侧，因此也不会由于深的p型阱层而损害衬底中央部与衬底端部的分离功能。由此，能够维持空穴的蓄积效果在衬底中央部和衬底端部均等的状态。其结果，不会使导通电压与通断损耗的折衷关系变差，能够抑制衬底内的电流不平衡。
附图说明
图1是表示本发明的实施方式1涉及的半导体装置的斜视图。
图2是表示本发明的实施方式1涉及的半导体装置的剖视图。
图3是表示本发明的实施方式1涉及的半导体装置的衬底的俯视图。
图4是表示本发明的实施方式1涉及的半导体装置的变形例1的斜视图。
图5是表示本发明的实施方式1涉及的半导体装置的变形例2的衬底的俯视图。
图6是表示本发明的实施方式1涉及的半导体装置的变形例3的衬底的俯视图。
图7是表示本发明的实施方式1涉及的半导体装置的变形例4的衬底的俯视图。
图8是表示本发明的实施方式2涉及的半导体装置的斜视图。
图9是表示本发明的实施方式2涉及的半导体装置的衬底的俯视图。
图10是表示本发明的实施方式2涉及的半导体装置的变形例的衬底的俯视图。
图11是表示本发明的实施方式3涉及的半导体装置的斜视图。
图12是表示本发明的实施方式3涉及的半导体装置的衬底的仰视图。
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置进行说明。对相同或者相对应的结构要素标注相同的标号，有时省略重复的说明。
实施方式1.
图1是表示本发明的实施方式1涉及的半导体装置的斜视图。图2是表示本发明的实施方式1涉及的半导体装置的剖视图。图3是表示本发明的实施方式1涉及的半导体装置的衬底的俯视图。该半导体装置为CSTBT(Carrier Stored Trench Gate BipolarTransistor)构造的IGBT(Insulated Gate Bipolar Transistor)。
n型衬底1具有实质上作为晶体管进行动作的有源单元区域和不作为晶体管进行动作的伪单元区域。n型电荷蓄积层2和p型基极层3依次设置于n型衬底1的上表面侧。p+型接触层4设置于p型基极层3之上的一部分。n+型发射极层5在有源单元区域设置于p型基极层3之上的一部分。
栅极沟槽6在有源单元区域将n型电荷蓄积层2、p型基极层3、p+型接触层4以及n+型发射极层5贯穿。有源栅极7隔着栅极氧化膜8设置于栅极沟槽6内。
在俯视观察时与栅极沟槽6平行地设置的第一以及第二伪沟槽9、10，在伪单元区域将n型电荷蓄积层2、p型基极层3以及p+型接触层4贯穿。第三伪沟槽11在衬底端部的伪单元区域将p型基极层3贯穿，且与第一以及第二伪沟槽9、10正交。伪栅极12隔着栅极氧化膜8设置于第一、第二以及第三伪沟槽9、10、11内。
在衬底端部，p型阱层15设置为比p型基极层3以及第三伪沟槽11深。在p型基极层3等之上设置有层间绝缘膜13，在该层间绝缘膜13之上设置有发射极电极14。n型缓冲层16和p型集电极层17依次设置于n型衬底1的下表面侧。集电极(collector)电极(electrode)18与p型集电极层17连接。
发射极电极14经由层间绝缘膜13的被去除的图案与n+型发射极层5、有源单元区域的p型基极层3和p+型接触层4、以及衬底端部的伪单元区域的p型阱层15连接。层间绝缘膜13使由第一以及第二伪沟槽9、10夹持的衬底中央部的伪单元区域的p型基极层3、p+型接触层4与发射极电极14绝缘。第三伪沟槽11将衬底中央部的伪单元区域的p型基极层3等p型扩散层、和与发射极电极14连接的衬底端部的伪单元区域的p型阱层15等p型扩散层分离。
由第一、第二以及第三伪沟槽9、10、11包围的p型扩散层成为浮置电位。为了缓和由该浮置p型扩散层的端部的曲率引起的电场强度，在衬底端部设置有p型阱层15。但是，为了防止衬底中央部侧和衬底端部侧隔着第三伪沟槽11而通过深的p型阱层15电连接，而使第三伪沟槽11与p型阱层15相比设置于衬底中央侧。
如以上所说明的那样，在本实施方式中，第三伪沟槽11将衬底中央部的伪单元区域的p型扩散层、和与发射极电极14连接的衬底端部的伪单元区域的p型扩散层分离。另外，由于第三伪沟槽11与p型阱层15相比设置于衬底中央侧，因此也不会由于深的p型阱层15而损害衬底中央部与衬底端部的分离功能。由此，能够维持空穴的蓄积效果在衬底中央部和衬底端部均等的状态。其结果，不会使导通电压与通断损耗的折衷关系变差，能够抑制衬底内的电流不平衡。
图4是表示本发明的实施方式1涉及的半导体装置的变形例1的斜视图。在变形例1中，栅极沟槽6与第一、第二以及第三伪沟槽9、10、11的深度彼此相同。由此，能够使第一、第二以及第三伪沟槽9、10、11与通常的栅极沟槽6同时形成，因此能够削减工序数量。
图5是表示本发明的实施方式1涉及的半导体装置的变形例2的衬底的俯视图。图6是表示本发明的实施方式1涉及的半导体装置的变形例3的衬底的俯视图。图7是表示本发明的实施方式1涉及的半导体装置的变形例4的衬底的俯视图。第一以及第二伪沟槽9、10与第三伪沟槽11的交点在变形例2中俯视观察时为半圆形，在变形例3中为多边形。在变形例4中，使沟槽的交点具有曲率。通过以上述方式对沟槽的交点的形状进行设定，从而能够抑制局部性电场集中。
实施方式2.
图8是表示本发明的实施方式2涉及的半导体装置的斜视图。图9是表示本发明的实施方式2涉及的半导体装置的衬底的俯视图。在本实施方式中，代替实施方式1的第三伪沟槽11，使伪单元区域的p型基极层3以及p+型接触层4的杂质浓度比有源单元区域的p型基极层3以及p+型接触层4低。其他结构与实施方式1相同。
伪单元区域的p型扩散层的扩散电阻与有源单元区域的p型扩散层的扩散电阻相比变高，因此在伪单元区域的浮置p型扩散层，能够维持空穴的蓄积效果在衬底中央部和衬底端部均等的状态。由此，能够抑制衬底内的电流不平衡。
图10是表示本发明的实施方式2涉及的半导体装置的变形例的衬底的俯视图。即使这样在伪单元区域不设置p+型接触层4，也能够获得同样的效果。
实施方式3.
图11是表示本发明的实施方式3涉及的半导体装置的斜视图。图12是表示本发明的实施方式3涉及的半导体装置的衬底的仰视图。在本实施方式中，代替实施方式1的第三伪沟槽11，作为p型集电极层而设置有第一p型集电极层17a和第二p型集电极层17b，其中，该第一p型集电极层17a设置于有源单元区域和衬底中央部的伪单元区域，该第二p型集电极层17b设置于衬底端部的伪单元区域，具有比第一p型集电极层17a高的杂质浓度。第二p型集电极层17b并不限定于p型阱层15正下方，具有朝向衬底中央部而杂质浓度逐渐降低的浮置构造。
在与发射极电极14连接的衬底端部的伪单元区域，空穴变得容易逃逸。因此，在本实施方式中，在该区域使p型集电极层为高浓度而增加空穴的注入量。由此，能够抑制衬底内的电流不平衡。
此外，实施方式1～3涉及的半导体装置不限于由硅形成，也可以由与硅相比带隙宽的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料或金刚石。对于由上述宽带隙半导体形成的半导体装置，由于耐电压性、容许电流密度高，因此能够实现小型化。通过使用该小型化的半导体装置，从而安装有该半导体装置的半导体模块也能够小型化。另外，由于半导体装置的耐热性高，因此能够使散热器的散热鳍片小型化，能够将水冷部进行空冷化，因此能够使半导体模块进一步小型化。另外，半导体装置的电力损失低且高效率，因此能够使半导体模块高效化。
标号的说明
1n型衬底，3p型基极层(p型扩散层)，4p+型接触层(p型扩散层)，5n+型发射极层，6栅极沟槽，9第一伪沟槽，10第二伪沟槽，11第三伪沟槽，13层间绝缘膜，14发射极电极，15p型阱层(p型扩散层)，17p型集电极层，17a第一p型集电极层，17b第二p型集电极层，18集电极电极

Claims (2)

1.一种半导体装置，其特征在于，具有：
n型衬底，其具有有源单元区域和伪单元区域；
p型扩散层，其设置于所述n型衬底的上表面侧；
n型发射极层，其在所述有源单元区域设置于所述p型扩散层之上的一部分；
栅极沟槽，其在所述有源单元区域将所述p型扩散层和所述n型发射极层贯穿；
第一以及第二伪沟槽，它们在所述伪单元区域将所述p型扩散层贯穿，是在俯视观察时与所述栅极沟槽平行地设置的；
发射极电极，其与所述n型发射极层、所述有源单元区域的所述p型扩散层、以及衬底端部的所述伪单元区域的所述p型扩散层连接；
层间绝缘膜，其使由所述第一以及第二伪沟槽夹持的衬底中央部的所述p型扩散层与所述发射极电极绝缘；
p型集电极层，其设置于所述n型衬底的下表面侧；以及
集电极电极，其与所述p型集电极层连接，
所述p型集电极层具有第一p型集电极层和第二p型集电极层，其中，该第一p型集电极层设置于所述有源单元区域和所述衬底中央部的所述伪单元区域，该第二p型集电极层设置于所述衬底端部的所述伪单元区域，具有比所述第一p型集电极层高的杂质浓度。
2.根据权利要求1所述的半导体装置，其特征在于，
所述第二p型集电极层具有朝向所述衬底中央部而杂质浓度逐渐降低的浮置构造。
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