JP2008526000A - 強誘電性キャパシタ積層エッチ・クリーニング - Google Patents
強誘電性キャパシタ積層エッチ・クリーニング Download PDFInfo
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- JP2008526000A JP2008526000A JP2007547040A JP2007547040A JP2008526000A JP 2008526000 A JP2008526000 A JP 2008526000A JP 2007547040 A JP2007547040 A JP 2007547040A JP 2007547040 A JP2007547040 A JP 2007547040A JP 2008526000 A JP2008526000 A JP 2008526000A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
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- Microelectronics & Electronic Packaging (AREA)
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- Materials Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
Claims (7)
- 半導体デバイス内に強誘電性キャパシタ構造を製造する方法であって、この方法は、
誘電性材料の上に下部電極拡散障壁構造を形成し、下部電極は誘電性材料内の導電性構造に少なくとも部分的に連結し、
下部電極拡散障壁構造の上に下部電極を形成し、
下部電極の上に強誘電性材料を形成し、
強誘電性材料の上に上部電極を形成し、
パターニングされたエッチング・マスクを上部電極の上に形成し、パターニングされたエッチング・マスクは、上部電極の一部を露出させ、
パターニングされたエッチング・マスクを用いて、上部電極、強誘電性材料、及び下部電極の一部をエッチングして、パターニングされた強誘電性キャパシタ構造を画定し、
パターニングされたエッチング・マスクを用いて下部電極拡散障壁構造の一部をエッチングし、
パターニングされた強誘電性キャパシタ構造を、第1のアッシング・プロセスを用いてアッシングし、
第1のアッシング・プロセスの後、ウェット・クリーニング・プロセスを実行し、更に、
ウェット・クリーニング・プロセスの直後、パターニングされた強誘電性キャパシタ構造を、第2のアッシング・プロセスを用いて酸化雰囲気中で約摂氏300度又はそれ以上の温度でアッシングする
ことを含む方法。 - 請求項1に記載の方法であって、第1のアッシング・プロセス、ウェット・クリーニング・プロセス、及び第2のアッシング・プロセスは、下部電極拡散障壁構造の一部をエッチングした後、及びパターニングされた強誘電性キャパシタ構造の上に上部拡散障壁又は誘電体材料が形成される前に実行される方法。
- 請求項1又は請求項2に記載の方法であって、第1のアッシング・プロセス、ウェット・クリーニング・プロセス、及び第2のアッシング・プロセスは、上部電極、強誘電性材料、及び下部電極の一部をエッチングした後、及び下部電極拡散障壁構造の一部をエッチングする前に実行される方法。
- 請求項1又は請求項2に記載の方法であって、第1のアッシング・プロセス、ウェット・クリーニング・プロセス、及び第2のアッシング・プロセスは、下部電極拡散障壁構造の一部をエッチングした後、及びパターニングされた強誘電性キャパシタ構造の上に上部拡散障壁又は誘電体材料が形成される前に実行される方法。
- 請求項1に記載の方法であって、更に
下部電極拡散障壁構造の一部をエッチングした後、第2のウェット・クリーニング・プロセスを実行し、更に
第2のウェット・クリーニング・プロセスの後、パターニングされた強誘電性キャパシタ構造を、第3のアッシング・プロセスを用いてアッシングすること
を含む方法。 - 請求項1から請求項5のうち任意の請求項に記載の方法であって、第2のアッシング・プロセスの後、パターニングされた強誘電性キャパシタ構造の上に上部拡散障壁又は誘電体材料を形成することを更に含む方法。
- 半導体デバイス内の強誘電性キャパシタ構造をエッチング及びクリーニングする方法であって、
上部電極、強誘電性材料、及び下部電極の一部をエッチングして、パターニングされた強誘電性キャパシタ構造を画定し、
下部電極拡散障壁構造の一部をエッチングし、
パターニングされた強誘電性キャパシタ構造を、第1のアッシング・プロセスを用いてアッシングし、
第1のアッシング・プロセスの後、ウェット・クリーニング・プロセスを実行し、更に、
ウェット・クリーニング・プロセスの後、パターニングされた強誘電性キャパシタ構造を、第2のアッシング・プロセスを用いて酸化雰囲気中で約摂氏300度又はそれ以上の温度でアッシングし、ウェット・クリーニング・プロセスと第2のアッシング・プロセスとの間に材料形成処理がないこと
を含む方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/016,400 | 2004-12-17 | ||
US11/016,400 US7220600B2 (en) | 2004-12-17 | 2004-12-17 | Ferroelectric capacitor stack etch cleaning methods |
PCT/US2005/046318 WO2006066261A2 (en) | 2004-12-17 | 2005-12-19 | Ferroelectric capacitor stack etch cleaning |
Publications (2)
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JP2008526000A true JP2008526000A (ja) | 2008-07-17 |
JP4838811B2 JP4838811B2 (ja) | 2011-12-14 |
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JP2007547040A Active JP4838811B2 (ja) | 2004-12-17 | 2005-12-19 | 強誘電性キャパシタ積層エッチ・クリーニング |
Country Status (4)
Country | Link |
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US (1) | US7220600B2 (ja) |
JP (1) | JP4838811B2 (ja) |
CN (1) | CN101416275A (ja) |
WO (1) | WO2006066261A2 (ja) |
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-
2004
- 2004-12-17 US US11/016,400 patent/US7220600B2/en active Active
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- 2005-12-19 JP JP2007547040A patent/JP4838811B2/ja active Active
- 2005-12-19 WO PCT/US2005/046318 patent/WO2006066261A2/en active Application Filing
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Cited By (1)
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JP2008010772A (ja) * | 2006-06-30 | 2008-01-17 | Fujitsu Ltd | 半導体装置及びその製造方法 |
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JP4838811B2 (ja) | 2011-12-14 |
WO2006066261A3 (en) | 2009-04-02 |
US7220600B2 (en) | 2007-05-22 |
WO2006066261A2 (en) | 2006-06-22 |
CN101416275A (zh) | 2009-04-22 |
US20060134808A1 (en) | 2006-06-22 |
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