JP2008523640A5 - - Google Patents

Download PDF

Info

Publication number
JP2008523640A5
JP2008523640A5 JP2007546817A JP2007546817A JP2008523640A5 JP 2008523640 A5 JP2008523640 A5 JP 2008523640A5 JP 2007546817 A JP2007546817 A JP 2007546817A JP 2007546817 A JP2007546817 A JP 2007546817A JP 2008523640 A5 JP2008523640 A5 JP 2008523640A5
Authority
JP
Japan
Prior art keywords
layer
amorphous silicon
arsenic
doped amorphous
trench
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007546817A
Other languages
English (en)
Japanese (ja)
Other versions
JP5252417B2 (ja
JP2008523640A (ja
Filing date
Publication date
Priority claimed from US11/011,550 external-priority patent/US7109097B2/en
Application filed filed Critical
Publication of JP2008523640A publication Critical patent/JP2008523640A/ja
Publication of JP2008523640A5 publication Critical patent/JP2008523640A5/ja
Application granted granted Critical
Publication of JP5252417B2 publication Critical patent/JP5252417B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2007546817A 2004-12-14 2005-12-13 深トレンチのドープシリコン充填のプロセスシーケンス Expired - Fee Related JP5252417B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/011,550 2004-12-14
US11/011,550 US7109097B2 (en) 2004-12-14 2004-12-14 Process sequence for doped silicon fill of deep trenches
PCT/US2005/044985 WO2006065776A2 (en) 2004-12-14 2005-12-13 Process sequence for doped silicon fill of deep trenches

Publications (3)

Publication Number Publication Date
JP2008523640A JP2008523640A (ja) 2008-07-03
JP2008523640A5 true JP2008523640A5 (enExample) 2011-08-18
JP5252417B2 JP5252417B2 (ja) 2013-07-31

Family

ID=36584548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007546817A Expired - Fee Related JP5252417B2 (ja) 2004-12-14 2005-12-13 深トレンチのドープシリコン充填のプロセスシーケンス

Country Status (6)

Country Link
US (3) US7109097B2 (enExample)
EP (1) EP1829095A2 (enExample)
JP (1) JP5252417B2 (enExample)
KR (1) KR100930140B1 (enExample)
CN (1) CN100561694C (enExample)
WO (1) WO2006065776A2 (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3998677B2 (ja) * 2004-10-19 2007-10-31 株式会社東芝 半導体ウェハの製造方法
US7109097B2 (en) * 2004-12-14 2006-09-19 Applied Materials, Inc. Process sequence for doped silicon fill of deep trenches
US8012847B2 (en) 2005-04-01 2011-09-06 Micron Technology, Inc. Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
US7344975B2 (en) * 2005-08-26 2008-03-18 Micron Technology, Inc. Method to reduce charge buildup during high aspect ratio contact etch
US7608195B2 (en) * 2006-02-21 2009-10-27 Micron Technology, Inc. High aspect ratio contacts
JP4640221B2 (ja) * 2006-03-10 2011-03-02 セイコーエプソン株式会社 インクカートリッジ及びプリンタ
KR20100040455A (ko) * 2008-10-10 2010-04-20 주식회사 동부하이텍 반도체 소자의 제조 방법
US7943463B2 (en) * 2009-04-02 2011-05-17 Micron Technology, Inc. Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon
CN101859700B (zh) * 2009-04-09 2012-05-30 上海先进半导体制造股份有限公司 多晶硅淀积工艺
JP2010272758A (ja) * 2009-05-22 2010-12-02 Hitachi High-Technologies Corp 被エッチング材のプラズマエッチング方法
US8105956B2 (en) 2009-10-20 2012-01-31 Micron Technology, Inc. Methods of forming silicon oxides and methods of forming interlevel dielectrics
US8293625B2 (en) 2011-01-19 2012-10-23 International Business Machines Corporation Structure and method for hard mask removal on an SOI substrate without using CMP process
KR20130087929A (ko) * 2012-01-30 2013-08-07 에스케이하이닉스 주식회사 트랜치 소자분리층을 갖는 반도체소자 및 그 제조방법
JP6059085B2 (ja) * 2013-05-27 2017-01-11 東京エレクトロン株式会社 トレンチを充填する方法及び処理装置
JP6150724B2 (ja) * 2013-12-27 2017-06-21 東京エレクトロン株式会社 凹部を充填する方法
US9704708B2 (en) 2014-07-11 2017-07-11 Applied Materials, Inc. Halogenated dopant precursors for epitaxy
US20160020094A1 (en) * 2014-07-18 2016-01-21 Asm Ip Holding B.V. Process for forming silicon-filled openings with a reduced occurrence of voids
KR102318197B1 (ko) 2014-09-22 2021-10-26 삼성전자주식회사 씨모스 이미지 센서의 픽셀 및 이를 포함하는 이미지 센서
US9401410B2 (en) * 2014-11-26 2016-07-26 Texas Instruments Incorporated Poly sandwich for deep trench fill
CN105826312B (zh) * 2015-01-04 2019-01-11 旺宏电子股份有限公司 半导体元件及其制造方法
KR101706747B1 (ko) * 2015-05-08 2017-02-15 주식회사 유진테크 비정질 박막의 형성방법
US10468263B2 (en) 2015-12-19 2019-11-05 Applied Materials, Inc. Tungsten deposition without barrier layer
US10991586B2 (en) 2015-12-19 2021-04-27 Applied Materials, Inc. In-situ tungsten deposition without barrier layer
US10480066B2 (en) 2015-12-19 2019-11-19 Applied Materials, Inc. Metal deposition methods
US9768072B1 (en) 2016-06-30 2017-09-19 International Business Machines Corporation Fabrication of a vertical fin field effect transistor with reduced dimensional variations
KR102499035B1 (ko) 2016-07-25 2023-02-13 삼성전자주식회사 반도체 장치의 제조 방법
US20180076026A1 (en) 2016-09-14 2018-03-15 Applied Materials, Inc. Steam oxidation initiation for high aspect ratio conformal radical oxidation
CN110431661B (zh) * 2017-03-31 2023-09-22 应用材料公司 用于用非晶硅膜对高深宽比沟槽进行间隙填充的两步工艺
WO2019013891A1 (en) * 2017-07-12 2019-01-17 Applied Materials, Inc. CYCLIC CONFORMAL DEPOSITION / REINFORCEMENT / ETCHING FOR FILLING INS
WO2019074877A1 (en) * 2017-10-09 2019-04-18 Applied Materials, Inc. DOPED AMORPHOUS SILICON CONFORMS AS A METAL DEPOSITION NUCLEATION LAYER
CN109904057A (zh) * 2017-12-11 2019-06-18 中芯国际集成电路制造(北京)有限公司 半导体装置的制造方法
JP6968011B2 (ja) 2018-03-19 2021-11-17 東京エレクトロン株式会社 成膜方法及び成膜装置
CN109300781B (zh) * 2018-09-11 2020-08-11 上海华虹宏力半导体制造有限公司 Ono膜层的制造方法
TWI768860B (zh) * 2021-04-29 2022-06-21 力晶積成電子製造股份有限公司 沉積製程控制方法
CN113628959B (zh) * 2021-07-19 2024-06-14 华虹半导体(无锡)有限公司 应用于功率器件的沟槽填充方法
CN116110777A (zh) * 2021-11-10 2023-05-12 长江存储科技有限责任公司 掺杂有杂质的硅薄膜、其制备方法以及半导体器件
CN114267642A (zh) * 2021-12-01 2022-04-01 福建省晋华集成电路有限公司 半导体存储装置及其制备方法
CN117238839B (zh) * 2023-11-10 2024-02-09 合肥晶合集成电路股份有限公司 一种浅沟槽隔离结构及其形成方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4528831A (en) * 1980-10-27 1985-07-16 Sleeper & Hartley Corp. Wire coiling machine
US4454646A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
US4473598A (en) * 1982-06-30 1984-09-25 International Business Machines Corporation Method of filling trenches with silicon and structures
US4526631A (en) * 1984-06-25 1985-07-02 International Business Machines Corporation Method for forming a void free isolation pattern utilizing etch and refill techniques
JP2706469B2 (ja) * 1988-06-01 1998-01-28 松下電器産業株式会社 半導体装置の製造方法
US5198387A (en) * 1989-12-01 1993-03-30 Texas Instruments Incorporated Method and apparatus for in-situ doping of deposited silicon
US5256566A (en) * 1991-05-08 1993-10-26 Texas Instruments Incorporated Method for in-situ doping of deposited silicon
JP3181357B2 (ja) * 1991-08-19 2001-07-03 株式会社東芝 半導体薄膜の形成方法および半導体装置の製造方法
JPH07307300A (ja) * 1994-03-15 1995-11-21 Toshiba Corp 凹部内に膜を形成する方法
US6352593B1 (en) 1997-08-11 2002-03-05 Torrex Equipment Corp. Mini-batch process chamber
US20030049372A1 (en) 1997-08-11 2003-03-13 Cook Robert C. High rate deposition at low pressures in a small batch reactor
EP1060287B1 (en) * 1998-03-06 2005-01-26 ASM America, Inc. Method of depositing silicon with high step coverage
JP2000243930A (ja) * 1999-02-22 2000-09-08 Toshiba Corp 半導体装置の製造方法
JP3485081B2 (ja) * 1999-10-28 2004-01-13 株式会社デンソー 半導体基板の製造方法
TW426947B (en) * 1999-12-09 2001-03-21 Mosel Vitelic Inc Method of producing trench capacitor
JP3591823B2 (ja) * 1999-12-27 2004-11-24 株式会社東芝 成膜方法
JP2002299242A (ja) * 2001-03-29 2002-10-11 Fuji Electric Co Ltd 半導体装置の製造方法
US6436760B1 (en) * 2001-04-19 2002-08-20 International Business Machines Corporation Method for reducing surface oxide in polysilicon processing
US6930345B2 (en) * 2001-05-10 2005-08-16 Infineon Technologies Richmond, Lp Increase in deep trench capacitance by a central ground electrode
TW556311B (en) * 2001-07-31 2003-10-01 Infineon Technologies Ag Method for filling trenches in integrated semiconductor circuits
JP3918565B2 (ja) * 2002-01-21 2007-05-23 株式会社デンソー 半導体装置の製造方法
DE10225941A1 (de) * 2002-06-11 2004-01-08 Infineon Technologies Ag Verfahren zur Füllung von Graben- und Reliefgeometrien in Halbleiterstrukturen
DE10234952B3 (de) * 2002-07-31 2004-04-01 Infineon Technologies Ag Herstellungsverfahren für eine Halbleiterstruktur mit einem Graben, insbesondere zur Verwendung bei der Herstellung eines Grabenkondensators
US7494894B2 (en) * 2002-08-29 2009-02-24 Micron Technology, Inc. Protection in integrated circuits
US6815077B1 (en) * 2003-05-20 2004-11-09 Matrix Semiconductor, Inc. Low temperature, low-resistivity heavily doped p-type polysilicon deposition
DE102004020834B4 (de) * 2004-04-28 2010-07-15 Qimonda Ag Herstellungsverfahren für eine Halbleiterstruktur
US7109097B2 (en) * 2004-12-14 2006-09-19 Applied Materials, Inc. Process sequence for doped silicon fill of deep trenches

Similar Documents

Publication Publication Date Title
JP2008523640A5 (enExample)
KR102259262B1 (ko) 유동성 실리콘-함유 막들의 증착
US10854461B2 (en) Tungsten deposition without barrier layer
US6867152B1 (en) Properties of a silica thin film produced by a rapid vapor deposition (RVD) process
JP2020065087A (ja) ＳｉＯＣＮ薄膜の形成
TWI791529B (zh) 包含鈦、矽及氮的多區域擴散阻障
US10096514B2 (en) Seamless trench fill using deposition/etch techniques
JP2020526923A (ja) Ｓｉ間隙充填のための周期的な共形堆積／アニーリング／エッチング
CN104805414A (zh) 半导体器件的制造方法及衬底处理装置
US9312167B1 (en) Air-gap structure formation with ultra low-k dielectric layer on PECVD low-k chamber
US20230230833A1 (en) Method for forming a layer provided with silicon
JP2012049290A (ja) 半導体装置の製造方法及び半導体装置
KR102474163B1 (ko) 실리사이드화에 의한 금속-함유 막들의 부피 팽창
TWI868212B (zh) 利用介電ａｌｄ膜的無縫間隙填充
TW202444944A (zh) 形成矽化鉬之方法
US20180350596A1 (en) Method of depositing doped amorphous silicon films with enhanced defect control, reduced substrate sensitivity to in-film defects and bubble-free film growth
TWI898469B (zh) 具有多孔層的半導體元件
JP7542046B2 (ja) バリア層なしのタングステン堆積物
US20250333837A1 (en) Methods of filling a recessed feature on a substrate employing metal sequential infiltration synthesis processes
KR102869832B1 (ko) 유동성 cvd 막 결함 감소
KR101172311B1 (ko) 반도체 장치 제조방법
KR100548846B1 (ko) 도핑 균일도를 향상시킨 캐패시터의 제조 방법
TW440928B (en) Method for forming a silicon conductive layer by CVD
CN114597159A (zh) 半导体结构的制备方法以及半导体结构
KR20070111709A (ko) 질화지르코늄막의 형성 방법 및 이를 이용하는 반도체장치의 형성 방법 및 이에 의해 형성된 반도체 장치