JP2008513999A5 - - Google Patents

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Publication number
JP2008513999A5
JP2008513999A5 JP2007532334A JP2007532334A JP2008513999A5 JP 2008513999 A5 JP2008513999 A5 JP 2008513999A5 JP 2007532334 A JP2007532334 A JP 2007532334A JP 2007532334 A JP2007532334 A JP 2007532334A JP 2008513999 A5 JP2008513999 A5 JP 2008513999A5
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JP
Japan
Prior art keywords
layer
floating gate
forming
gate
etch stop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007532334A
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English (en)
Japanese (ja)
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JP2008513999A (ja
JP5103182B2 (ja
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Publication date
Priority claimed from US10/944,244 external-priority patent/US7183161B2/en
Application filed filed Critical
Publication of JP2008513999A publication Critical patent/JP2008513999A/ja
Publication of JP2008513999A5 publication Critical patent/JP2008513999A5/ja
Application granted granted Critical
Publication of JP5103182B2 publication Critical patent/JP5103182B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007532334A 2004-09-17 2005-08-15 フローティングゲート素子を形成する方法 Expired - Fee Related JP5103182B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/944,244 2004-09-17
US10/944,244 US7183161B2 (en) 2004-09-17 2004-09-17 Programming and erasing structure for a floating gate memory cell and method of making
PCT/US2005/028828 WO2006036334A2 (en) 2004-09-17 2005-08-15 Programming and erasing structure for a floating gate memory cell and method of making

Publications (3)

Publication Number Publication Date
JP2008513999A JP2008513999A (ja) 2008-05-01
JP2008513999A5 true JP2008513999A5 (enExample) 2008-09-18
JP5103182B2 JP5103182B2 (ja) 2012-12-19

Family

ID=36074588

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007532334A Expired - Fee Related JP5103182B2 (ja) 2004-09-17 2005-08-15 フローティングゲート素子を形成する方法

Country Status (7)

Country Link
US (2) US7183161B2 (enExample)
EP (1) EP1792336A2 (enExample)
JP (1) JP5103182B2 (enExample)
KR (1) KR20070048247A (enExample)
CN (1) CN101432858B (enExample)
TW (1) TWI412085B (enExample)
WO (1) WO2006036334A2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4377676B2 (ja) * 2003-12-24 2009-12-02 株式会社東芝 半導体装置およびその製造方法
US7615445B2 (en) * 2006-09-21 2009-11-10 Sandisk Corporation Methods of reducing coupling between floating gates in nonvolatile memory
US8076229B2 (en) * 2008-05-30 2011-12-13 Micron Technology, Inc. Methods of forming data cells and connections to data cells
CN102282651A (zh) * 2009-01-29 2011-12-14 国际商业机器公司 具有非平面浮动栅极的存储器晶体管及其制造方法
US8415217B2 (en) * 2011-03-31 2013-04-09 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor

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JPH0232539A (ja) * 1988-07-22 1990-02-02 Hitachi Ltd 半導体装置の製造方法及びエッチング方法
JP2908163B2 (ja) * 1993-02-25 1999-06-21 株式会社東芝 半導体装置の製造方法
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US6243289B1 (en) * 1998-04-08 2001-06-05 Micron Technology Inc. Dual floating gate programmable read only memory cell structure and method for its fabrication and operation
KR100318683B1 (ko) * 1998-12-17 2001-12-28 윤종용 산화막/질화막/산화막 유전층의 형성방법
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JP4443008B2 (ja) * 2000-06-30 2010-03-31 富士通株式会社 半導体装置及びその製造方法
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TW463248B (en) * 2000-09-26 2001-11-11 Macronix Int Co Ltd Method for forming gates
JP3984020B2 (ja) * 2000-10-30 2007-09-26 株式会社東芝 不揮発性半導体記憶装置
KR100375231B1 (ko) * 2001-02-19 2003-03-08 삼성전자주식회사 비휘발성 메모리 소자의 제조방법
US6627942B2 (en) 2001-03-29 2003-09-30 Silicon Storage Technology, Inc Self-aligned floating gate poly for a flash E2PROM cell
US6791142B2 (en) 2001-04-30 2004-09-14 Vanguard International Semiconductor Co. Stacked-gate flash memory and the method of making the same
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US6780712B2 (en) 2002-10-30 2004-08-24 Taiwan Semiconductor Manufacturing Company Method for fabricating a flash memory device having finger-like floating gates structure
US6716705B1 (en) 2002-06-03 2004-04-06 Lattice Semiconductor Corporation EEPROM device having a retrograde program junction region and process for fabricating the device
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US6908817B2 (en) * 2002-10-09 2005-06-21 Sandisk Corporation Flash memory array with increased coupling between floating and control gates
KR100454135B1 (ko) 2002-10-10 2004-10-26 삼성전자주식회사 비휘발성 기억소자의 형성방법
KR100482765B1 (ko) * 2002-12-12 2005-04-14 주식회사 하이닉스반도체 플래쉬 메모리 소자의 플로팅 게이트 형성 방법
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US7557042B2 (en) 2004-06-28 2009-07-07 Freescale Semiconductor, Inc. Method for making a semiconductor device with reduced spacing

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