JP2008084959A5 - - Google Patents

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Publication number
JP2008084959A5
JP2008084959A5 JP2006260949A JP2006260949A JP2008084959A5 JP 2008084959 A5 JP2008084959 A5 JP 2008084959A5 JP 2006260949 A JP2006260949 A JP 2006260949A JP 2006260949 A JP2006260949 A JP 2006260949A JP 2008084959 A5 JP2008084959 A5 JP 2008084959A5
Authority
JP
Japan
Prior art keywords
semiconductor chip
wiring pattern
connection terminal
forming
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006260949A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008084959A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2006260949A priority Critical patent/JP2008084959A/ja
Priority claimed from JP2006260949A external-priority patent/JP2008084959A/ja
Priority to KR1020070089769A priority patent/KR20080028279A/ko
Priority to US11/856,354 priority patent/US7884453B2/en
Priority to TW096135326A priority patent/TW200816414A/zh
Priority to CNA2007101541917A priority patent/CN101154641A/zh
Priority to EP07018974A priority patent/EP1906446A2/en
Publication of JP2008084959A publication Critical patent/JP2008084959A/ja
Publication of JP2008084959A5 publication Critical patent/JP2008084959A5/ja
Priority to US12/581,486 priority patent/US8211754B2/en
Pending legal-status Critical Current

Links

JP2006260949A 2006-09-26 2006-09-26 半導体装置及びその製造方法 Pending JP2008084959A (ja)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP2006260949A JP2008084959A (ja) 2006-09-26 2006-09-26 半導体装置及びその製造方法
KR1020070089769A KR20080028279A (ko) 2006-09-26 2007-09-05 반도체 장치 및 그 제조 방법
US11/856,354 US7884453B2 (en) 2006-09-26 2007-09-17 Semiconductor device and manufacturing method thereof
TW096135326A TW200816414A (en) 2006-09-26 2007-09-21 Semiconductor device and manufacturing method thereof
CNA2007101541917A CN101154641A (zh) 2006-09-26 2007-09-24 半导体器件及其制造方法
EP07018974A EP1906446A2 (en) 2006-09-26 2007-09-26 Semiconductor device and manufacturing method thereof
US12/581,486 US8211754B2 (en) 2006-09-26 2009-10-19 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006260949A JP2008084959A (ja) 2006-09-26 2006-09-26 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
JP2008084959A JP2008084959A (ja) 2008-04-10
JP2008084959A5 true JP2008084959A5 (enExample) 2009-08-20

Family

ID=38858918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006260949A Pending JP2008084959A (ja) 2006-09-26 2006-09-26 半導体装置及びその製造方法

Country Status (6)

Country Link
US (2) US7884453B2 (enExample)
EP (1) EP1906446A2 (enExample)
JP (1) JP2008084959A (enExample)
KR (1) KR20080028279A (enExample)
CN (1) CN101154641A (enExample)
TW (1) TW200816414A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101303443A (zh) * 2007-05-11 2008-11-12 鸿富锦精密工业（深圳）有限公司 相机模组及其组装方法
JP2010165940A (ja) * 2009-01-16 2010-07-29 Shinko Electric Ind Co Ltd 半導体素子の樹脂封止方法
US9620455B2 (en) * 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
JP5878054B2 (ja) * 2012-03-27 2016-03-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法及び半導体装置
JP6196893B2 (ja) * 2012-12-18 2017-09-13 新光電気工業株式会社 半導体装置の製造方法
KR101374770B1 (ko) * 2013-11-22 2014-03-17 실리콘밸리(주) 금속 박판의 적층을 이용한 반도체 검사 패드 및 제조방법
CN104576405B (zh) * 2014-12-16 2017-11-07 通富微电子股份有限公司 单层基板封装工艺
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
JP6851239B2 (ja) * 2017-03-29 2021-03-31 エイブリック株式会社 樹脂封止型半導体装置およびその製造方法
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276750A (ja) 1988-04-28 1989-11-07 Matsushita Electric Ind Co Ltd 半導体装置
JP2005328057A (ja) * 1994-03-18 2005-11-24 Hitachi Chem Co Ltd 半導体パッケージの製造法及び半導体パッケージ
JP3030201B2 (ja) * 1994-04-26 2000-04-10 富士通株式会社 半導体装置の製造方法及び半導体装置の製造装置
JP3313547B2 (ja) 1995-08-30 2002-08-12 沖電気工業株式会社 チップサイズパッケージの製造方法
JP3007833B2 (ja) 1995-12-12 2000-02-07 富士通株式会社 半導体装置及びその製造方法及びリードフレーム及びその製造方法
JP3336235B2 (ja) * 1997-08-27 2002-10-21 松下電器産業株式会社 半導体装置およびその製造方法
JP2000164638A (ja) 1998-11-27 2000-06-16 Toshiba Corp 半導体装置
JP3501281B2 (ja) * 1999-11-15 2004-03-02 沖電気工業株式会社 半導体装置
JP2001217354A (ja) * 2000-02-07 2001-08-10 Rohm Co Ltd 半導体チップの実装構造、および半導体装置
JP2001257453A (ja) * 2000-03-09 2001-09-21 Shinko Electric Ind Co Ltd 配線基板、半導体装置及びそれらの製造方法
JP3786339B2 (ja) * 2000-03-23 2006-06-14 株式会社三井ハイテック 半導体装置の製造方法
JP2001298115A (ja) 2000-04-13 2001-10-26 Seiko Epson Corp 半導体装置及びその製造方法、回路基板並びに電子機器
JP4819304B2 (ja) * 2000-10-18 2011-11-24 日本電気株式会社 半導体パッケージ
JP3866033B2 (ja) * 2000-12-14 2007-01-10 シャープ株式会社 半導体装置の製造方法
US7331502B2 (en) * 2001-03-19 2008-02-19 Sumitomo Bakelite Company, Ltd. Method of manufacturing electronic part and electronic part obtained by the method
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP3914239B2 (ja) 2005-03-15 2007-05-16 新光電気工業株式会社 配線基板および配線基板の製造方法
JP5000877B2 (ja) * 2005-10-07 2012-08-15 ルネサスエレクトロニクス株式会社 半導体装置
US7728437B2 (en) * 2005-11-23 2010-06-01 Fairchild Korea Semiconductor, Ltd. Semiconductor package form within an encapsulation
JP2007250834A (ja) * 2006-03-16 2007-09-27 Matsushita Electric Ind Co Ltd 電子部品装置の製造方法
US8072059B2 (en) * 2006-04-19 2011-12-06 Stats Chippac, Ltd. Semiconductor device and method of forming UBM fixed relative to interconnect structure for alignment of semiconductor die
US7666709B1 (en) * 2008-12-10 2010-02-23 Stats Chippac, Ltd. Semiconductor device and method of placing semiconductor die on a temporary carrier using fiducial patterns
US7642128B1 (en) * 2008-12-12 2010-01-05 Stats Chippac, Ltd. Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

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