JP2005260079A5 - - Google Patents
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- Publication number
- JP2005260079A5 JP2005260079A5 JP2004071294A JP2004071294A JP2005260079A5 JP 2005260079 A5 JP2005260079 A5 JP 2005260079A5 JP 2004071294 A JP2004071294 A JP 2004071294A JP 2004071294 A JP2004071294 A JP 2004071294A JP 2005260079 A5 JP2005260079 A5 JP 2005260079A5
- Authority
- JP
- Japan
- Prior art keywords
- groove
- wiring layer
- main surface
- via hole
- pad electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims 35
- 239000010410 layer Substances 0.000 claims 19
- 239000000758 substrate Substances 0.000 claims 9
- 238000004519 manufacturing process Methods 0.000 claims 7
- 238000000034 method Methods 0.000 claims 5
- 239000011241 protective layer Substances 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 1
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071294A JP4282514B2 (ja) | 2004-03-12 | 2004-03-12 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071294A JP4282514B2 (ja) | 2004-03-12 | 2004-03-12 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005260079A JP2005260079A (ja) | 2005-09-22 |
| JP2005260079A5 true JP2005260079A5 (enExample) | 2007-04-19 |
| JP4282514B2 JP4282514B2 (ja) | 2009-06-24 |
Family
ID=35085497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004071294A Expired - Fee Related JP4282514B2 (ja) | 2004-03-12 | 2004-03-12 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4282514B2 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101697573B1 (ko) * | 2010-11-29 | 2017-01-19 | 삼성전자 주식회사 | 반도체 장치, 그 제조 방법, 및 상기 반도체 장치를 포함하는 반도체 패키지 |
| FR2970118B1 (fr) | 2010-12-30 | 2013-12-13 | St Microelectronics Crolles 2 | Puce de circuits integres et procede de fabrication. |
| FR2970119B1 (fr) * | 2010-12-30 | 2013-12-13 | St Microelectronics Crolles 2 Sas | Puce de circuits integres et procede de fabrication. |
| TWI459485B (zh) | 2011-01-17 | 2014-11-01 | 精材科技股份有限公司 | 晶片封裝體的形成方法 |
| SE538058C2 (sv) | 2012-03-30 | 2016-02-23 | Silex Microsystems Ab | Metod att tillhandahålla ett viahål och en routing-struktur |
| CN116344478B (zh) * | 2021-12-24 | 2025-02-25 | 长鑫存储技术有限公司 | 一种半导体结构及半导体结构的制备方法 |
| CN115084082B (zh) * | 2022-07-19 | 2022-11-22 | 甬矽电子(宁波)股份有限公司 | 扇出型封装结构和扇出型封装方法 |
-
2004
- 2004-03-12 JP JP2004071294A patent/JP4282514B2/ja not_active Expired - Fee Related
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