JP2008078660A - 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ - Google Patents

半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ Download PDF

Info

Publication number
JP2008078660A
JP2008078660A JP2007244188A JP2007244188A JP2008078660A JP 2008078660 A JP2008078660 A JP 2008078660A JP 2007244188 A JP2007244188 A JP 2007244188A JP 2007244188 A JP2007244188 A JP 2007244188A JP 2008078660 A JP2008078660 A JP 2008078660A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor wafer
polishing step
polished
less
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007244188A
Other languages
English (en)
Japanese (ja)
Inventor
Klaus Roettger
レットガー クラウス
Vladimir Dutschke
ドゥチュケ ヴラディミール
Leszek Mistur
ミストゥア レシェク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Siltronic AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltronic AG filed Critical Siltronic AG
Publication of JP2008078660A publication Critical patent/JP2008078660A/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
JP2007244188A 2006-09-20 2007-09-20 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ Pending JP2008078660A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102006044367A DE102006044367B4 (de) 2006-09-20 2006-09-20 Verfahren zum Polieren einer Halbleiterscheibe und eine nach dem Verfahren herstellbare polierte Halbleiterscheibe

Publications (1)

Publication Number Publication Date
JP2008078660A true JP2008078660A (ja) 2008-04-03

Family

ID=39133976

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007244188A Pending JP2008078660A (ja) 2006-09-20 2007-09-20 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ

Country Status (7)

Country Link
US (1) US20080070483A1 (zh)
JP (1) JP2008078660A (zh)
KR (2) KR100915433B1 (zh)
CN (1) CN101148025B (zh)
DE (1) DE102006044367B4 (zh)
SG (2) SG141306A1 (zh)
TW (1) TWI336280B (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008044646B4 (de) * 2008-08-27 2011-06-22 Siltronic AG, 81737 Verfahren zur Herstellung einer Halbleiterscheibe
DE102008045534B4 (de) * 2008-09-03 2011-12-01 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe
EP2428984B1 (en) * 2009-05-08 2018-04-11 SUMCO Corporation Semiconductor wafer polishing method
DE102009025243B4 (de) * 2009-06-17 2011-11-17 Siltronic Ag Verfahren zur Herstellung und Verfahren zur Bearbeitung einer Halbleiterscheibe aus Silicium
DE102009030292B4 (de) * 2009-06-24 2011-12-01 Siltronic Ag Verfahren zum beidseitigen Polieren einer Halbleiterscheibe
DE102009037281B4 (de) * 2009-08-12 2013-05-08 Siltronic Ag Verfahren zur Herstellung einer polierten Halbleiterscheibe
DE102009049330B3 (de) * 2009-10-14 2011-02-17 Siltronic Ag Verfahren zum Nachpolieren einer Halbleiterscheibe
US8952496B2 (en) 2009-12-24 2015-02-10 Sumco Corporation Semiconductor wafer and method of producing same
JP5423384B2 (ja) 2009-12-24 2014-02-19 株式会社Ｓｕｍｃｏ 半導体ウェーハおよびその製造方法
DE102010013520B4 (de) * 2010-03-31 2013-02-07 Siltronic Ag Verfahren zur beidseitigen Politur einer Halbleiterscheibe
DE102013201663B4 (de) 2012-12-04 2020-04-23 Siltronic Ag Verfahren zum Polieren einer Halbleiterscheibe
KR101660900B1 (ko) * 2015-01-16 2016-10-10 주식회사 엘지실트론 웨이퍼 연마 장치 및 이를 이용한 웨이퍼 연마 방법
JP6968201B2 (ja) * 2017-12-22 2021-11-17 東京エレクトロン株式会社 基板処理システム、基板処理方法及びコンピュータ記憶媒体
US11145556B2 (en) * 2019-11-21 2021-10-12 Carl Zeiss Smt Gmbh Method and device for inspection of semiconductor samples
JP6885492B1 (ja) * 2020-05-13 2021-06-16 信越半導体株式会社 両面研磨方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05177539A (ja) * 1991-12-24 1993-07-20 Sumitomo Electric Ind Ltd 両面ポリッシュ装置によるウェハ研磨方法
WO2000047369A1 (en) * 1999-02-12 2000-08-17 Memc Electronic Materials, Inc. Method of polishing semiconductor wafers
JP2000235941A (ja) * 1999-02-11 2000-08-29 Wacker Siltronic G Fuer Halbleitermaterialien Ag 半導体ウェハ、半導体ウェハの製造方法および該製造方法の使用
JP2001191249A (ja) * 1999-10-21 2001-07-17 Speedfam Co Ltd ワークの研磨方法
JP2001196334A (ja) * 1999-11-23 2001-07-19 Wacker Siltronic G Fuer Halbleitermaterialien Ag 多数の半導体ウェーハの製造法
JP2005158798A (ja) * 2003-11-20 2005-06-16 Shin Etsu Handotai Co Ltd 半導体ウェーハの両面研磨方法、半導体ウェーハ及びキャリアプレート
JP2006198751A (ja) * 2005-01-24 2006-08-03 Showa Denko Kk 磁気ディスク用サブストレート基板の製造方法及び研磨装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19704546A1 (de) * 1997-02-06 1998-08-13 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer einseitig beschichteten und mit einem Finish versehenen Halbleiterscheibe
DE10007390B4 (de) * 1999-03-13 2008-11-13 Peter Wolters Gmbh Zweischeiben-Poliermaschine, insbesondere zur Bearbeitung von Halbleiterwafern
US6299514B1 (en) * 1999-03-13 2001-10-09 Peter Wolters Werkzeugmachinen Gmbh Double-disk polishing machine, particularly for tooling semiconductor wafers
DE10023002B4 (de) * 2000-05-11 2006-10-26 Siltronic Ag Satz von Läuferscheiben sowie dessen Verwendung
DE10314212B4 (de) * 2002-03-29 2010-06-02 Hoya Corp. Verfahren zur Herstellung eines Maskenrohlings, Verfahren zur Herstellung einer Transfermaske
JP4748968B2 (ja) * 2004-10-27 2011-08-17 信越半導体株式会社 半導体ウエーハの製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05177539A (ja) * 1991-12-24 1993-07-20 Sumitomo Electric Ind Ltd 両面ポリッシュ装置によるウェハ研磨方法
JP2000235941A (ja) * 1999-02-11 2000-08-29 Wacker Siltronic G Fuer Halbleitermaterialien Ag 半導体ウェハ、半導体ウェハの製造方法および該製造方法の使用
WO2000047369A1 (en) * 1999-02-12 2000-08-17 Memc Electronic Materials, Inc. Method of polishing semiconductor wafers
JP2001191249A (ja) * 1999-10-21 2001-07-17 Speedfam Co Ltd ワークの研磨方法
JP2001196334A (ja) * 1999-11-23 2001-07-19 Wacker Siltronic G Fuer Halbleitermaterialien Ag 多数の半導体ウェーハの製造法
JP2005158798A (ja) * 2003-11-20 2005-06-16 Shin Etsu Handotai Co Ltd 半導体ウェーハの両面研磨方法、半導体ウェーハ及びキャリアプレート
JP2006198751A (ja) * 2005-01-24 2006-08-03 Showa Denko Kk 磁気ディスク用サブストレート基板の製造方法及び研磨装置

Also Published As

Publication number Publication date
CN101148025A (zh) 2008-03-26
KR100915433B1 (ko) 2009-09-03
CN101148025B (zh) 2010-06-23
KR20080026485A (ko) 2008-03-25
US20080070483A1 (en) 2008-03-20
SG141306A1 (en) 2008-04-28
KR20090020671A (ko) 2009-02-26
TW200815153A (en) 2008-04-01
TWI336280B (en) 2011-01-21
DE102006044367A1 (de) 2008-04-03
KR100945774B1 (ko) 2010-03-08
DE102006044367B4 (de) 2011-07-14
SG169385A1 (en) 2011-03-30

Similar Documents

Publication Publication Date Title
JP2008078660A (ja) 半導体ウェハを研磨する方法及びその方法に従って製作可能な研磨された半導体ウェハ
TWI567811B (zh) 拋光半導體晶圓兩面的方法
KR101032932B1 (ko) 반도체 웨이퍼 연마법
KR101436482B1 (ko) 반도체 웨이퍼 및 그 제조 방법
WO2006046403A1 (ja) 半導体ウエーハの製造方法及び半導体ウエーハ
US20140264765A1 (en) Semiconductor wafer and method of producing same
JP2011040753A (ja) ポリッシングされた半導体ウェハを製造する方法
KR101240008B1 (ko) 반도체 웨이퍼를 연마하는 방법
US6599760B2 (en) Epitaxial semiconductor wafer manufacturing method
JP3943869B2 (ja) 半導体ウエーハの加工方法および半導体ウエーハ
US11456168B2 (en) Method of lapping semiconductor wafer and semiconductor wafer
JP5167207B2 (ja) 半導体ウェハの製造方法
JP2021536140A (ja) パッド−パッド変動のために調整を行う半導体基板の研磨方法 （関連出願の相互参照） 本願は、２０１８年９月１０日に出願された米国仮特許出願第６２／７２９，１３４号の優先権の利益を主張する。当該米国仮特許出願の開示内容は、全ての関連性および一貫性のため（ｆｏｒ ａｌｌ ｒｅｌｅｖａｎｔ ａｎｄ ｃｏｎｓｉｓｔｅｎｔ ｐｕｒｐｏｓｅｓ）参照により本明細書中に組み込まれる。
JP2004022677A (ja) 半導体ウエーハ
JP7276246B2 (ja) 両面研磨装置用キャリアの製造方法及びウェーハの両面研磨方法
JP2010010358A (ja) 半導体ウェーハの製造方法
KR20090070330A (ko) 나노토포그라피가 개선된 웨이퍼 제조 방법
KR20080063641A (ko) 에피텍셜 웨이퍼의 제작 방법

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101217

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101227

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20101228

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20110314

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20110317

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110706