TW200815153A - Method for polishing a semiconductor wafer and polished semiconductor wafer producible according to the method - Google Patents

Abstract

The invention relates to a method for polishing a semiconductor wafer between an upper polishing plate and a lower polishing plate, the semiconductor wafer being polished on both sides while lying in a recess of a carrier by supplying a polishing agent. The method comprises double-sided polishing off the semiconductor wafer in a first polishing step, which is concluded with a negative overhang, the overhang being the difference between the thickness of the semiconductor wafer and the thickness of the carrier after the first polishing step, and double-sided polishing of the semiconductor wafer in a second polishing step, in which less than 1 μm of material is polished from the side surfaces of the semiconductor wafer. The invention also relates to a silicon semiconductor wafer having a polished front side and a polished rear side with a front side global planarity expressed by an SBIRmax value of less than 100 nm, and with a front side local planarity expressed by a PSFQR value of 35 nm or less in an edge region, an edge exclusion of 2 mm being considered in each case.

Description

200815153 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD The present invention relates to a method of polishing a semiconductor wafer, in particular a germanium semiconductor wafer, with the object of providing a flattening in the edge region that has not been achieved to date. Improved semiconductor wafers. More particularly, the present invention relates to a method of polishing a semiconductor wafer between an upper polishing disk and a lower polishing disk. The semiconductor wafer is placed in a cavity of a carrier by polishing a semiconductor by providing a polishing agent. Wafer, the present invention also relates to a semiconductor wafer, particularly a material conductor wafer, having improved flatness with a local front side least squares focal (site front side least squares focal) The piane range (SFQR) and the partial backside ideal f〇cal ρ1_ (SBIR) are expressed. [Prior Art]

The flatness of a semiconductor wafer is an important quality parameter that is used to evaluate the suitability of a semiconductor wafer as a substrate for the fabrication of the latest generation of electronic components. An ideal flattened semiconductor wafer having sides that are parallel to each other and completely flat will not produce stepper focus during fabrication of the lithography (4) of the component. This person tries to get as close as possible to the ideal shape. To this end, the semiconductor wafers that have been physically separated are subjected to a series of processing steps, which are mechanically modified by grinding and/or grinding the sides to form them at the beginning. Subsequent steps such as semiconductor wafer stenciling and side polishing are mainly used for (iv) machining/sampling (4) damage and for smoothing the sides. At the same time, these subsequent steps determine the influence of the semiconductors and the goal of the financial efforts is to achieve the flatness achieved by the machining process. It is known that this target can be double-sided polished by combining simultaneous semiconductor wafers. While most effectively achieved, the double-sided polishing is referred to below as DSP polishing. A suitable Dsp polishing machine is described, for example, in de 100 07 390 A1. During DSP polishing, the semiconductor wafer is located in a guide cage (two In a cavity of a carrier such as a cage, and between an upper polishing disk and a lower polishing disk, the cavity is provided for the semiconductor wafer. The at least one polishing disk and the carrier are rotated, and when provided In the case of a polishing agent, the semiconductor wafer is moved relative to the polishing disk covered with the polishing cloth on a φ carrier predetermined by the rolling cam. The polishing pressure and polishing duration of the polishing disk pressed on the semiconductor wafer are collectively determined by polishing. Key parameters of the resulting material removal. DE 199 56 250 C1 describes a method in which a machined and etched germanium semiconductor wafer system is used. It is first polished by DSp and then quality-controlled, and its flatness is checked in the quality system and compared with the set value. If the required flatness has not been reached, it is re-polished with another shorter Dsp finish. 00/47369, the DSP polishing system is performed in the first polishing step to spring the semiconductor wafer to a concave shape different from the ideal shape. Then, the concave shape of the polished side surface is eliminated by the early polishing, the single Face polishing is hereinafter referred to as CMP polishing. This is due to the fact that (4) cMp polishing on the flat side has a tendency to produce a - convexly polished side, so if the side to be polished is in the shape of a concave surface, then CMP A flat side can be produced after polishing. As the inventors of the present invention have determined, the above-mentioned method has the disadvantage that the method can be used to reduce the flatness of the wafer at the edge of the wafer. "The local flatness achieved by DSp polishing in the domain. But the wafer edge 7 200815153 edge area is more and more important for the manufacturers of electronic components, because people try to benefit The use of conventional edge exclusion expands the usable area of the polished side, which is referred to below as FQA (Fixed Quality Area), which is excluded from EE (Edge Exclusion). The unevenness of the side surface in the edge region is especially attributed to the edge drop, which is referred to below as Er〇(Edge R〇ll-〇ff). Kimura et al.

J. AppL

Phys.), vol. 38 (1999), pp. 38-39, states that ER〇 can be derived from the SFQR value of the local region (pai1ial φ sltes). The SFQR value describes the local flatness of a measurement area of a certain size (for example, an area of 20 mm χ 20 mm), specifically in the form of a maximum height deviation of the front surface of the semiconductor wafer from a reference surface having the same size, This maximum face deviation is obtained by a least squares minimization force α. The local area is the measurement area in the edge area, which is no longer part of the FQA, but the center of these measurement areas is still in the FQA. The SFQR value of the local zone is hereinafter referred to as the partial site frontside least squares focal plane range j PSFQR) φ In addition to the local flatness, the overall flatness must still be considered, especially since CMP polishing during component fabrication requires good overall flatness. The normalized parameters used for this estimate are the global backside ideal focal plane range (GBIR) values and the SBIR values associated therewith. These two values represent the maximum height deviation of the front side of the semiconductor wafer relative to the back side that is supposed to be ideally flat and differ in that it is calculated in FQA in the case of GBIR values and is limited in measurement in the case of SBIR values. The area of the area is calculated. If the definitions provided here differ from the definitions of the SEMI standard, in particular the definitions of the standards M59, Ml and 8 200815153 M1530 in the current version, the definition of the standard has priority. It is an object of the present invention to provide a method for polishing a semiconductor wafer that comprehensively improves the flatness of the semiconductor wafer and that is not unsuitable for the flatness of the semiconductor wafer or especially in the edge region The invention relates to a method for polishing a semiconductor wafer between an upper polishing disk and a lower polishing disk, wherein the semiconductor wafer is located in a cavity of a carrier, The semiconductor wafer is polished on both sides by providing a polishing agent, the method comprising: polishing the semiconductor wafer on both sides in a first polishing step, the step ending with a negative protrusion, the protruding finger a difference between the thickness of the semiconductor wafer and the thickness of the carrier after the first polishing step; and polishing the semiconductor wafer on both sides in a second polishing step, wherein the semiconductor wafer is removed from the side of the semiconductor wafer The material is less than 1 micron. • By this method, the local flatness (especially the local flatness in the edge region) achieved after the first polishing step is successfully maintained in the second polishing step and the overall flatness is improved, wherein the overall is satisfied The flatness required by a 7L piece with a line width of 32 nanometers (nm). This is an unexpected result, as the methods described in the above-mentioned DE 199 56 250 C1 and w〇 〇〇/47369 do not achieve this effect. In the case of DE 199 56 25 〇 C1, although the local flatness set in the first polishing step is maintained after the second polishing step, the overall flatness achieved in the first polishing step is in the second Reduced during the polishing step. In the case of 69, the first polishing step reduces the local flatness (especially the local flatness in the edge region) of the 9 200815153 achieved by the first light-removing step. The germanium semiconductor wafer fabricated in accordance with the method of the present invention has a flatness that was previously unachievable. Accordingly, the present invention is also directed to a germanium semiconductor wafer having a polished front side and a polished back side, and having a maximum surface backside ideal focal plane range (SBIRmax) less than 100 nm (nm) of the overall flatness of the front side, and in one edge region has a frontal partial flatness of not more than 35 nanometers (nm) expressed in PSFQR値, 0 in each case considering the edge of 2 mm exclude. In addition, the SBIRmax value is for a measurement area of 26 mm χ 33 mm and a measurement area grid setting with an offset of 13 及 and 16.5 mm in the sense and y directions. The smRmax value is the maximum SBIR value in all measurement zones. The specification of the PSFQR value is for a measurement area of 2 mm mm x 20 mm and an S-zone grid setting with an offset of 1 mm in both the sense and y directions. PSQR is obtained by dividing the sum of the PSFQR values of the local regions by their number. The initial product of the method is preferably a crystal, which is preferably a semiconductor wafer that is separated by a single crystal, which is machined in a manner that is ground and/or ground on its side (ie, , the front and back of the semiconductor wafer). The front side refers to a side surface for forming a surface for providing an electronic component structure. The edges of the semiconductor wafer can be rounded to reduce the sensitivity of the semiconductor wafer to impact damage. In addition, the surface damage caused by the prior mechanical plus X has been largely eliminated by making a residual in an acidic and/or silvery silver engraving agent. In addition, the semiconductor wafer can be subjected to other processing steps, particularly S cleaning steps or edge polishing. According to the method, the semiconductor wafer is simultaneously polished on both sides in the first polishing step, wherein in order to improve productivity, (4) 200815153 polishing is preferably performed by multi-wafer polishing, in which the plurality of wafers are polished. Each of these carriers has a plurality of cavities for the semiconductor wafer. The DSP polished - (four) Μ produces - negative bulge, wherein the bulging system, refers to the difference between the wafer thickness and the polished semiconductor wafer = (Dlw hunger). The bulge of the bulge is preferably from Ημm to Γ4 Μm, especially preferably less than _〇·5 microns to _4, and the like is not to be tested, and the total material removal from the side is better. For 15 micron to 30 micro. The utility of the first-polishing step is to cause the semiconductor wafer to be concavely curved in a horizontally symmetric manner such that the sbir value is within a range of greater than 100 r nm, dip, and target that is considered unfavorable; and the semiconductor wafer is described The SFQR value of the local flatness, especially the DSFQR value, is already in the range of no more than 35 nanometers (nm) which is considered to be advantageous. The second polishing step, also performed by polishing, aims to improve the overall flatness and to maintain or improve the local flatness that has been achieved, especially the local flatness of the marginal area. (d) Two gift-spraying - A special feature is that the desired effect is achieved by throwing material less than 1 micron from both sides of the semiconductor wafer. The average material removal is - in the range of less than i microns - preferably from 0.2 microns to less than! Within the micrometer range. The upper limit given 値 should not be exceeded because it will adversely affect the overall flatness of the Semiconductor Crystal®. The car is preferably advertised to a depth of not less than 〇 micron, wherein the embossed semiconductor wafer thickness D2W and the thickness of the carrier for polishing the semiconductor wafer, the value D2W_; D2L. The protrusion is particularly preferably from 〇 micron to 2 microns. The political use of the second polishing step is that the SBIR value is within the range of _ is considered to be favorable less than the range of the nanometer, and the local flatness degree SFQR value is described, in particular, the psFQR value is in a favored Within the range of 35 nanometers (nm). [Embodiment] According to a preferred embodiment of the present invention, the thus obtained semiconductor wafer concavity is measured after the first polishing step, for example, by measuring a 4G embrittlement value. The measured value is used as an input parameter for calculating the duration of the second polishing step, by which the amount of material removal to be achieved by the second polishing step is determined. In this way, the flatness of the semiconductor wafer is further optimized. The optimum duration d of the second polishing step is preferably calculated according to the following formula: D = (GBIR : RT) + 〇 ffset, where the typical removal rate of the polishing machine used in RT 以 in micrometers per minute, It is a correction value that is related to the polishing process used and therefore must be determined empirically. The invention will be described in detail below by means of the drawings and comparative examples. Figures 1A through 1C illustrate semiconductor wafers located within a disc at different times of the method of the present invention. At the time a) (Fig. 1A) at which the first DSP polishing starts, the semiconductor wafer 1 has a thickness DW which is greater than the thickness D1L of the carrier 21. In the polishing step, the semiconductor wafer is polished between an upper polishing disk 3 and a polished 4 φ using a specific polishing pressure and a polishing agent until the time b is reached (Fig. 16). At the moment, the difference between the polished semiconductor wafer thickness 〇1^ and the carrier 21 thickness D1L becomes a negative value. The semiconductor wafer is then subjected to a second DSP polishing by the carrier 22, which is finished at time c) (Fig. (1)). The differences between the first polishing step and the second polishing step are illustrated in Figures 2 and 3, which show linear scans along the diameter of the semiconductor wafer. After the first polishing step (Fig. 2), the semiconductor wafer has a concave shape which is substantially due to the bulging of the material 12 200815153 in an area extending inwardly by about 100 mm. There is only a slight edge drop on the outer edge of the FQA. The concavity of the semiconductor wafer makes the overall flatness unsatisfactory. This is changed after the second polishing step (Fig. 3), which utilizes the initial effect of double-sided polishing, that is, the material protrusions which adversely affect the overall flatness are preferentially eliminated, and the edge regions thereof are maintained. The local flatness in the middle is not affected. EXAMPLES AND COMPARATIVE EXAMPLES A germanium semiconductor wafer having a diameter of 300 mm was divided from a single crystal and was each pretreated by machining and etching in the same manner. Next, these semiconductor wafers were polished in a double-sided polisher model AC 2000 produced by Peter Wolters AG until a negative bulge (underhang) (example E and comparative example C2) or until a positive Protrusion (Comparative Example C1). A portion of the semiconductor wafer (C1) is then subjected to a second DSP polishing that ends with a positive protrusion and a material removal greater than 1 micrometer. Another portion of the semiconductor wafer (C2) is subjected to a CMP polishing. The CMP polishing ends with a material removal of less than 1 micron. The remaining portion of the semiconductor wafer (13) is also subjected to a second DSp polishing which ends with a small amount of material removal of 1 micron. The flatness measurement results of the non-contact measuring instruments of the AFS type produced by ade after these polishing steps are compiled in the following table. Parameters for SBIR measurement and SFqr measurement: FQA=296 mm EE=2 mm Parameters for SBIR measurement: Measurement area = 26 mm X 33 mm 13 200815153 Offset of the grid in the X direction = 13 mm The offset of the grid area in the y direction is 26.5 mm. Parameters for PSFQR measurement: Area of measurement area = 20 mm χ 20 mm Offset of grid area in the X direction = 10 mm Grid in the y direction Grid offset = 10 mm Table: First polishing step Material removal [μm] Protrusion [μm] GBIR [μm] SBIRmax [μm] PSFQR [μm] C1 26.8 + 1.3 0.51 0.27 0.090 C2, E 27.6 - 2.7 0.78 0.19 0,034 Second polishing step Bimaterial removal [μm] Convex [μm] GBIR [μm] SBIRmax [μm] PSFQR [μm] C1 4.3 + 1.0 0.76 0.43 0.060 _ C2 0.3 0.93 0.23 0.059 E 0.72 0.56 0.111 0.08 0.035 [Simple Description of the Drawings] Figures 1A to 1C are schematic views of semiconductor wafers located in a polishing disk at different times of the method of the present invention. Figure 2 is a linear scan of the radius along the semiconductor wafer after the first polishing step in accordance with the present invention. Figure 3 is a linear scan of the radius of 14 200815153 along the semiconductor wafer after the second polishing step in accordance with the present invention. [Main component symbol description] 1 Semiconductor wafer 3 Upper polishing disk 4 Lower polishing disk 21, 22 Carrier

Claims (1)

200815153 X. Patent application scope: A method of semiconductor wafer, a difference between the thickness of the semiconductor wafer and the thickness of the carrier; and 1 - polishing between the upper polishing disk and the lower polishing disk in a second polishing step, wherein the semiconductor wafer is double-sided polished The material thrown off the sides of the semiconductor wafer is less than 丨 microns. Negative bulging from micron to -4 micron is the end. 3. The method of claim 1 or 2, wherein the material thrown from the side of the semiconductor wafer in the second polishing step is in the range of 〇 2 μm to less than 丨 μm. Or the method of 2, wherein the concavity of the semiconductor wafer is measured after the first polishing step, and the polishing wear generated in the second polishing step is dependent on the measured concavity. 5. A Shixi semiconductor wafer having a polished front side and a polished back side, the semiconductor wafer having a maximum site backside ideal f0cai piane range (SBIRmax) of less than 100 The positive flatness of the front side of the nanometer (nm), and having a frontal least squares focal plane range (PSFQR) in the edge region is not more than 35 nanometers (nm). The positive local flatness of each side is considered to be excluded in the edge of 2,16,2008,15,153 meters in each case. 6. The semiconductor wafer of claim 5, having a diameter of 200 mm or 300 mm.