KR20080026485A - Method for polishing a semiconductor wafer and polished semiconductor wafer producible according to the method - Google Patents

Abstract

A method for polishing a semiconductor wafer and the semiconductor wafer polished by the same are provided to prevent the local planarity or the global planarity from being excessively damaged in an edge region of the semiconductor wafer. A semiconductor wafer(1) is polished between an upper polishing plate(3) and a lower polishing plate(4), while both sides of the semiconductor wafer lying in recesses of carriers(21,22) are polished by supplying a polishing agent. When polishing the both sides of the semiconductor wafer, an overhang which is a difference between the thickness of the semiconductor wafer and the thickness of the carrier is concluded with a negative overhang. After that, material of 1 micrometer or less is polished from the side surfaces of the semiconductor wafer.

Description

METHOD FOR POLISHING A SEMICONDUCTOR WAFER AND POLISHED SEMICONDUCTOR WAFER PRODUCIBLE ACCORDING TO THE METHOD}

The present invention relates to a method of polishing a semiconductor wafer, in particular a silicon semiconductor wafer, in order to provide a semiconductor wafer having an improved flatness which has never been achieved, especially in the edge region. Specifically, the present invention relates to a method of polishing a semiconductor wafer, wherein both sides of the semiconductor wafer are polished by supplying a polishing agent between the upper polishing plate and the lower polishing plate with the semiconductor wafer disposed in the recess of the carrier. And a semiconductor wafer, in particular a silicon semiconductor wafer, having improved flatness expressed in the form of SFQR values and SBIR values.

Flatness of semiconductor wafers is a major quality parameter that evaluates the basic suitability of semiconductor wafers as substrates for manufacturing the latest generation of electronic devices. Ideally flat semiconductor wafers with generally flat surfaces lying parallel to each other will not cause difficulty in focusing for the stepper during lithography for the fabrication of the device. Thus, attempts have been made to approximate the ideal shape as much as possible. To this end, the semiconductor wafer cut from the crystal is subjected to a series of processing steps, in which the mechanical processing performed at the beginning of the processing functions to shape the surface by lapping and / or grinding. Subsequent steps, such as etching the semiconductor wafer and polishing the face, are primarily performed to remove the surface damage imparted by the mechanical machining step and to smooth the face. At the same time, such subsequent steps will decisively affect the flatness of the semiconductor wafer, and all efforts are aimed at maintaining the flatness achieved by the mechanical processing step as much as possible. It is known that this object can be achieved by adopting double-side polishing of a semiconductor wafer, which will be simultaneously referred to hereinafter as DSP polishing. Suitable machines for DSP polishing are for example disclosed in DE 100 07 390 A1. During DSP polishing, the semiconductor wafer is placed in a recess for the semiconductor wafer of the carrier which functions as a guide cage, and is placed between the upper polishing plate and the lower polishing plate. At least one polishing plate and carrier are rotated and the semiconductor wafer is moved on a predetermined path by a milling curve for the polishing plate covered with a polishing cloth while the polishing agent is supplied. The polishing pressure and the polishing time when the polishing plate is pressed on the semiconductor wafer together are important parameters that determine the material polishing caused by polishing.

In the method disclosed in DE 199 56 250 C1, a silicon semiconductor wafer that has been machined and etched is first subjected to DSP polishing, followed by a quality check to test flatness and compare it with a set point. If the required flatness is not yet achieved, it is polished again by further shorter DSP polishing.

According to WO 00/47369, DSP polishing is performed to give the semiconductor wafer a concave shape different from the ideal shape in the first polishing step. The concave shape of the polished face is removed by subsequent one side polishing, hereinafter referred to as CMP polishing. This takes advantage of the fact that CMP polishing applied to a flat face tends to provide a convex polished face, so that CMP polishing can produce a flat face if the face to be polished is concave.

According to the inventors of the present invention, the above-described method has the disadvantage that only the flatness of the surface in the edge region of the wafer can be achieved insufficiently. Thus, CMP polishing reduces the local planarity already achieved by DSP polishing in such areas. However, for electronic device manufacturers, the available area of the polished face, hereinafter referred to as fixed quality area (FQA), is sacrificed at the expense of conventional edge exclusion (hereinafter referred to as EE). The edge area of the wafer is considered very important in that it is attempting to expand. In particular, edge roll-off, referred to as ERO, contributes to non-flatness of the face in the edge region of the semiconductor wafer. Kimura et al. Jpn. J. Appl. Phys. Vol 38, pp. 38-39 (1999), suggests that ERO can be derived from SFQR values of partial sites. The SFQR value represents the local flatness in the measurement zone with a specific size, for example an area of 20 mm x 20 mm, specifically the front face of the semiconductor wafer from the same size reference plane obtained by least square minimization. Is represented in the form of a maximum height deviation. The partial region no longer completely forms part of the FQA but the center is the measurement zone in the edge region still lying within the FQA. The SFQR value of the partial region will hereinafter be referred to as the PSFQR value.

In addition to local flatness, global flatness also needs to be considered at the same time, particularly in that CMP polishing requires good global planarity during device fabrication. Standardized parameters for such evaluations are GBIR and SBIR values that are related to each other. These two values are expressed as the maximum height deviation of the front face with respect to the back face of the semiconductor wafer, which is assumed to be the ideal plane. For GBIR values, FQA is used for calculation, and for SBIR values, the limited area in the measurement area is used for calculation. The difference is that it is used. If the definitions given herein differ from the definitions in the SEMI standard, in particular the M59, M1 and M1530 standards in the current version, the definition of such standard should take precedence.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor wafer polishing method which improves the flatness of a semiconductor wafer as a whole, but does not excessively impair local or global flatness, particularly in the edge region of the semiconductor wafer.

The present invention is a polishing method of a semiconductor wafer which polishes both surfaces of the semiconductor wafer by supplying a polishing agent between the upper polishing plate and the lower polishing plate with the semiconductor wafer disposed in the recess of the carrier.

In the first polishing step, after the first polishing step, the semiconductor wafer is double-sided polished such that an overhang, which is a difference between the thickness of the semiconductor wafer and the thickness of the carrier, is completed in a negative state,

In a second polishing step, polishing the semiconductor wafer on both sides such that less than 1 μm of material is polished from the sides of the semiconductor wafer.

In this method, the local flatness achieved after the first polishing step, especially in the edge region, is preserved in the second polishing step, and the global flatness can be improved, so that the requirements of the generation of devices having a line width of 32 nm To achieve a flatness as a whole to meet. This is a surprising result in that it is impossible with the method disclosed in DE 199 56 250 C1 described above and the method disclosed in WO 00/47369 described above. In the case of DE 199 56 250 C1, the local flatness obtained in the first polishing step is preserved even after the second polishing step, but the global flatness achieved in the first polishing step decreases in the second polishing step. In the case of WO 00/47369, the local flatness achieved in the first polishing step, in particular in the edge area, is reduced in the second polishing step.

Silicon semiconductor wafers produced by the method according to the invention have flatness that has not been attainable in the past. Thus, the front of which the present invention also when having a polished front and back side polishing, each given the extreme edge inclusion of 2㎜ less than the global flatness of the front 100㎚ also expressed in SBIR _max is expressed in PSFQR Local flatness relates to a silicon semiconductor wafer having 35 nm or less in the edge region. The SBIR _max value also relates to the area of the measuring zone of 26 × 33 mm and to the arrangement of the measuring zone grid offset by 13 mm and 16.5 mm in the x and y directions. The SBIR _max value means the SBIR value of the measurement zone having the maximum value of all the measurement zones. The PSFQR value concerns the area of the measuring zone of 20 x 20 mm and the arrangement of the measuring zone grids offset by 10 mm in the x and y directions. The PSQR value is given by dividing the sum of the PSFQR values of the partial regions by the number of partial regions.

Preferred products for starting the method are semiconductor wafers cut from crystals, in particular silicon single crystals, and machined by lapping and / or grinding their faces, ie front and back. The front face refers to the face that is intended to form a surface that provides a structured electronic device. The edges of the semiconductor wafer may have already been rounded to make them less susceptible to impact damage. In addition, surface damage due to previous machining was substantially eliminated by etching in acidic and / or alkaline etchant. In addition, the semiconductor wafer may have already undergone additional processing steps, in particular a cleaning step or an edge polishing step. According to the method of the present invention, the semiconductor wafer is polished on both sides simultaneously in the first polishing step, and in this case, in order to improve productivity, the DSP polishing is performed by using multiple wafers each having a plurality of carriers each having a plurality of recesses for the semiconductor wafer. Preference is given to performing as polishing. A special feature of the first DSP polishing is that the overhang, which is the difference (D1W-D1L) between the thickness D1W of the semiconductor wafer after the polishing is completed and the thickness D1L of the carrier used for polishing the semiconductor wafer, becomes negative. to be. The overhang is preferably less than 0 µm to -4 µm, particularly preferably -0.5 µm to -4 µm, and preferably a material of 15 µm to 30 µm is polished over the entire surface. The result of the first polishing step is that the semiconductor wafer is curved concave in a horizontal symmetrical shape so that the SBIR value is considered to be undesirably greater than 100 nm, and the SFQR value, in particular the PSFQR, indicating local flatness of the semiconductor wafer. The value is already in the preferred range of 35 nm or less. Similarly, the goal of the second polishing step performed with DSP polishing is not only to improve global flatness, but also to preserve or likewise improve the local flatness already achieved, especially in the edge region. A special feature of the second DSP polishing is that the desired result is achieved by polishing a material of less than 1 μm overall from both sides of the semiconductor wafer. Average material polishing is in the range of less than 1 μm, preferably in the range of 0.2 μm to less than 1 μm. It should not exceed the stated upper limit in that it may adversely affect the global flatness of the semiconductor wafer. Further, it is preferable that the overhang, which is the difference (D2W-D2L) between the thickness D2W of the semiconductor wafer after such polishing is completed and the thickness D2L of the carrier used for polishing the semiconductor wafer, is ≧ 0 μm. It is particularly preferable that the overhang is 0 to 2 mu m. The result of the second polishing step is that the SBIR value is within the range considered to be less than 100 nm preferred, and that the SFQR value exhibiting local flatness, in particular the PSFQR value, is within the range considered to be desirable below 35 nm.

According to a preferred embodiment of the present invention, the concavity of the semiconductor wafer thereby achieved after the first polishing step is determined by measuring the GBIR value, for example. Using the measured value as an input value, the duration of the second polishing step is calculated, thereby setting the material polishing to be achieved in the second polishing step. In this way, the flatness of the semiconductor wafer is further optimized. The optimal duration D of the second polishing step is determined according to the following equation.

D = (GBIR: RT) + Offset

Here, RT is a normal polishing rate expressed in µm / min of the polishing machine used, and Offset is a correction value, which needs to be determined empirically depending on the polishing process used.

According to the present invention, there is provided a semiconductor wafer in which the flatness of the semiconductor wafer as a whole has been improved, but in particular, local or global flatness is not excessively damaged in the edge region of the semiconductor wafer.

The invention will be described in more detail below with reference to the drawings and comparative examples.

Figure 1 schematically shows a semiconductor wafer sandwiched between polishing plates at various times in the method according to the invention. At time a) at the beginning of the first DSP polishing step, the semiconductor wafer 1 has a thickness D1W that is greater than the thickness D1L of the carrier 21. The semiconductor wafer is top polished by using a specific polishing pressure while supplying a polishing agent until the time b) when the difference between the thickness D1W of the semiconductor wafer polished in the first polishing step and the thickness D1L of the carrier becomes negative. Polished between plate 3 and lower polishing plate 4. This semiconductor wafer is then subjected to a second DSP polishing with carrier 22 completed at time c).

2 and 3 show a line scan along the diameter of the semiconductor wafer as showing different results of the first and second polishing steps. After the first polishing step (see FIG. 2), the semiconductor wafer has a concave shape due to the raised material in the region extending substantially inwards to about 100 mm. Only a slight edge roll off is still at the outer edge of the FQA. Global flatness is not satisfactory as a result of the concaveness of the semiconductor wafer. This is changed after the second polishing step (see FIG. 3) using the initial effect of double-side polishing, in other words, the raised areas that adversely affect global flatness are preferentially removed and the local flatness in the edge area is It remains virtually unaffected.

Examples and Comparative Examples

Silicon semiconductor wafers having a diameter of 300 mm were cut from single crystals and subjected to pretreatment by machining and etching in the same manner, respectively. Subsequently, these wafers were then used in a Perter Wolters AG AC 2000 type double side polishing machine until the negative overhang (ie underhang) was reached (Example E or Comparative Example C2) or when the positive overhang was reached. Polished to (Comparative Example C1). Some of the semiconductor wafers (Comparative Example C1) were then subjected to a second DSP polishing that was completed with a positive overhang and material polishing greater than 1 μm. Another semiconductor wafer (Comparative Example C2) was subjected to CMP polishing, which was completed with material polishing of less than 1 μm. The remaining semiconductor wafers (Example E) likewise undergo a second DSP polishing, which is completed with material polishing of less than 1 μm. The flatness measurement result performed using the AFS type contactless measuring device of ADE Corp. after a polishing step is shown in Table 1 below.

Parameters for SBIR and SFQR Measurements:

FQA = 296 mm

EE = 2 mm

Parameters for SBIR Measurements:

Area of the measuring zone = 26 mm × 33 mm

Offset of grid zone in x direction = 13 mm

offset of the grid zone in the y direction = 16.5 mm

Parameters for PSFQR Measurements:

Measuring Area Area = 20 mm × 20 mm

Offset of grid zone in x direction = 10 mm

offset of the grid zone in the y direction = 10 mm

First polishing step Polishing material [µm] Overhang [μm] GBIR [μm] SBIR _max [μm] PSFQR [μm] C1 26.8 +1.3 0.51 0.27 0.090 C2, E 27.6 -2.7 0.78 0.19 0.034 Second polishing step Polishing material [µm] Overhang [μm] GBIR [μm] SBIRmax [μm] PSFQR [μm] C1 4.3 +1.0 0.76 0.43 0.060 C2 0.3 ----- 0.93 0.23 0.059 E 0.72 0.56 0.111 0.08 0.035

1 is a schematic representation of a semiconductor wafer sandwiched between polishing plates at various times in a method according to the invention.

2 and 3 show different effects of the first and second polishing steps.

<Explanation of symbols for the main parts of the drawings>

1: semiconductor wafer

3: top polishing plate

4: bottom polishing plate

21: carrier

22: carrier

Claims (6)

A method of polishing a semiconductor wafer, wherein both sides of the semiconductor wafer are polished by supplying a polishing agent between the upper polishing plate and the lower polishing plate with the semiconductor wafer disposed in the recess of the carrier. In the first polishing step, after the first polishing step, the semiconductor wafer is double-sided polished such that an overhang, which is a difference between the thickness of the semiconductor wafer and the thickness of the carrier, is completed in a negative state, In a second polishing step, polishing the semiconductor wafer on both sides such that less than 1 μm material is polished from the sides of the semiconductor Polishing method of a semiconductor wafer comprising a. The method of claim 1, wherein the first polishing step is completed with a negative overhang of less than 0 μm to −4 μm. The method of polishing a semiconductor wafer according to claim 1 or 2, wherein less than 0.2 [mu] m to less than 1 [mu] m of material is polished from the surface of the semiconductor wafer in the second polishing step. The semiconductor wafer according to claim 1, wherein the concaveness of the semiconductor wafer is measured after the first polishing step, and polishing polishing performed in the second polishing step is performed depending on the measured concaveness. Polishing method. With a polished front side and a polished back side, each of which considers edge exclusion of 2 mm, the global planarity of the front face, expressed as SBIR _max , is less than 100 nm and is expressed in PSFQR. A silicon semiconductor wafer, wherein the local flatness of the front face is 35 nm or less in the edge region. The silicon semiconductor wafer of claim 5, having a diameter of 200 mm or 300 mm.

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