JP4352229B2 - Semiconductor wafer double-side polishing method - Google Patents

Description

  The present invention relates to a double-side polishing technique for a semiconductor wafer such as a silicon wafer (hereinafter sometimes simply referred to as a wafer), and more particularly to a double-side polishing method for a semiconductor wafer that can easily reduce the peripheral sag of a semiconductor wafer to be processed.

  Conventionally, a method for manufacturing a semiconductor wafer used as a semiconductor substrate material used for a memory device or the like is generally a single crystal ingot using a Czochralski (CZ) method, a floating zone (FZ) method, or the like. And a wafer manufacturing (processing) process in which the single crystal ingot is sliced and at least one main surface is processed into a mirror surface.

  The wafer manufacturing (processing) process will be described in more detail. A slicing process for slicing a single crystal ingot to obtain a thin disk-shaped wafer, and its outer periphery to prevent cracking and chipping of the wafer obtained by the slicing process. A chamfering process for chamfering a part, a lapping process for flattening the wafer, an etching process for removing processing distortion remaining on the chamfered and lapped wafer, and a polishing (polishing) process for mirroring the wafer surface; It has a cleaning step of cleaning the polished wafer and removing the abrasive and foreign matter adhering to the wafer. The above wafer processing process is a main process, and other processes such as a heat treatment process are added, the same process is performed in multiple stages, and the order of processes is changed. In the polishing step, a single-side polishing method for polishing one side of a wafer or a double-side polishing method for simultaneously polishing both surfaces of a wafer is applied.

  In recent years, the diameter of semiconductor wafers has been increasing, and currently, mass production of 300 mm diameter wafers is rapidly progressing. On the other hand, as device integration progresses, the depth of focus margin in the photolithography process is reduced, and the flatness of the wafer including the CMP process is increasingly demanded. In particular, the demand for the flatness of the outer peripheral portion of the wafer is severe because it greatly affects the device yield. Since the amount of work applied to the outer periphery of the wafer by the conventional polishing method is larger than that of the central portion at the outer periphery of the wafer, the outer periphery is sagged. Further, when the diameter of the wafer is increased, the outer sagging is likely to occur. It is known that this outer peripheral sag is due to the pressure being concentrated on the outer peripheral portion of the wafer due to polishing in the double-side polishing process, and also due to the influence of the polishing slurry and the viscoelasticity of the polishing cloth (Patent Document 1, especially the first). Page 2).

  Here, a conventional double-side polishing method for a semiconductor wafer includes a primary double-side polishing step for polishing both surfaces of a wafer using a double-side polishing apparatus, and a wafer for obtaining a surface on which a device is fabricated using the single-side polishing apparatus. It is known that it is composed of a second single-side polishing step for one side and a third single-side final polishing step for final finish polishing (see Patent Document 2, especially page 3 thereof).

  However, in the double-side polishing of the primary double-side polishing step, the taper component is controlled by the rotation of the wafer, but the outer peripheral sag generated at that time is the secondary single-side polishing step and the tertiary single-side finish polishing step. Since the amount of work on the outer periphery of the wafer due to polishing is large, it is usually deteriorated.

Therefore, it is necessary to make an improvement for eliminating the sagging of the outer periphery that occurs during double-side polishing in the primary double-side polishing step. As an example, there is a method of defining the thickness of the carrier plate holding the wafer and the wafer, and the amount of deformation of the polishing cloth when the carrier plate is sandwiched between the upper and lower surface plates (Patent Document 3, especially the second one). Page).
JP 2002-222781 A JP-A-9-270401 JP-A-5-177539

  However, in both conventional semiconductor wafer double-side polishing methods, the wafer held on the carrier plate is rotated along with the rotational movement of the surface plate, and the wafer rotates in this way from the center to the outer periphery. The peripheral speed increases as it goes to the wafer. As a result, the polishing amount of the wafer outer peripheral portion increases as compared with the polishing amount of the wafer central portion, and the polishing margin is particularly large in the first double-side polishing step. It always occurs.

  Accordingly, an object of the present invention is to provide a double-side polishing method for a semiconductor wafer which can easily reduce the peripheral sag of the semiconductor wafer.

In order to achieve the above object, a semiconductor wafer double-side polishing method of the present invention includes a primary double-side polishing step for polishing both surfaces of a semiconductor wafer, and an outer periphery of the semiconductor wafer generated in the primary double-side polishing step. Ri Do and a secondary double-side polishing step of modifying the sag, at the secondary double-side polishing step, holding the semiconductor wafer in the wafer holding hole of the carrier plate, the polishing of the upper and lower affixed to the upper platen and lower platen Using a double-side polishing apparatus capable of simultaneously polishing both surfaces of the semiconductor wafer by moving the carrier plate in a plane parallel to the surface of the carrier plate between cloths, the carrier plate of the double-side polishing apparatus The semiconductor wafer held on the substrate is not moved independently, so that the semiconductor wafer and the carrier plate are integrated to sharpen the outer periphery of the semiconductor wafer. The suppresses characterized in that so as to double-side polishing. That is, the method of the present invention is characterized in that the taper amount of the wafer controlled by the double-side polishing in the primary double-side polishing step is maintained, and only the outer peripheral sag is corrected in the secondary double-side polishing step. It exists.

  In the method of the present invention, it is preferable to provide a third single-side finish polishing step for finishing and polishing one side of the wafer in order to obtain a surface on which a device is produced as necessary after completion of the second double-side polishing step. .

  Further, in the method of the present invention, the semiconductor wafer is held in the wafer holding hole of the carrier plate, and between the upper and lower polishing cloths attached to the upper surface plate and the lower surface plate, in a plane parallel to the surface of the carrier plate. By using a double-side polishing apparatus capable of simultaneously polishing both surfaces of the semiconductor wafer by moving the carrier plate, the pressure is not concentrated on the outer peripheral portion of the semiconductor wafer, and the viscoelasticity of the polishing cloth is not affected. Therefore, the thickness of at least the periphery of the wafer holding hole of the carrier plate of the double-side polishing apparatus used in the second double-side polishing step is in the range of 0 μm to 5 μm from the thickness of the semiconductor wafer before the second double-side polishing step. The semiconductor wafer held in the carrier plate is set to be thick and does not move independently such as rotating. By integrating the semiconductor wafer and the carrier plate, it is preferable to perform double-side polishing while suppressing polishing of the outer peripheral portion of the wafer.

  As described above, when the thickness of at least the periphery of the wafer holding hole of the carrier plate is set in the range of 0 μm or more and 5 μm or less than the thickness of the wafer before polishing, the surface of the carrier plate and the surface of the wafer are substantially in the same plane state. Thus, the pressure distribution applied to the wafer becomes almost constant, and the surface is uniformly polished, and the flatness thereof is improved. However, when making the surface of the carrier plate and the surface of the wafer almost the same surface, it is better to make the thickness of the carrier plate slightly thicker than the thickness of the wafer in consideration of processing variations in the previous process of wafer processing. It is safe. On the other hand, if the thickness is too thick, the state in which the polishing cloth does not come into contact with the vicinity of the outer periphery of the wafer becomes longer due to the depth of the sinking of the polishing cloth. In the method of the present invention, the difference between the thickness of the carrier plate and the thickness of the wafer is set in consideration of about twice the polishing allowance (to be described later) + the variation in polishing and wafer thickness.

The semiconductor wafer polished by the double-side polishing method for a semiconductor wafer of the present invention is slightly polished in the second double-side polishing step so that the polishing allowance is not more than 3 μm on both sides, preferably not more than 2 μm. The inner area is flattened while suppressing the portion, and the thickness in the range of 1.5 ± 0.5 mm from the outermost periphery of the wafer is made thicker in the range of 0 μm to 0.5 μm than the inner thickness. but, Ru der having a thickness profile of a wafer peripheral sag has been modified. If the polishing allowance is larger than 3 μm, the thickness of the central portion of the wafer becomes too thin, which is not preferable. On the other hand, if the polishing allowance is 0 μm (not polished), it is obvious that the peripheral sag of the wafer is not corrected. Actually, it is sufficient to set the polishing allowance to about 1 μm.

The carrier plate used Oite the double-side polishing method for a semiconductor wafer of the present invention, holding the semiconductor wafer in the wafer holding hole of the carrier plate, between the polishing cloth of the upper and lower affixed to the upper platen and lower platen, A carrier plate used in a double-side polishing apparatus capable of simultaneously polishing both surfaces of the semiconductor wafer by moving the carrier plate in a plane parallel to the surface of the carrier plate, the carrier plate being two upper and lower These upper and lower carrier plates are respectively provided with wafer holding holes at opposing positions, a semiconductor wafer is inserted into the wafer holding holes, and the upper and lower carrier plates are inserted from above and below the semiconductor wafer. Sandwiching and overlapping, the outer peripheral ends of the upper and lower carrier plates are fixed, for example, That to be able to integrally carrier plate beneath the semiconductor wafer and the upper by securing the fixed ring are preferred. The total thickness of the upper and lower carrier plates is preferably set so that at least the thickness of the periphery of the wafer holding hole is greater than or equal to 0 μm and less than or equal to 5 μm than the thickness of the semiconductor wafer to be polished.

As another aspect of the carrier plate used in the double-side polishing method of a semiconductor wafer of the present invention, the semiconductor wafer is held in the wafer holding hole of the carrier plate, and between the upper and lower polishing cloths attached to the upper surface plate and the lower surface plate. A carrier plate used in a double-side polishing apparatus capable of simultaneously polishing both surfaces of the semiconductor wafer by moving the carrier plate in a plane parallel to the surface of the carrier plate, wherein the carrier plate is The wafer holding hole is composed of two left and right semicircular carrier plates that are divided into right and left so that the dividing line crosses, and the wafer holding holes are in contact with the dividing line portions of these left and right carrier plates. Semi-circular wafer holding hole recesses are formed, and semiconductor wafers are formed in the wafer holding hole recesses. Insert Ha, that the left and right semicircular carrier plate and to be able to integrally with said semiconductor wafer and the left and right carrier plate by fixing under pressure sandwiched from the left and right of the semiconductor wafer Is preferred . The thicknesses of the left and right carrier plates are preferably set so that at least the thickness of the peripheral portion of the recess of the wafer holding hole is greater than or equal to 0 μm and less than or equal to 5 μm than the thickness of the semiconductor wafer to be polished.

  As described above, according to the double-side polishing method of a semiconductor wafer of the present invention, a wafer having peripheral sag caused by double-side polishing in the primary double-side polishing step can be corrected in the secondary double-side polishing step, and there is little peripheral sag. A flat semiconductor wafer can be manufactured.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the accompanying drawings, but the illustrated examples show preferred examples, and it goes without saying that various modifications can be made without departing from the technical idea of the present invention.

  FIG. 1 is a flowchart showing an example of the order of steps of a method for polishing a semiconductor wafer on both sides according to the present invention. As shown in FIG. 1, first, a workpiece to be polished is prepared (step 100). As this wafer, a wafer which has been etched by alkali or the like in the above-described conventional wafer manufacturing process etching process and whose processing distortion has been removed may be used. Next, the wafer to be polished is double-side polished (first double-side polishing step, step 102). The double-side polishing in the first double-side polishing step is performed using a double-side polishing apparatus. Here, the basic structure of the double-side polishing apparatus will be described with reference to FIG.

  FIG. 2 is a cross-sectional explanatory view showing the basic structure of the double-side polishing apparatus. In FIG. 2, 10 is a double-side polishing apparatus. The double-side polishing apparatus 10 includes a lower surface plate 14 that is rotated at a predetermined rotational speed by a lower rotating shaft 12, and an upper surface plate that is provided opposite to the lower surface plate 14 and is rotated at a predetermined rotational speed by an upper rotating shaft 16. 18. Reference numeral 15 denotes a lower polishing cloth attached to the upper surface of the lower surface plate 14, and reference numeral 19 denotes an upper polishing cloth attached to the lower surface of the upper surface plate 18.

  A carrier holder 20 is provided outside the outer peripheral portions of the lower surface plate 14 and the upper surface plate 18 and holds the carrier plate 24. Reference numeral 26 denotes a fixing pin for fixing the carrier plate 24 to the carrier holder 20. A plurality of wafer holding holes 28 are formed in the carrier plate 24. As a material of the carrier plate 24, a plastic material, a glass epoxy material, or the like is used.

  As shown in FIG. 2, the wafer 8 is held in the wafer holding hole 28 of the carrier plate 24, and the surface of the carrier plate 24 is between the upper polishing cloth 19 of the upper surface plate 18 and the lower polishing cloth 15 of the lower surface plate 14. By moving the carrier plate 24 in a plane parallel to the surface of the wafer 8, both surfaces of the wafer 8 can be polished simultaneously. Note that the double-side polishing in the first double-side polishing step is similar to the conventional double-side polishing step described in Patent Document 2 and the like, in which the wafer 8 held in the wafer holding hole 28 of the carrier plate 24 is transferred to the upper surface plate 18. And it carries out in the aspect rotated with the rotational motion of the lower surface plate 14.

  Subsequently, the wafer that has undergone the first double-side polishing step (step 102) is further double-side polished (secondary double-side polishing step, step 104). This second double-side polishing step (step 104) is a characteristic step of the method of the present invention, and the taper amount of the wafer controlled by double-side polishing in the first double-side polishing step is maintained, and only the peripheral sagging is corrected. Double-side polishing is performed. The polishing allowance of the wafer in the second double-side polishing step may be 3 μm or less, preferably 2 μm or less.

  Here, a double-side polishing apparatus used in the second double-side polishing step for correcting the peripheral sag of the wafer will be described with reference to FIGS. FIG. 3 is an enlarged sectional view showing an example of a carrier plate of a double-side polishing apparatus used in the second double-side polishing step of the method of the present invention, and shows a state where the upper and lower carrier plates are separated. FIG. 4 is a view similar to FIG. 3 and shows a state in which the upper and lower carrier plates are overlapped. FIG. 5 is an overall perspective view showing a state where the upper and lower carrier plates are separated. 3 to 5, the same or similar members as those in FIG. 2 are denoted by the same reference numerals. The basic structure of the double-side polishing apparatus used in the second double-side polishing step of the method of the present invention may be the same as that shown in FIG. 2, and the description of the basic structure will not be repeated. As long as it has a basic structure as shown in FIG. 2, the same apparatus may be used in the primary double-side polishing process and the secondary double-side polishing process, or different apparatuses may be used.

  In FIG. 3, the carrier plate 24 is composed of two upper and lower carrier plates 24a and 24b. As shown in FIG. 5, the upper and lower carrier plates 24a and 24b are provided with upper and lower wafer holding holes 28a and 28b at positions facing each other. Side wall inner peripheral surfaces 27a and 27b of the wafer holding holes 28a and 28b are formed in a groove shape in accordance with the edge portion shape of the wafer 8 so that the wafer 8 can be stored and fixed. Protective pads 29a and 29b are affixed to these groove-shaped inner peripheral surfaces 27a and 27b so as to press and protect the edge portions of the wafer 8 to be stored and fixed. As a material for the protective pads 29a and 29b, any material that is compatible with the shape of the wafer edge portion, such as a rubber material or a urethane foam material, can be used.

  In the example shown in FIG. 4, the thickness of the carrier plates 24a and 24b is the total thickness of both the carrier plates 24a and 24b before the wafer 8 to be polished in the second double-side polishing step. It is formed thicker than the thickness, for example, in the range of 5 μm or less. Therefore, the wafer 8 is inserted into the wafer holding holes 28a and 28b, and the upper and lower carrier plates 24a and 24b are sandwiched from the upper and lower sides of the wafer 8 and overlapped to fix the outer peripheral ends of the carrier plates 24a and 24b. 4, the upper surface of the upper carrier plate 24 a is positioned above the upper surface of the wafer 8, and the lower surface of the lower carrier plate 24 b is positioned lower than the lower surface of the wafer 8. It has become.

  The total thickness of the carrier plates 24a and 24b, that is, the thickness of the carrier plate 24 is at least the thickness of the peripheral portion of the wafer holding holes 28a and 28b (the peripheral portion includes the groove-shaped inner peripheral surfaces 27a and 27b). In this case, the thickness including the groove-like space may be thicker in the range of 0 μm to 5 μm than the thickness of the wafer 8 polished in the second double-side polishing step, but it may be thicker than 0 μm to 3 μm. The range is preferably 0 μm or more and 2 μm or less.

  As shown in FIG. 4, the wafer 8 is fixed in the wafer holding holes 28a and 28b of the carrier plates 24a and 24b, and the wafer 8 and the carrier plates 24a and 24b are integrally polished, so that the carrier plate 24a, The wafer 8 held by 24b does not move independently such as rotating, the pressure is not concentrated on the outer peripheral portion of the wafer 8, and the influence of the viscoelasticity of the polishing cloths 15 and 19 is also eliminated. 8 is polished on both sides in a state in which the polishing of the outer peripheral portion is suppressed, and the peripheral sagging is corrected.

  In the example shown in FIGS. 3 to 5, the wafer 8 is held by pressing the edge portion of the wafer 8 with the groove-like inner peripheral surfaces 27 a and 27 b of the wafer holding holes 28 a and 28 b in order to prevent independent movement such as rotation of the wafer 8. Although the structure which fixes 8 is shown, as shown in FIG. 6, the latching protrusion 25 matched with the notch part 8a of the wafer 8 is provided in the inner peripheral part of the wafer holding holes 28a and 28b of the carrier plates 24a and 24b. Independent movement such as rotation of the wafer 8 can be completely prevented by fitting and locking the notch portion 8a of the wafer 8 to the locking projection 25.

  Various configurations other than the examples shown in FIGS. 3 to 5 can be adopted as the manner of supporting and fixing the wafer. For example, the carrier plate can be divided into left and right parts. This will be described with reference to FIGS. FIG. 7 is an enlarged sectional view showing another example of the carrier plate of the double-side polishing apparatus used in the second double-side polishing step of the method of the present invention, and shows a state before the wafer is held and fixed in the wafer holding hole. FIG. 8 is a view similar to FIG. 7 and shows a state where the wafer is held and fixed in the wafer holding hole. FIG. 9 is a top view showing a state in which the wafer is held in the wafer holding holes of the left and right carrier plates and the left and right carrier plates are abutted and fixed. 7 to 9, the same or similar members as those in FIG. 2 are denoted by the same reference numerals.

  7 to 9, the carrier plate 24 includes a semicircular left carrier plate 24c and a semicircular right carrier plate 24d which are divided into two left and right so that the dividing line 50 crosses the wafer holding hole 28. Yes. Accordingly, the semicircular recesses 28c and 28d, which become the wafer holding holes 28 when they are abutted with each other, are formed in the dividing line 50 portions of the left and right semicircular carrier plates 24c and 24d, respectively. The side wall inner peripheral surfaces 27c and 27d of the wafer holding hole recesses 28c and 28d are formed in a groove shape in accordance with the edge shape of the wafer 8 so that the wafer 8 can be stored and fixed. Protective pads 29c and 29d are affixed to the groove-like inner peripheral surfaces 27c and 27d, and the edge portions of the wafer 8 to be stored and fixed are pressed and protected.

  Also in the example shown in FIG. 7, the thickness of the carrier plates 24c and 24d is, for example, 5 μm, as compared with the thickness before polishing of the wafer 8 polished in the second double-side polishing step, as in the case of FIG. It is formed thick in the following range. Therefore, in the state where the wafer 8 is inserted into the wafer holding hole recesses 28c and 28d and the left and right semicircular carrier plates 24c and 24d are sandwiched and pressed from the left and right and fixed, as shown in FIG. The upper surfaces of the carrier plates 24 c and 24 d are located above the upper surface of the wafer 8, and the lower surfaces of the carrier plates 24 c and 24 d are located below the lower surface of the wafer 8.

  The thickness of the carrier plates 24c and 24d, that is, the thickness of the carrier plate 24 is at least the thickness of the peripheral portion of the wafer holding hole recesses 28c and 28d (when the peripheral portion includes the groove-shaped inner peripheral surfaces 27c and 27d). The thickness including the groove-like space may be thicker in the range of 0 μm to 5 μm than the thickness of the wafer 8 to be polished in the second double-side polishing step, but it may be 0 μm to 3 μm. The range is preferable, and the range of 0 μm to 2 μm is more preferable. Also in the examples of FIGS. 7 to 9, it is possible to adopt a configuration in which the locking protrusions for locking with the notch portions of the wafer shown in FIG. 6 are provided in the wafer holding hole recesses 28c and 28d of the carrier plates 24c and 24d. It is.

  A third single-side final polishing step (step 106) is performed as necessary after the above-described second double-side polishing step (step 104). This single-side finish polishing may be performed in the same manner as in the prior art, but may be performed using, for example, a single-side polishing apparatus as shown in FIG.

  FIG. 10 is a schematic side view illustrating a single-side polishing apparatus. In FIG. 10, the single-side polishing apparatus 40 has a surface plate 30 that is rotated by a rotation shaft 37 at a predetermined rotation speed. A polishing cloth 32 is stuck on the upper surface of the surface plate 30.

  Reference numeral 33 denotes a work holding plate which is rotated by a rotating shaft 38 via an upper load 35 and is swung by a swinging means. The plurality of wafers 8 are pressed against the surface of the polishing cloth 32 while being held on the lower surface of the work holding plate 33 by means of adhesion, and at the same time, a predetermined flow rate is passed through a slurry supply pipe 34 from a slurry supply device (not shown). Then, the slurry 39 is supplied onto the polishing cloth 32, and the surface to be polished of the wafer 8 is rubbed against the surface of the polishing cloth 32 through the slurry 39 to polish the wafer 8.

  Examples of the method of the present invention will be described below, but it is needless to say that these examples are shown by way of illustration and should not be construed as limiting.

(Example 1)
The used wafer was a silicon wafer having a diameter of 300 mm, and this wafer was polished according to the order of steps shown in the flowchart of FIG. First, a wafer from which the processing strain layer etched by alkali or the like was removed was prepared (step 200), and this wafer was double-side polished (first double-side polishing step, step 202). Next, the surface of the edge portion of this wafer was mirror-finished (Step 204).

  Thereafter, in order to correct the sag generated on the outer periphery of the wafer in the first double-side polishing step (step 202), the wafer is integrated with the carrier plate using the carrier plate shown in FIGS. Were set and polished on both sides (second double-side polishing step, step 206). As the carrier plate, a plate whose thickness is 3 μm thicker than the thickness of the wafer was used.

The double-side polishing conditions at this time are such that the pressure applied to the wafer is 150 to 300 g / cm ^2, and a urethane cloth with a hardness of 85 to 95 (Asker C hardness) is applied to the upper and lower surface plates. The obtained double-side polishing apparatus was used. During polishing, a slurry in which colloidal silica was dispersed in an alkaline solution was supplied. The wafer was polished by about 2 μm on both sides under the above polishing conditions.

  Thereafter, the wafer edge portion contacts the protective pad of the carrier plate during the double-side polishing in the second double-side polishing step (step 206) to remove the attached dirt (step 208), and the surface on which the device is formed is a single-side polishing apparatus. The final finish polishing was performed (third single-side finish polishing step, step 210).

  Incidentally, as described above, the double-side polishing method in the first double-side polishing step (step 202), the single-side polishing apparatus used in the third single-side finish polishing step (step 210), and the final polishing method have been conventionally performed. Performed in the same manner as the apparatus and method. Further, as a method of removing the stain on the edge portion in step 208, a very slight polishing process was performed. The thickness of the outer peripheral portion of the wafer polished according to the above-described process order was measured using a thickness measuring device (LER-310M edge roll-off measuring device manufactured by Optical Kobelco Kaken), and the result is shown in FIG. .

(Comparative Example 1)
For comparison, the thickness of the outer peripheral portion of the wafer subjected to single-side finish polishing after double-side polishing in the conventional primary double-side polishing step was measured using the same apparatus as in Example 1, and the result is shown in FIG. It was.

  As is apparent from the results of FIGS. 12 and 13, compared with the wafer polished by the conventional double-side polishing method (FIG. 13, Comparative Example 1), it is polished by double-side polishing in the second double-side polishing step according to the present invention. In addition, the sagging of the outer periphery of the wafer (FIG. 12, Example 1) is remarkably improved, and the thickness in the range of 1.5 ± 0.5 mm from the outermost periphery of the wafer becomes thicker in the range of 0 μm to 0.5 μm from the inner side. Was confirmed.

(Example 2)
Double-side polishing in the same manner as in Example 1 except that the carrier plate of the double-side polishing apparatus in the second double-side polishing step is the same as the thickness of the wafer (the difference between the thicknesses is 0 μm). As a result of the processing, it was confirmed that the peripheral sagging of the polished wafer was remarkably improved in the same manner as in Example 1.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and has the same function and effect can be used. Included in the technical scope.

It is a flowchart which shows one example of the process order of this invention method. It is sectional explanatory drawing which shows the basic structure of a double-side polish apparatus. FIG. 2 is an enlarged enlarged sectional view showing an example of a carrier plate of a double-side polishing apparatus used in a second double-side polishing step of the method of the present invention, showing a state where the upper and lower carrier plates are separated from each other. FIG. 6 is a view similar to FIG. 3 showing a state in which the upper and lower carrier plates are overlapped. It is a whole perspective view which shows the state which separated the upper and lower carrier plates. It is a top surface explanatory view showing the state where the notch portion of the wafer is fitted and locked to the locking protrusion provided on the inner peripheral portion of the wafer holding hole of the carrier plate. The state before the wafer is hold | maintained and fixed to a wafer holding hole by the expanded sectional view which shows the other example of the carrier plate of the double-side polish apparatus used at the 2nd double-side polish process of this invention method is shown. 7 is a view similar to FIG. 7, showing a state where the wafer is held and fixed in the wafer holding hole. It is a top view which shows the state which faced and fixed the left and right carrier plate which hold | maintained the wafer to the wafer holding hole of the left and right carrier plate. It is a schematic side view showing a single-side polishing apparatus. 3 is a flowchart showing a process sequence of a polishing process in Example 1. 4 is a graph showing a measurement result of a thickness of an outer peripheral portion of a wafer polished in Example 1. 6 is a graph showing a measurement result of a thickness of an outer peripheral portion of a wafer polished in Comparative Example 1.

Explanation of symbols

  8: Wafer, 10: Double-side polishing apparatus, 12: Lower rotating shaft, 14: Lower surface plate, 15: Lower polishing cloth, 16: Upper rotating shaft, 18: Upper surface plate, 19: Upper polishing cloth, 20: Carrier holder, 22: fixing ring, 24: carrier plate, 24a: upper carrier plate, 24b: lower carrier plate, 24c: left carrier plate, 24d: right carrier plate, 25: locking protrusion, 26: fixing pin, 27a, 27b, 27c 27d: Groove-shaped inner peripheral surface, 28a, 28b: Wafer holding hole, 28c, 28d: Wafer holding hole recess, 29a, 29b, 29c, 29d: Protective pad, 30: Polishing surface plate, 32: Polishing cloth, 33: Work holding plate, 34: slurry supply pipe, 35: upper load, 37: rotating shaft, 38: rotating shaft, 39: slurry, 40: single-side polishing apparatus, 50: dividing line.

Claims (7)

A primary double-side polishing step of polishing both surfaces of a semiconductor wafer, Ri Do and a secondary double-side polishing step of modifying the peripheral sag of the semiconductor wafer generated in the primary double-side polishing step, the second-order double-sided In the polishing process, the semiconductor wafer is held in the wafer holding hole of the carrier plate, and the carrier plate is placed in a plane parallel to the surface of the carrier plate between the upper and lower polishing cloths attached to the upper surface plate and the lower surface plate. By using a double-side polishing apparatus capable of simultaneously polishing both surfaces of the semiconductor wafer, the semiconductor wafer and the semiconductor wafer held in the carrier plate of the double-side polishing apparatus are prevented from moving independently. A method for double-side polishing a semiconductor wafer , in which a carrier plate is integrated and the double-side polishing is performed while suppressing polishing of the outer peripheral portion of the semiconductor wafer.   The double-sided polishing method of a semiconductor wafer according to claim 1, further comprising a third single-sided final polishing step of finishing and polishing one side of the semiconductor wafer that becomes a surface on which a device is formed after the completion of the second double-sided polishing step.   The thickness of at least the periphery of the wafer holding hole of the carrier plate of the double-side polishing apparatus used in the second double-side polishing step is set to be thicker in the range of 0 to 5 μm than the thickness of the semiconductor wafer before the second double-side polishing step. 3. The double-side polishing method for a semiconductor wafer according to claim 1, wherein the semiconductor wafer is fixed in the carrier plate, and the semiconductor wafer and the carrier plate are integrally polished on both sides. The carrier plate is composed of two upper and lower carrier plates. Wafer holding holes are formed in opposing positions on the upper and lower carrier plates, and a semiconductor wafer is inserted into the wafer holding holes. the overlay is sandwiched from the top and bottom of the semiconductor wafer, according to claim which is adapted to both surfaces polished as a whole that the carrier plate under the semiconductor wafer and the upper by fixing the outer peripheral edge of the carrier plate under the upper fixed unit 3. A method for polishing both sides of a semiconductor wafer according to 1 or 2 . The total thickness of the upper and lower carrier plate, at least the semiconductor wafer thickness thickness of the peripheral portion of the wafer holding hole is polished equal to or more than a fourth aspect the carrier plate according. The carrier plate is constituted by two left and right semicircular carrier plates which are divided into left and right so that the dividing line crosses the wafer holding hole, and they are abutted against the dividing line portions of the left and right carrier plates. A semi-circular wafer holding hole recess is formed, which becomes a wafer holding hole in the state. A semiconductor wafer is inserted into the wafer holding hole recess, and left and right semi-circular carrier plates are sandwiched from the left and right sides of the semiconductor wafer. claim 1 or 2 double-side polishing method for a semiconductor wafer according to such double-sided polishing and integrally with said semiconductor wafer and the left and right carrier plate by pressure in fixed. 7. The carrier plate according to claim 6, wherein the thicknesses of the left and right carrier plates are at least equal to or greater than the thickness of the semiconductor wafer to be polished at least in the peripheral part of the recess of the wafer holding hole.

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