WO1998044541A1

WO1998044541A1 - Flattening process for semiconductor wafers

Info

Publication number: WO1998044541A1
Application number: PCT/US1998/006530
Authority: WO
Inventors: Ankur H. Desai; David L. Vadnais
Original assignee: Memc Electronic Materials, Inc.
Priority date: 1997-04-03
Filing date: 1998-04-02
Publication date: 1998-10-08
Also published as: TW432518B

Abstract

Process for the preparation of a wafer having a total thickness variation of less than about 1.0 νm. The distance between the front and back surfaces of the wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the wafer in a stock removal step to reduce the thickness of the wafer to the target thickness, Tt, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and Tt.

Description

FLATTENING PROCESS FOR SEMICONDUCTOR WAFERS

Background of the Invention

The present invention relates to a process for flattening a semiconductor wafer. In particular, the present invention provides a process for improving the global flatness and/or the local site flatness of a semiconductor wafer. It also provides populations of semiconductor wafers resulting from this process.

Semiconductor wafers used as starting materials for the fabrication of integrated circuits must meet certain surface flatness requirements. Such wafers must be polished particularly flat in order to print circuits on them (or on layers deposited upon them) by, for example, an electron beam-lithographic or photolithographic process . Wafer flatness in the focal point of the electron beam delineator or optical printer is important for uniform imaging in the electron beam- lithographic and photolithographic processes. The flatness of the wafer surface directly impacts device line width capability, process latitude, yield and throughput. The continuing reduction in device geometry and increasingly stringent device fabrication specifications are forcing manufacturers of semiconductor wafers to prepare increasingly flatter wafers. Wafers can be characterized for flatness in terms of a global flatness variation parameter (for example, total thickness variation ("TTV") or Total Indicated Reading ("TIR")) or in terms of a local site flatness variation parameter (for example, Site Total Indicated Reading ("STIR") or Site Focal Plane Deviation ("SFPD")). A more detailed discussion of the characterization of wafer flatness can be found in F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press 1989), pp. 191-195. TTV, frequently used to measure global flatness variation, is the difference between the maximum and minimum thicknesses of the wafer. TTV in the wafer is an important indicator of the quality of the polish of the wafer. STIR (back reference center focus) , frequently used to measure local site flatness variation, is the sum of the maximum positive and negative deviations of the surface in a small area of the wafer from a reference plane which is parallel to the back surface of the wafer and intersects the front surface at the center of the local site. A conventional polished semiconductor wafer typically will have a TTV exceeding about 0.7 μm and a STIR (back reference center focus) exceeding about 0.5 μm for any 25mm X 30mm local site. Such values, however, depend upon actual process conditions and often are significantly larger than 0.7 μm or 0.5 μm. Unless otherwise expressly noted, all STIR values discussed herein are based on a back reference center focus reference plane. Conventionally, polished semiconductor wafers are prepared from a single crystal ingot which undergoes cropping, grinding and orientation marking prior to slicing the ingot into individual wafers . The edges of the wafers are rounded to avoid wafer damage during further processing. The wafers are then lapped (treated with an abrasive slurry) to remove surface damage induced by the slicing process and to make the opposed surfaces of each wafer flat and parallel. After the lapping process, the wafers are subjected to chemical etching to remove mechanical damage produced by the prior shaping steps. Finally, at least one surface of each wafer is subjected to a chemical/mechanical polishing process, such as polishing the wafer with a colloidal silica slurry and a chemical etchant, to ensure that the wafer has a highly reflective, damage-free surface. The wafers are then sorted and cleaned prior to being packaged. Wafers exceeding a maximum specification value for flatness (based on TTV, STIR, etc.) generally are discarded.

Conventional polishing techniques, particularly chemical/mechanical polishing techniques, are limited in the degree of wafer flatness and yield they can achieve. Therefore, there is a need for new methods capable of further improving the flatness of a semiconductor wafer and/or the yield of a given production run over conventional values. In addition, there is a need for methods capable of reducing the overall processing demands and disadvantages of conventional polishing processes without degrading wafer flatness.

The process of the present invention uses a material removal tool, preferably a plasma assisted chemical etching removal tool, in combination and appropriately sequenced with conventional polishing techniques to reduce the flatness variation and/or improve the yields of semiconductor wafers . Poultney, U.S. Patent No. 5,563,709, discusses the use of a metrology apparatus, particularly an apparatus which uses Hartmann-Shack Sensor configurations, to measure the total thickness variation of wafers. The metrology apparatus is situated above a flattening apparatus, such as a plasma assisted chemical etching tool . The placement of the metrology apparatus above the flattening apparatus allows the metrology step and material removal step to occur at a single work station and eliminates the need for a sophisticated co- registration scheme for overlapping a metrology map into shaping station coordinates.

Zarowin, et al . , U.S. Patent No. 5,254,830, discusses a method using a thickness measuring apparatus to generate profile data representing the point-by-point thickness of a semiconductor wafer, particularly the thickness of the silicon film of a silicon-on-insulator ("SOI") substrate. The profile data is processed to yield a dwell time versus position map for the entire surface measured. This map is then used to control the movement of a material removal tool over the surface to locally remove additional stock from the surface to produce a layer having a uniform thickness, particularly to produce an SOI wafer having a device layer with a uniform thickness.

Summary of the Invention Among the several objects of this invention, therefore, may be noted the provision of a process for improving the flatness of a semiconductor wafer; a process for the preparation of a semiconductor wafer with a total thickness variation of less than about 1.0 μm; a process for the preparation of a semiconductor wafer with a site total indicated reading of less than about 1.0 μm; a process for preparing a surface of a semiconductor wafer for the subsequent placement of a film or layer on that surface; a process for improving the yield for a semiconductor wafer production run at a relatively low cost; a process for recovering rejected semiconductor wafers; a process for improving the flatness of conventionally flattened semiconductor wafers exceeding a maximum flatness specification; a process for eliminating flatness sorting of semiconductor wafers; and a process to shape semiconductor wafers prior to polishing such wafers .

Briefly, therefore, the present invention is directed to a process for the preparation of a semiconductor wafer having a TTV and/or a STIR of less than about 1.0 μm. The wafer is first flattened using conventional techniques to reduce the TTV and/or STIR of the wafer to an intermediate value. The distance between the front and back surfaces of the wafer at discrete positions on its front surface is then measured to generate thickness profile data, preferably using an ADE 9700 capacitance probe. Alternatively, other metrology methods (such as metrology apparatus capable of measuring light or acoustic wavefronts reflected by the surface of the wafer) which use other reference planes can be used to generate thickness profile data.

Additional stock is then removed from the front surface of the wafer in a second process step, preferably through plasma assisted chemical etching, to reduce the thickness of the wafer at each discrete point to a target thickness, T_t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T_t . The wafer is optionally subjected to an additional finish polishing step. In addition, the process optionally comprises one or more conventional cleaning steps sequenced throughout the process, preferably immediately following plasma assisted chemical etching. This sequencing and use of the additional material removal step results in the preparation of wafers with flatness values and/or in yields superior to those currently attainable by conventional processes.

The present invention also is directed to a process for flattening semiconductor wafers prepared according to conventional techniques wherein the flatness value of the wafers exceeds a maximum value. According to this process, semiconductor wafers are initially prepared in the conventional manner. The flatness of the wafers is then measured and those wafers not satisfying a minimum acceptable flatness value are subjected to additional processing to further flatten them.

Thickness profile data is generated for the rejected wafers in a manner similar to that discussed above for the first embodiment of the invention. Additional stock is then removed from the front surface of the wafer, preferably through plasma assisted chemical etching, to reduce the thickness of the wafer at each discrete point to a target thickness, T_t, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and T_t. The flattened wafer is optionally subjected to an additional finish polishing step.

Alternatively, the conventionally prepared wafers are not sorted. Instead, all wafers are subjected to the additional stock removal step. This additional step can eliminate the need for a separate flatness sorting step where the required total thickness variation and/or site total indicated reading values for each wafer can be greater than about 0.5 μm and about 0.3 μm, respectively. The present invention is also directed to a population of wafers consisting of at least 10 wafers having an average total thickness variation and/or an average site total indicated reading which does not exceed about 1.0, preferably about 0.7 μm, more preferably about 0.5 μm, and optimally about 0.2 μm. Other objects and features will be in part apparent and in part pointed out hereinafter.

Brief Description of the Drawings

Fig. 1(a) is a graphical illustration of the initial TIR distribution for a number of conventionally flattened wafers and the TIR distribution for the same wafers after plasma assisted chemical etching in accordance with one embodiment of the present invention.

Fig. 1(b) is a graphical illustration of the initial TTV distribution for a number of conventionally flattened wafers and the TTV distribution for the same wafers after plasma assisted chemical etching in accordance with one embodiment of the present invention. Fig. 1(c) is a graphical illustration of the initial STIR distribution for a number of conventionally flattened wafers and the STIR distribution for the same wafers after plasma assisted chemical etching in accordance with one embodiment of the present invention. Fig. 2(a) and 2(b) are graphical illustrations of the initial STIR distribution (back reference center focus) for a group of conventionally flattened wafers and the STIR distribution (back reference center focus) for the same wafers after plasma assisted chemical etching, respectively, in accordance with one embodiment of the present invention.

Fig. 3(a) and 3(b) are graphical illustrations of the initial STIR (site best fit reference plane) distribution for a group of conventionally flattened wafers selected from the wafers shown in Fig. 2 (a) and 2 (b) and the STIR (site best fit reference plane) distribution for the same wafers after plasma assisted chemical etching, respectively, in accordance with one embodiment of the present invention.

Fig. 4(a) is a graphical illustration of the initial SFPD distribution for a number of conventionally flattened wafers in accordance with one embodiment of the present invention. Figs. 4(b), 4(c) and 4(d) are graphical illustrations of the SFPD distribution for a group of wafers selected from the same wafers shown in Fig. 4(a) after plasma assisted chemical etching for three different site sizes. Fig. 5(a) and 5(b) are graphical illustrations of the initial STIR distribution for a number of conventionally flattened and finish polished wafers and the STIR distribution for the same wafers after plasma assisted chemical etching, respectively, in accordance with one embodiment of the present invention. Fig. 6 is a graphical illustration of the initial STIR distribution for a number of conventionally flattened wafers and the STIR distribution for the same wafers after plasma assisted chemical etching in accordance with one embodiment of the present invention.

Description of the Preferred Embodiments

In accordance with the present invention it has been discovered that the global and/or local site flatness of a semiconductor wafer, as well as the yield for a given production run, can be improved by incorporating and appropriately sequencing an additional material removal step, preferably a plasma assisted chemical etching step, with the conventional flattening process for a semiconductor wafer. Wafers having improved global and local site flatness variation values in comparison to those currently attainable through conventional processing can be prepared according to the process of this application. In addition or in the alternative, wafer yield can be improved over conventional yields according to the process of this application.

Further, the incorporation of the additional material removal step in the conventional flattening process can result in the relaxation of one or more of the processing constraints normally imposed upon the flattening process. The material removal rate for and resulting flatness of the wafer in the conventional process depend on a variety of operating factors such as temperature, pressure, pad material and dressing technique, rotation rate and slurry composition. For example, a slower polishing rate generally results in a smoother surface. These variables typically must be tightly controlled to prepare wafers having a consistent minimum flatness. Greater latitude in selecting the values of these variables to achieve a target wafer flatness is possible with the incorporation of the additional material removal step into the conventional process . The process of the present invention employs as a starting material a semiconductor wafer sliced from a single crystal ingot. Silicon is a preferred material for the wafer with the conductivity type and resistivity not being critical. The wafer may have any diameter and target thickness which is appropriate for a semiconductor application. For example, the diameter may be from 4 to 8 inches (100 to 200 mm) or greater and the thickness may be from 475 to 725 μm or greater, with the thickness typically increasing with increasing diameter. The wafer may also have any crystal orientation. In general, however, the wafers have a <100> or <111> crystal orientation.

The wafer is lapped on both sides to remove the nonuniform damage caused by the slicing process, and to improve the parallelism and flatness of the wafer. The lapping abrasive slurry is typically a mixture of alumina or silicon carbide and glycerine, although other suitable lapping slurries are commercially available. The mechanical damage from slicing and lapping can then be substantially removed by chemical etching. Both acid- etching agents and caustic-etching agents are commercially available.

Conventional chemical/mechanical polishing processes typically can be used to reduce the total thickness variation ("TTV") and/or site total indicated reading ("STIR") of a wafer to, at best, about 0.7 μm or about 0.5 μm, respectively. Semiconductor wafers prepared in accordance with the present invention, however, require only that the initial conventional processing step flatten the wafer to an intermediate value which may exceed the values generally achieved by the conventional rough polishing step. Preferably, the intermediate TTV and/or STIR of the wafer is less than about 5 μm; more preferably less than about 4 μm; most preferably less than about 3 μm; and optimally less than about 2 μm. In addition, it is desirable, although not necessary, that the flattened wafer have a surface roughness (RMS), R_a, of less than about 1.0 nm over an area of 1 mm X 1 mm. More preferably R_a is less than about 0.5 nm over an area of 1 mm X 1 mm. For purposes of this invention, the flatness and roughness of the wafer after the initial flattening step can optionally be measured by any suitable metrology apparatus to confirm that the wafer has achieved the desired intermediate flatness and/or roughness values. In an illustrative initial flattening step, a silicon wafer is wax bonded to a ceramic polishing block which is then mounted on the arm of a rough polisher. As the rough polishing begins, the polisher arm is lowered until it comes into contact with a hard pad on the ceramic turntable of the polisher. The turntable is then rotated while a sodium stabilized colloidal silica slurry and an alkaline etchant are dispensed onto the pad surface. The surface of the wafer is polished at about 9 lb/in² and about 50-55°C for about 400 to about 600 seconds for a p-type wafer. This polishing removes from about 16 μm to about 18 μm of silicon (Si <100>) from the surface of the wafer and reduces the low frequency surface roughness of the wafer to no greater than 2.0 nm R_a . Preferably, the low frequency surface roughness is reduced to about 1.2 nm R_a to 2.0 nm R_a in this polishing step. For purposes of the present invention, low frequency surface roughness as observed with a Nomarski microscope at 50X magnification or with a Wyko-2D microscope equipped with a 10X magnification head is in a lateral bandwidth of from 100 μm to 1 mm with a vertical peak to valley measurement not exceeding 15 nm. High frequency surface roughness is haze as measured by a light scattering instrument or an AFM in a lateral bandwidth of from 1 μm to 10 μm with a vertical peak to valley measurement not exceeding 3 nm. Sodium stabilized colloidal silica slurries are well known in the art, and have been described in U.S. Patent No. 3,170,273. Syton HT-50, a preferred sodium stabilized slurry commercially available from E.I. du Pont de Nemours & Company, has a silica content of 49.2- 50.5% and a particle size of 35-50 μm. The sodium stabilized colloidal silica slurry is dispensed at a flow rate of from about 50 to about 80 ml/min.

The alkaline etchant is preferably an amine reinforced caustic solution having a pH ranging from about 11 to 14. A suitable etchant solution can include from about 1.0 to about 1.5 wt . % potassium hydroxide, from about 0.5 to about 1.3 wt . % ethylene diamine and a remainder of distilled water. The alkaline etchant flow typically begins about 12 seconds after the colloidal silica slurry flow is initiated, and continues for about 60 seconds after the colloidal silica slurry flow is discontinued. Alkaline etchant is provided at a flow rate ranging from about 80 to about 120 ml/min. Although use of an alkaline etchant is not required after stock removal, there is a high variance in stock removal between wafers that are polished on the same rough polisher without an alkaline etchant.

The sodium stabilized colloidal silica slurry and alkaline etchant are preferably dispensed onto a hard polyurethane impregnated felt pad, such as a Suba H2 pad which is commercially available from Rodel of Scottsdale, Arizona. Appropriate polishing pads for use in rough polishing or finish polishing are well known in the art. The wafer is then treated with an acidic quench solution for about 10 to about 40 seconds to neutralize the alkaline etchant and slurry that was applied to the wafer. The wafer is also rinsed with water for about 10 to about 30 seconds at a flow rate of from about 100 to about 1000 ml/min. The acidic quench solution and the water rinse can be applied simultaneously or sequentially. The polisher arm is then raised and the ceramic block is demounted and water rinsed.

The acidic quench solution includes a polyether polyol having an average molecular weight of from about 100,000 to about 1,000,000 and an organic or inorganic acid or a mixture thereof. A representative quench solution is composed of from about 0.01 to about 0.1 wt . % polyether polyol, from about 0.2 to about 0.5 wt . % isopropanol, from about 0.5 to about 5.0 wt . % hydrogen peroxide in distilled water, adjusted to a pH of from about 3.4 to about 3.6 with acetic acid or sulfuric acid. A suitable polyether polyol is Polyox WSR N-3000, a water soluble resin commercially available from Union Carbide and having a molecular weight of about 400,000. The acidic quench solution is dispensed at a flow rate of from about 400 to about 800 ml/min.

After the initial flattening step, point-by-point thickness profile data is generated for the wafer and mapped as a function of position on the front surface of the wafer with data being generated at a sufficient number of discrete positions to assure full surface coverage for the wafer. The number of discrete positions, therefore, is at least 2, preferably at least 10, more preferably at least about 100, still more preferably at least about 1000 and, for some applications, most preferably at least about 5,000.

The thickness measurement tool used to generate this data may be a capacitance, optical interference, FTIR, or mechanical (e.g., micrometer) thickness measurement tool.

Preferably, however, it is determined using a capacitance thickness measurement tool having a resolution of at least about 0.5 μm and more preferably a resolution of at least about 0.1 μm. A capacitance measurement tool having a resolution of about 0.1 to about 0.2 μm is commercially available from ADE Corporation (Newton, MA) under the ADE 7200 trademark. Preferably, however, the capacitance measurement tool is the ADE 9700. In operation, the introduction of a silicon wafer in the airgap of a parallel plate capacitor of these tools causes a change in capacitance. This capacitance change can be related to the thickness of the wafer and its effective dielectric constant. The remaining discussion focuses on the use of a capacitance measurement tool for purposes of illustration. One skilled in the art can modify the embodiments disclosed herein to replace such capacitance measurement tools with other metrology apparatus known in the art and can measure flatness based on reference planes differing from those employed by capacitance measurement tools.

Significantly, the reduction in TTV and/or STIR of the wafer can be calculated using an algorithm which operates on the thickness profile data and a target thickness value for the wafer, T_t. For example, the amount of material to be removed can be determined by subtracting the target thickness, T_t, from the thickness profile data at each discrete position with the difference between the two values constituting the amount of stock which must be removed at each position on the front surface of the wafer to achieve the target thickness, T_t, and thus minimize TTV and/or STIR.

Once the amount of material to be removed from each position of the wafer is determined, this information is processed and converted to a dwell time versus position map which is used to control a stock removal tool during a stock removal step. This stock removal step may be executed using any tool which is capable of locally and precisely removing stock from small regions of the front surface of the wafer. The tool may be, for example, a chemical/mechanical polishing tool having micropolishing heads. Preferably, however, it is a PACE removal tool of the type described in U.S. Patent Nos . 4,668,366, 5,254,830, 5,291,415, 5,375,064, 5,376,224, and 5,491,571, which are commercially available from IPEC/Precision, Inc. under the PWS-200 trademark.

After the stock removal step, the wafer has a TTV of less than 1 μm, more preferably a TTV of less than about 0.7 μm, still more preferably a TTV of less than about 0.5 μm, still more preferably a TTV of less than about 0.4 μm, still more preferably a TTV of less than about 0.2 μm, and optimally a TTV of less than about 0.1 μm. Alternatively or additionally, the wafer has a STIR of less than 1 μm, more preferably an STIR of less than about 0.7 μm, still more preferably an STIR of less than about 0.5 μm, still more preferably an STIR of less than about 0.3 μm, still more preferably an STIR of less than about 0.2 μm, and optimally a TTV of less than about 0.1 μm. The final TTV and/or STIR value for the wafer is achieved by accurately mapping the thickness of the wafer and precision thinning the wafer using this map in the stock removal step. During the stock removal step, preferably at least 1.0 μm of stock is removed from the wafer; more preferably at least about 2.0 μm, and most preferably at least about 4.0 μm of stock is removed during the stock removal step .

Prior to and/or after stock removal, the wafer optionally may be cleaned to remove contaminants such as slurry particles and metals introduced during the initial flattening step and sulfur deposited on the wafer surface by the plasma during stock removal . The wafer may be cleaned using any suitable cleaning procedure that does not materially affect the thickness profile of the wafer. Such cleaning procedures are well known in the art and include, for example, the RCA method (described in F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press 1989) , pp. 189-191) , or an appropriate water rinse. After this stock removal step, the wafer may optionally be subjected to a "kiss" (or finish) polish to reduce the surface roughness (rms) , R_a. Plasma wafer- thinning processes will typically leave the surface of the silicon wafer with a significant amount of surface roughness (rms) as measured, for example, with an Atomic Force Microscope (AFM) . Thus, it is preferred that the roughness of the plasma etched wafer surfaces be reduced to a value which is less than that level of roughness. Preferably, the roughness, R_a, is reduced to a value of about 1.0 nm over an area of 1 mm X 1 mm, more preferably to a value of about 0.5 nm over an area of 1 mm X 1 mm, and most preferably to a value of about 1.0 nm over an area of 1 mm X 1 mm.

A kiss polish reduces nonspecularly reflected light (haze) and enhances the specularity of the wafer surface. An unpolished wafer includes high and low frequency components of roughness on its surface. The high frequency roughness causes high light scatter from the surface due to haze. The "kiss" polishing minimizes the high and low frequency surface roughness and reduces haze . The algorithm to determine the amount of removal is as follows: (1) determine the peak ("p") to valley ("v") roughness of the plasma etched surface, r(p-v); (2) design the polishing process to remove approximately 3r(p-v) to 4r(p-v) using a finishing type slurry (e.g., diluted Glanzox) ; and (3) conventional RCA type cleaning. Removing this small amount of silicon typically does not detract from the flatness of the wafer.

In general, about 1 to about 300 nanometers of silicon will be removed in this polish step. The polishing may be carried out in a chemical/mechanical polishing process using, for example, a dilute ammonia stabilized colloidal silica slurry and conventional polishing equipment. A preferred ammonia stabilized colloidal silica slurry is Glanzox 3900, which is commercially available from Fujimi Incorporated of Aichi Pref. 452, Japan. Glanzox 3900 has a silica content of from about 8 to about 10% and a particle size of from about 0.025 μm to about 0.035 μm. If the ammonia stabilized silica slurry is not diluted prior to use, the polished wafer will not be as smooth as a wafer treated with a diluted slurry. A dilution of about one part silica slurry to about 10 parts deionized water is preferred.

A p⁺-type wafer is typically finish polished for about 300 seconds, followed by a quench phase. A finish polishing time of about 240 seconds is conventional for a p^~-type wafer. After polishing, the substrate optionally is subjected to a suitable cleaning procedure, such as use of a standard cleaning solution such as H₂0-H₂0₂-NH₄OH. This embodiment of the present invention offers particular advantages in the preparation of ultra-flat wafers having a TTV and/or STIR of less than about 0.7 μm or about 0.5 μm, respectively. In addition, yields approaching 100% are possible for flatness specifications as low as about 0.7 μm TTV and/or about 0.5 μm STIR. Consequently, this embodiment eliminates the need for flatness sorting of wafers where the flatness specification only requires a TTV and\or STIR above about 0.7 μm and about 0.5 μm, respectively. Conventional wafer preparation processes require such flatness sorting. Further, the process of the present invention also offers particular advantages in the manipulation of conventional flattening and polishing steps . These advantages arise from the additional flexibility in selecting the initial flattening and polishing variable values made possible by the incorporation of the additional material removal step.

Figs. 1(a), 1(b), 2(a), 2(b), 3(a), 3(b), 4(a), (b) , 4 (c) , 4 (d) and 6 illustrate the improvement in flatness according to this embodiment of the invention. In a second embodiment, the stock removal step can be incorporated into the wafer preparation process after the conventional preparation of a wafer. Typically, wafers that have been prepared through conventional processes, i.e., flattening followed by finish polishing, are measured using a thickness measurement tool (such as the ADE 7200 capacitance measurement tool previously discussed) to determine their TTV and/or STIR values and are sorted into one group of wafers exceeding a specified flatness value, and a second group of wafers satisfying the specified flatness value. These wafers may be measured for and sorted based on global flatness and/or local site flatness . Those wafers having a TTV and/or STIR exceeding a maximum specified value typically are discarded. The amount of discarded wafers generally ranges, for example, up to about 3% of a given production run of 200 mm diameter wafers. For tighter flatness specifications, however, this number can increase to 10% to 30% of a given production run.

It has been discovered, however, that such rejected wafers can be economically processed to improve their flatness to acceptable values. In this embodiment of the invention, conventionally prepared wafers are sorted into one or more groups based upon their global and/or local site flatness. The wafers in those groups having a TTV and/or STIR exceeding a maximum specified value are measured to generate thickness profile data. These wafers are then subjected to an additional stock removal step, preferably a plasma assisted chemical etching step, and optionally finish polished again to remove any additional surface roughness and restore the specular surface of the wafer. These additional steps are conducted in substantially the same manner as previously disclosed above with respect to the first embodiment of the invention.

Preferably, the TTV and/or STIR of the rejected wafers is reduced to less than about 0.7 μm; more preferably to less than about 0.4 μm; more preferably to less than about 0.3 μm; still more preferably to less than about 0.2 μm; and optimally to less than about 0.1 μm. In addition, it is desirable, although not necessary, that after such additional stock removal the rejected wafer have an surface roughness (RMS) , R_a, of less than about 1.0 nm over an area of 1 mm X 1mm. More preferably R_a is less than about 0.5 nm over an area of

1 mm X 1mm. For purposes of this invention, the flatness and roughness of the wafer after the rough polishing step can optionally be measured by any suitable metrology apparatus to confirm that the wafer has achieved the target flatness and/or roughness values.

Alternatively, the metrology apparatus can be used to measure and generate thickness profile data for all of the conventionally prepared wafers. All of the wafers are then subjected to a stock removal step based on this thickness profile data in substantially the same manner as previously disclosed above. Fig. 5(a) and 5(b) illustrates the improvement in flatness for rejected wafers according to this embodiment of the invention. These flattened wafers are optionally "kiss" polished. These embodiments of the present invention advantageously improve the yield of a given semiconductor wafer production run by providing a method for recovering wafers not satisfying a target flatness value. The alternative embodiment processing all wafers further reduces or eliminates the disadvantages associated with flatness sorting such as increased cycle time for the preparation of wafers, complicated material flows and increased the cost of manufacture for wafers .

The wafer flattening process of the present invention also enables the preparation of a population of semiconductor wafers having a tight distribution of TTV and/or STIR values. That is, a population of at least about 10 substrates, preferably at least about 25 substrates, can be prepared having an average TTV and/or STIR for the wafer which does not exceed about about

1.0 μm, preferably about 0.7 μm, more preferably about 0.5 μm, still more preferably about 0.3 μm, and optimally about 0.2 μm .

In yet another embodiment of the invention,- the additional stock removal step can be incorporated before the initial chemical/mechanical polishing, or rough polishing, of the wafer. The stock removal step can be used to shape the wafer to offset any flatness degradation caused by the subsequent rough polishing step. For example, certain rough polishing processes can impart a convex shape to the wafer. The additional stock removal step can be used to remedy this problem by removing stock in a manner which imparts a concave shape to the wafer prior to rough polishing. The subsequent rough polishing of the wafer accordingly results in a wafer without convexity. The incorporation of the stock removal step prior to the rough polishing of the wafer, therefore, improves the flatness of the wafer after rough polishing relative to the flatness conventionally obtained after rough polishing. The subsequent finish polishing of the wafer ordinarily does not degrade the flatness of the wafer.

In each of the above embodiments, it may be desirable prior to and/or after stock removal to optionally clean the wafer to remove contaminants such as slurry particles and metals introduced during the initial or intermediate processing steps and sulfur deposited on the wafer surface by the plasma during stock removal . The wafer may be cleaned using any suitable cleaning procedure that does not materially affect the thickness profile of the wafer. Such cleaning procedures are well known in the art and include, for example, the RCA method (described in F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press 1989) , pp. 189-191) , or an appropriate water rinse. Similarly, after "kiss" polishing, it may be desirable to optionally subject the wafer to a suitable cleaning procedure such those conventional procedures discussed above in connection with the stock removal step.

While the present invention has been described in the context of semiconductor wafers, it has general application to any semiconductor substrate for which an ultra- flat surface is needed, particularly where an ultra-flat wafer substrate is needed for epitaxial layer growth. In addition, while the embodiments discussed above focus on flattening wafers to achieve a TTV and/or

STIR value within the preferred ranges discussed herein, one skilled in the art can modify the embodiments to prepare for wafers having larger TTV and/or STIR values if less limiting flatness specifications apply, particularly for TTV and/or STIR values less than about 5 μm.

In view of the above, it will be seen that the several objects of the invention are achieved and other advantageous results attained. As various changes could be made in the above constructions and processes without departing from the scope of the invention, it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

CLAIMS :WHAT IS CLAIMED IS:

1. A process for flattening a semiconductor wafer, the process comprising flattening the wafer to reduce the flatness variation of the wafer to a value of no more than about 5.0 ╬╝m, the flattened wafer having a front surface and a back surface; generating thickness profile data at discrete positions of the wafer, the wafer having a front surface and a back surface; determining the amount of stock to be removed at each of said discrete positions to reduce the flatness variation of the wafer, said determination comprising use of an algorithm operating on the thickness profile data and a target thickness value, T_t; and removing stock from the front surface of the wafer to reduce the flatness variation of said wafer to less than about 1.0 ╬╝m, the amount of stock being removed at each of said discrete positions being based upon said determination; said flatness variation corresponding to a total thickness variation or a site total indicated reading for the wafer.

2. The process of claim 1 wherein the thickness profile data is generated by measuring the capacitance of the wafer at said discrete positions, and stock is removed by etching the front surface of the wafer with a plasma.

3. The process of claim 1 wherein the wafer having a flatness variation of no more than about 5.0 ╬╝m and from which the thickness profile data is generated is a finish polished semiconductor wafer exceeding a specified flatness variation value.

4. The process of claim 1, 2 or 3 wherein the wafer has a flatness variation of less than about 0.7 ╬╝m after the stock removal step.

5. The process of claim 1, 2 or 3 wherein the wafer has a flatness variation of less than about 0.5 ╬╝m after the stock removal step.

6. The process of claim 1, 2 or 3 wherein at least about 1.0 ╬╝m of stock is removed from the wafer during the stock removal step.

7. The process of claim 1, 2 or 3 wherein the wafer is polished after the stock removal step.

8. A population of semiconductor wafers consisting of at least 10 wafers having an average flatness variation for the wafers which does not exceed about 0.5 ╬╝m, said flatness variation corresponding to a total thickness variation or a site total indicated reading for the wafers.

9. The population of wafers of claim 8 wherein the population consists of at least about 25 wafers.

10. The population of wafers of claim 8 or 9 wherein the average site total indicated reading for the wafers does not exceed about 0.3 ╬╝m.