TW432518B - Flattening process for semiconductor wafers - Google Patents

Abstract

Process for the preparation of a wafer having a total thickness variation of less than about 1.0 mu m. The distance between the front and back surfaces of the wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the wafer in a stock removal step to reduce the thickness of the wafer to the target thickness, Tt, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and Tt.

Description

Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 2518 A7 ----- B7 V. Description of the Invention (i)-Background of the Invention The present invention relates to a process for planarizing semiconductor wafers. In particular, the present invention provides a process for improving the overall flatness and / or partial flatness of a semiconductor wafer. It also provides a group of semiconductor wafers obtained from this process. Semiconductor wafers used as starting materials for integrated circuit manufacturing must meet solid surface flatness requirements. Such wafers must be polished to a particularly flat surface by a process such as an electron beam development (lithography) or lithography (ph0tothography) process to print a circuit thereon (or a semiconductor deposited thereon). Layer). The flatness of the wafer at the focal point of the delineator or optical printer is in the process of electron beam-lithographic or photolithography (phot〇mh〇gr 邛 ...) The image of one system is very important. The flatness of the wafer surface directly affects the device line width capability, process level, yield and yield. The continuous reduction in device size and the increasingly strict device manufacturing specifications are Forcing semiconductor manufacturing to prepare increasingly flat wafers. The flatness of a wafer can be measured using overall flatness variation parameters (for example, total thickness variation ("TTV ") or general indication. Indication reading (, 'TIRI |)) Or expressed by local position flatness variation parameters (for example, total position indication reading ("s TIR ") or position focus plane deviation (" SFPD")). The wafer flatness characteristic is described in more detail The discussion can be found in F. S himura, Semiconductor Silicon Crystal T_echn〇l0gy (Academic Press 1 9 8 9), ppl91-195 0 is often used to measure the overall flatness variation TTV, which is the largest and smallest of the wafer The difference in thickness. The TTV in the wafer is a part of the polishing quality of the wafer. -4- This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 cm). (Please read the notes on the back and fill in the cheeks first. (This page)

A7 432518 5. Description of the invention (2) Important indicators. S TIR (Back Reference Central Focal Length), which is often used to measure the flatness variation of a local position, is the largest surface area of a small wafer from a reference plane that is parallel to the back surface of the wafer and intersects the front surface at the local position. The sum of positive and negative changes. A conventional polished semiconductor wafer will typically have a TTV exceeding approximately 0.5 and an STIR (back reference central focal length) exceeding approximately 0.5 for any local position of 25 mm x 30 mm. However, such a number depends on the implementation process conditions and is usually much larger than 0.7 m or 5 m. Unless otherwise noted, all STIR numbers discussed here are based on back-referenced central focal length reference surfaces. Traditionally, polished semiconductor wafers are prepared as individual wafers from a single crystal metal block, after being trimmed ' dish-grinded and positioning labels before slicing. The edges of the wafer are trimmed and rounded to prevent damage to the wafer during further processing. The wafer is then covered (treated with a slurry) to remove surface damage caused by the slicing process and keep the opposing surfaces of each wafer flat and parallel. After the capping process, the wafer is chemically etched to remove the mechanical damage caused by the previous modeling steps. Finally, at least one surface of each wafer is subjected to a chemical / mechanical polishing process, such as polishing the wafer with a colloidal silica slurry and a chemical etchant to ensure that the wafer has a highly reflective, non-destructive surface. These wafers are then sorted and cleaned before packaging. Wafers with flatness exceeding a maximum specification (according to TTV, STIR, etc.) are usually discarded. Traditional polishing techniques, especially chemical / mechanical polishing techniques, are limited by the level of wafer flatness and yield they can achieve. Therefore, there is a need for a method that can further improve the flatness of semiconductor wafers and / or production yields that surpass conventional data. In addition, it can reduce the overall process requirements and the traditional polishing of this paper. The standard of China Paper (CNS) A4 (210X 297 mm) is applicable; > ^ ------- Γΐτ-Τ ----— ο-- (Read the precautions on the reverse side before filling out this page) Employees of the Central Government Bureau of the Ministry of Economic Affairs shall print 5mu 432518 A7 B7, printed by the central government bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs and Consumer Cooperatives. 5. Description of the invention (3) There is also a need for a process that does not reduce wafer flatness. The process of the present invention uses a material removal tool, preferably a plasma-assisted chemical etching removal tool, which is combined with the traditional polishing technology and correctly connected to reduce the flatness variation and / or improve the yield of the semiconductor wafer. . Poultney, U.S. Patent No. 5,563,709, discusses a metrology mechanism, particularly a mechanism configured using a Hartmann-Shack sensor, to measure the total thickness variation of a wafer. The metrology mechanism is located on a flattening mechanism such as a plasma-assisted chemical rhyme tool. The configuration above the planarization mechanism allows this surveying step and substance removal step to occur in a single workstation and eliminates the need for complex mutual registration techniques for overlapping surveying maps into the forming station, etc. ¥ 〇win et al., U.S. Patent No. 5,254,830, discusses the use of a thickness measurement mechanism to generate a profile data representing the point-to-point thickness of a semiconductor wafer, especially the thickness of a silicon film on a silicon-on-insulator (S 01) substrate, and profile data. . The profile data is processed to produce a map of the dwell time versus position for the entire measurement surface. This map is then used to control the movement of the material on the top surface of the material removal tool to remove excess material from the surface locally to produce an SiO wafer with a semiconductor layer of uniform thickness. SUMMARY OF THE INVENTION Therefore, among several objects of the present invention, it can be described as a process preparation for improving the flatness of a semiconductor wafer; a method for preparing a semiconductor wafer having a total thickness variation of less than about 10 " m. Process; a process for preparing a semiconductor wafer with a local position indication reading that is less than about-for preparing a semiconductor wafer surface for subsequent use on the surface

f Xu first read the notes on the back before filling in this page J, 1T οι. 4 3 25 1 8 a7 V. Description of the invention (4) Printing process of the film or semiconductor layer configuration by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumers Cooperatives; -A process to improve the yield of semiconductor wafers at a relatively low cost; _ a process to recover discarded I semiconductor wafers; a process to improve what has traditionally exceeded the maximum flatness specification A process for flatness of a planarized semiconductor wafer; a process for eliminating flatness sorting of semiconductor wafers; a process for forming a semiconductor wafer before polishing such a wafer. Therefore, briefly, the present invention is directed to a process for the preparation of semiconductor wafers having approximately less than ... TTV and / or STIR. The wafer is planarized for the first time using conventional techniques to reduce the wafer's ττν and / or STIR to -middle chirp. The distances between the front and back surfaces at discrete locations on the front surface of the wafer are then measured to produce thickness profile data, preferably using an ade. 9700 capacitor probe. On the other hand, other measurement methods that use other reference planes (such as measurement mechanisms that measure light or sound reflected from the wafer surface) can also be used to generate thickness profile materials. Then the excess raw material is removed on the front surface of the wafer in the second process step to reduce the thickness at each discrete point of the wafer to a target thickness L. The amount of raw material that should be removed at each discrete location is The mosquito is considered after considering the thickness of the material and Tt. The wafer may also go through—additional polishing steps. In addition, 'the process may include one or more conventional cleaning steps sequenced anywhere in the process', preferably directly followed by plasma assisted chemical engraving. This sequence and the step of removing excess material and raw material cause the wafer preparation to be better in flatness number 値 and / or yield than the beta that can be obtained by current traditional processes. The process of semiconductor wafer whose flatness number exceeds the maximum. According to this process (read the precautions on the back before you fill in this page) 4 、-= I --11 1.- οι. I i 1 .ji In g --I, the paper size is suitable for national standard Hua 5 2B 1 R. Description of the invention (A7 B7 was printed by the Ministry of Standards and Technology Bureau of the Central Government Bureau of Consumers and Consumers Cooperatives. The semiconductor wafer was initially prepared in the traditional way. Then the wafer was flat, and the minimum acceptable flatness was not met. In order to further flatten the wafers, the thickness profile data of the wafers that have been screened out are in accordance with the methods discussed above and used in this, the first embodiment of the present invention, and the remaining materials are the best. It is plasma-assisted chemical etching, and is removed from the front surface of the wafer 'to reduce the thickness of the wafer at each discrete point to-target thickness' D. The amount of raw material to be removed at each discrete location is between It is determined after considering the thickness profile and Tt. On the other hand, traditionally prepared wafers have not been picked. Instead, all wafers are subjected to an additional raw material removal step. This additional step can eliminate individual flatness Needs for the picking step, where needed The total thickness and / or position indication readings of each wafer may be greater than about 0.5 m and about 0,3 am, respectively. The present invention is also directed to a wafer group comprising at least 10 wafers, the crystal The circle has an average total thickness variation and / or an average position total indication reading that does not exceed about 1 _ ο V m, preferably about 0.7 / zm, more preferably about 0.5 " m, and most preferably about 0.2 am Some of the other purposes and characteristics are obvious, and some of them will be pointed out here. Brief description of the graphics * 'Figure 1 (a) is the initial TIR distribution of many traditional planarized wafers and many of the same Graphical illustration of the TIR distribution of a wafer after plasma-assisted chemical etching according to a specific embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 111 jld ----- 4— ----- Cr (read the notice on the back of the book, please fill in this page) Printed by Shellfish Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 4 3 251 8 V. Description of Invention (6) 'Figure 1 (b) is The initial ττν distribution of many conventional planarized wafers and many of the same wafers are based on A graphical illustration of the distribution of τ τ ν after electrical assisted chemical silver engraving in a specific embodiment of the invention. Figure 1。 is the initial STIR distribution of many conventional planarized wafers and many of the same wafers according to the present invention-specific embodiments A graphical illustration of the STIR distribution after ZD-assisted chemical etching. ^ Figure 2U) and 2 (b) are the initial S.TIR distribution (back-referenced central focal length) of a group of traditional planarized wafers and the same wafers are based on The present invention—a specific example (a graphic illustration of s T R R after plasma-assisted chemical etching) (back reference central focal length). ^ Figures 3 (a) and 3 (b) are a group of traditional planarized wafers selected from the wafers shown in Figure 2 (a) * 2 (b). Graphical illustration of the STIR distribution (location optimal reference plane) after plasma-assisted chemical etching according to a specific embodiment of the present invention. Figure 4 (a) is a graphical illustration of the initial SFPD distribution of a number of conventional planarized wafers according to an embodiment of the present invention. Figures 4 (d) and 4 (b) and 4 (c) are a group of conventional planarized wafers selected from the wafers shown in Figure 4 (昀) after plasma-assisted chemical etching at three different positions. Graphical illustration of the SFPD distribution. Figures 5 (a) and 5 (b) are the initial STIR distributions of many conventional planarized and polished wafers, and the same wafers are respectively plasma-assisted according to the present invention-a specific embodiment. Graphical illustration of the STIR distribution after chemical etching. Figure 6 is the initial s τ distribution of many conventional planarized wafers and the paper ft ruler of the same wafer after plasma-assisted chemical etching according to a specific embodiment of the present invention ΙΐΙί is home; 缚 bound (CNS) Λ4 specification (2IGX 297), ^ ~ ^ — I —.-- Γ .--.---- Q ------ Ί. ^ ------- -(Please read the notes on the back before filling in this page) 432518 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, M Industrial Consumer Cooperative A7 B7 V. Description of the invention (7) Graphical description of the STIR distribution. According to the present invention, it has been found that the overall and / or local flatness of a semiconductor wafer and a given production yield can be achieved by The semiconductor wafer is assembled and correctly arranged with an additional material removal step, preferably-a plasma-assisted chemical etching step, which is improved compared to the conventional planarization process. It has an improvement compared to the current conventional process. The global and local position flatness variation numbers can be prepared according to the process of the application. In addition, the combination of the additional substance removal step in the conventional planarization process can cause one or more of the normal additions to the planarization process. Relaxation of process pressure. The material removal rate and flatness of the wafer in the traditional process depend on various operating factors, such as temperature, pressure, contact material and processing technology, spin rate and slurry compounds. For example, a Slower polishing rates result in a flatter surface. These variables typically must be strictly controlled to prepare a wafer with a uniform minimum flatness. In order to achieve the target wafer flatness, these variables are In terms of selection, a larger range is more likely to combine additional material removal steps into the traditional process. The process of the present invention uses A semiconductor wafer sliced from a single crystal metal block is the starting material. Silicon is a good material for this wafer, because its conductivity type and resistivity are not critical. The wafer may have any suitable for a semiconductor Applied diameter and target thickness. For example, the diameter may be 4 to 8 inches (100 to 200 mm) or larger, and the thickness may be 475 to 725 " claw or larger. The thickness usually increases as the diameter increases β This wafer may also have any crystal nature (〇Γ 丨 entat 丨 〇η). However, usually this wafer has ___ -10- This paper size is applicable (please read the precautions on the back before filling this page ), 1T -9. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 432518 u A7 ---'__ _ B7_ V. Description of the invention (8) A < 100 > or < 1 1 1 > The wafer is covered at both ends to remove non-destructive damage caused by the slicing process and improve the parallelism and flatness of the wafer. The overlay slurry is typically an aluminum carbide or a mixture of silicon and glycerol, although other suitable overlay slurry are also commercially available. Mechanical damage due to slicing and covering can therefore be removed essentially by chemical etching. Both acid etching agents and alkali etching agents have been commercialized. ... Traditional chemical / mechanical polishing processes can often be used to reduce the total thickness variation of a wafer Γττν ″) and / or the total position indication (, _STIR. To, preferably about 0 _ 7 A m or 0.5 " m. However, a semiconductor wafer prepared according to the present invention only requires an initial conventional process step to planarize the wafer to an intermediate chirp that may generally exceed that achievable with a conventional rough polishing step. Preferably, the crystal The middle 値 TT V and / or S TIR of the circle is about less than 5〆m; preferably less than about 4 μm and most preferably less than about 3 μm; and most ideally less than about 2 V m. No, it is desirable that the planarized wafer has a roughness (RMS) of less than 1.0 nm on an area of 1 mm X 1 mm, Ra. It is preferable that Ra is less than about 0.5 on an area of 1 mm X 1 mm. nm. For the purpose of the present invention, 'the flatness and thick chain of the wafer can be optionally measured with any suitable measuring mechanism after the initial flattening step to confirm that the wafer has reached the desired intermediate flatness. And / or roughness data. In the planarization step, the dream wafer is fixed to a ceramic polishing block, and it is then fixed to the arm of a rough polisher. When the rough polishing starts, the polisher arm Lower to the point where it comes into contact with the hard pad on the ceramic turntable of the polisher. Then the turntable rotates and stabilizes the sodium colloidal silica slurry and -11-This paper size is applicable to China National Standard #CNS (CNS) 6 4 cells (210X2men (Mm) f read the first note on the back of the page and write this page on Ningxiang)-Ding-° Printing policy of the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 2 5 1 8 at _________B7 V. Description of the invention (9)- An etchant is dispensed to the surface of the ladle. For a p-type wafer, the surface rain of the wafer is about 9 lb / in2 and about 50 ° C., and about 400 to 600 seconds. Polished. This polishing removes approximately 16 to 18 # m of silicon (Si < 100 >) from the surface of the wafer and reduces the low-frequency surface roughness of the wafer to no more than 2,0 nm Ra Preferably, the low-frequency surface roughness is reduced in this polishing step to approximately 12 nm Ra to 2.0 nm Ra. For the purposes of the present invention, a Nomarski microscope at 50 The low-frequency surface roughness observed at x magnification or with a Wyki> _2D microscope equipped with a 1 Ox magnification lens is a vertical peak-to-valley measurement of no more than 15 nm in the side bandwidth from 〇〇 " m to 1 mm. High Frequency surface roughness is generally ambiguous as measured by a light-scattering instrument or AFM in a sideband from 丨 V m to 10pm with vertical peak-to-valley measurements not exceeding 3 nm. Sodium stabilized colloidal SiliCa slurries) is well known in this art and has been described in us.

Patent No. 3, 1 70,273. Syton HT-50, a suggested and commercially available stable sodium colloidal silica slurry 'E. I. du Pontne Neurs & Cmpany' has 4 9.2 _ 5 0.5% Silicon dioxide content and molecular size of 35-50ym. The stable sodium colloidal silica slurry is dispensed at a flow rate from about 50 to 80 m 1 / m i η. The verification etchant is preferably a moon-enhanced strong solvent having a ρ Η 値 ranging from 丨 i to 丨 4. A suitable etching solvent may contain from about 1.0 to 1.5 wt.% Potassium hydroxide, from about 0.5 to 13 wt.% Diamethylene, and the remainder is distilled water. The alkaline etchant flow usually begins 12 seconds after the colloidal silica flow is started and continues for approximately 60 seconds after the colloidal silica flow is stopped. Alkaline etching __ -12_ This paper size is applicable to China National Standard (CNS) A4 specification (210X297 cm) --.---- L --.--- Q ^ .------- 1 J ------ οι (#Read the precautions on the back before filling out this page) Employees' Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, India and India 43 2 5 1 8 Α7 __ Β7 V. Description of the Invention Provided at flow rates ranging from approximately 80 to 120 m 1 / mi η. Although the use of a qualitative etchant is not required after raw material removal, there is still a high degree of difference in raw material removal between wafers that have been polished in the same rough polishing without an alkaline etchant. The stable sodium colloidal silica and alkaline etchant are preferably distributed to—

Polyurethane impregnated felt pads, such as the Suba H2 pad commercially used by Rodeloff Scottsdale, Arizona. The correct finish used in rough or finish polishing is well known in this art. 3 The wafer is then treated with an acid stopper for about 10 to 40 seconds to neutralize the application on the crystal. Round alkaline etchant and solvent. The wafer is also rinsed with water at a flow rate from about 1000 to 1000 ml / miη for about 10 to 30 seconds. The acid-stopping agent and the rinsing with water may be performed simultaneously or sequentially. The polishing arm is then lifted and the ceramic block is solidified and rinsed with water. The acid terminator comprises a polyether polyether (polyol) having an average molecular weight of about 100,000 to 10,000, and an organic or inorganic acid or a mixture thereof. . A typical stopping agent is a polyether polyol of about 0.01 to 0.1 v / t.% In steamed water, and an isopropyl appearance of about 0.2 to 0 _ 5 w t.% (Is 〇propa η ο 1 ), Consisting of about 0.5 to 5.0 wt.% Hydrogen peroxide, adjusted to 卩 15 値 3.4 to 3.6 with acetic acid or sulfuric acid. A suitable polyacid (90.3 ^ 61;) 161 ·) polyol is a water-soluble resin that is commercially used by Poly ox WSR N-3 000, and has about 4 0,000. Molecular weight. The acid-terminating agent is dispensed at a rate of about 400 to 800 m I / m i η. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)! D ------ ir —----- ζχ (谙 Please read the notes on the back before filling this page) 43 25 1 8 A7 V. Description of the invention (11 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, 1 ^ Industrial Consumers' Cooperative. After the initial flattening step, the crystal-solid point-to-point thickness profile data is generated and corresponds to the position of the front surface of the wafer and a sufficient number. The data generated at discrete locations to ensure the coverage of the entire surface of the wafer. Therefore, the number of S teach positions is at least 2, preferably at least 10, more preferably at least about 'and better at least about 100G' and for some For applications, the best case is at least 5, 0 0 0. The thickness measurement tool used to generate this information can be a capacitive, optical interference, F TIR, or mechanical (such as a macrometer) thickness measurement tool. However, most Anyway, a capacitor thickness measurement tool having a resolution of at least about 0.5 &quot; m, and more preferably at least about 〇, 丨 &quot; plus. A capacitor thickness having a resolution of about 〇1 to 〇2 &quot; 111 The measurement tool has been developed by ADE c〇r p〇raUn (Newton, MA) is used in the Moe industry using the ADE 72⑽ trademark. However, it is best to use the ADE 9700 capacitor thickness measurement tool. In operation, the use of silicon wafers in parallel-plate capacitors for these tools. Changes in capacitance may be related to the thickness of the wafer and its effective dielectric constant. The rest of the discussion focuses on the use of capacitance measurement tools for illustrative purposes. A person skilled in the art can modify the specifics disclosed herein This embodiment replaces the capacitance measurement tool with another measurement mechanism that is well known in the art and that can measure the flatness based on the reference plane, and which is different from that used by the capacitance measurement tool. Note that the wafer TTV and The reduction in STIR can be calculated using an algorithm that operates on the thickness profile data and the target thickness T t of the wafer. For example, the amount to be removed can be calculated from the thickness profile data at discrete locations. Determined by subtracting the difference between the target thickness Tt and two numbers 其 — ι — d (Please read the precautions on the back before filling this page)-) J ---- 9. This paper Standards apply to China National Standard 4 * · (CNS) Λ4 specifications (210 X 297 cm) • I-....... I.-U ― 1 I ml Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, printed by a cooperative 432518 A7 ______________B7 V. Description of the Invention (l2) The amount of raw materials that must be removed to achieve the target thickness t at various discrete positions on the surface of the yen and yen, and thus minimize TTV and / or STIR. Once from the crystal The amount of material removed at each discrete position of the circle is determined, and this information is processed and converted into a dwell time versus position map that is used to control the material removal tool in the material removal step. This raw material removal step can be performed using any tool capable of locally and accurately removing raw materials from a small area on the front surface of the wafer. For example, this tool is a chemical / mechanical polishing tool with a micro-polish. However, preferably, it is a pace removal tool of the type described in US Patent Nos' 4,668,366, 5,254,830, 5,291,415, 5,375,064, 5,376,224, and 5,4 91,571, which have been developed by IPEC / Precision, Inc. The PWS-200 trademark is commercially used. After the raw material removal step, the wafer has a TTV of less than &quot; m, preferably a TTV of less than about 0.7 &quot; m, even more preferably a TTV of less than about 0.5am, and even more preferably A TTV less than about 0.4 &quot; m, and even more preferably a TTV with less than about 0.2 am, and most ideally a TTV with less than about 0 &quot; m. On the other hand, or even further, it is said that the wafer has an STIR of less than 1 m, preferably having an STIR of less than about 0.7 m, still more preferably having an STIR of less than about 0.5 m, and even more preferably 1 has an STIR less than about 0.3 &quot; m, even more preferably has an STIR less than about 0.2 ym, and most preferably has an STIR less than about 0.1 #m. The final TTV and / or STIR of the wafer accurately maps the thickness of the wafer and uses the map to accurately thin the wafer during the material removal step. During this raw material removal step, it is preferable to have at least l.Oym of raw materials from -15- This paper size is applicable to Chinese National Standard (CNS) A4 specifications (2 丨 0 &gt; &lt; 297 mm): Γ-. 0 ^ ------ Ί ^ J ------- 〇Ί (谙 Please read the note on the back and fill in this page first) ^ 251 0 A7 B7 V. Description of the invention (13) Removal of many wafers More preferably, there is at least 2.0 m, and even more preferably, at least about m of raw materials are removed from the wafer in the raw material removing step. Before and / or after the raw material is removed, the wafer can be cleaned as desired to remove materials such as dissolved particles and metals introduced during the initial planarization step and deposited on the wafer surface by plasma during raw material removal. Impurities like sulfur. The wafer may be cleaned using any cleaning procedure that is suitable without substantially affecting the thickness profile of the wafer. This cleaning procedure is well known in the art, for example, 'including the RCA method (described in F. Shimura, SemicnndHr.tnr. Silicon Crystal Technology (Academic Press 1 98 9), pp. 1 8 9 -1 9 1) 'Or a correct water rinse. After the raw material is removed, the wafer may be subjected to &quot; kissing, and (or completed), polishing as desired to reduce the surface coarse sugar content (r m s), R a. Plasma wafer thinning processes often leave <5x wafer surfaces with a high degree of surface roughness (r m S), as measured by an atomic force microscope (AFM), for example. Therefore, it is desirable that the roughness of the wafer surface etched by plasma is reduced to a value smaller than this roughness. Take the 'Roughness R &amp; of the side and reduce it to a number of approximately 1.0 nm on an area of 1 mm X 1 mm, and more preferably, the roughness is reduced to approximately 0.5 nm on an area of 1 mm X 1 mm. The roughness Ra is, in the best case, reduced to a value of about 1.0 nm in an area of 1 mm × 1 mm. Kissing polishing does not reduce the reflected light (blurring) like a mirror to strengthen the wafer. Specularity of the surface. An unpolished wafer includes high and low frequency coarse chain components on its surface. High-frequency roughness results in a high degree of light scattering on the surface due to blurring. This "kiss touch" polishing minimizes high and low frequency roughness and reduces blur. The algorithm to determine the removal amount is as follows: determine the peak of the plasma etched surface -16- This paper size applies the Chinese National Standard (CNS) A4 specification (2) 0X297 mm page)

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C A7 B7 432518 ----__ 5. Description of the invention (I4) Γ'P ") Roughness (&quot; V") roughness, r (p_v); (2) Use a complete solution (such as diluted Glanzox) The design and polishing process is designed to remove about 3r (p_v) to 4r (pv); and (3) traditional 11 (: in-type cleaning. Removing this small amount of silicon usually does not damage the flatness of the wafer. Usually, about 1 to 30 (nanometers) of silicon is removed during this polishing step. This polishing can be performed in a chemical / mechanical polishing process using dilute ammonia to stabilize colloidal silicon slurry and traditional polishing equipment It was implemented. The recommended gas-water stabilization colloidal silica gel is Glanzox 3 900, which has been developed by Fujimi

Incorporated of Aichi Pref. 452, Japan is commercially used. Glanzox 3900 has a silicon content of about 8 to 10% and a molecular size of about 0.0225 m to 0.35 #m. If the ammonia stabilized colloidal silicon slurry is not diluted before use, the polished wafer will not be as flat as that treated with a dilute solution. The dilution method of about one part of silicon slurry to ten parts of deionized water is more recommended. 0 'wide wafers are usually polished for about 300 seconds and then stopped. For P-type wafers, the conventional polishing time is approximately 240 seconds. After polishing, the substrate can be subjected to appropriate cleaning procedures, such as the use of a standard cleaning solvent such as h2o-h2o2-nh4oh. This particular embodiment of the invention provides particular advantages in the preparation of ultra-flat wafers with TTV and / or STIR less than 0.7 V m and 0.5 Θ m, respectively. On the other hand, for flatness specifications as low as 0.7 &lt; m ττν and 0.5 β m STIR, a yield close to 100% is possible. Therefore, this specific embodiment eliminates the need for flatness specifications that only require TTV and / or STIR wafer flatness sorting of greater than 0.7 P m and 0.5 μm, respectively. Traditional wafer -17- This paper size applies the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm) -ft Read the note of the matter Note page Reprint by the staff of the Central Standards Bureau of the Ministry of Economic Affairs? Ben A7

4 3 2 5 1 8 The Central Bureau of Standards, Ministry of Economic Affairs, Machining and Consumer Cooperatives, etc. ^ The preparation process requires such flatness picking. In addition, the process of the present invention also provides special advantages in the processing of the conventional spheronization and polishing steps. These advantages appear in the additional flexibility in selecting the initial planarization and polishing variables ′, which makes the selection of data possible through a combination of additional substance removal steps. '' Bracelet 1〇), 1 (b), 2 (a), 2 (b), 3 (a), 3 (b), 4 (a), 4 (b), 4 (c), 4 (d) And 6 illustrate the improvement in flatness according to a specific embodiment of the present invention '. In a second embodiment, the raw material removal step may be combined into the wafer preparation process after the conventional wafer preparation. Usually, wafers that have been prepared by traditional processes, that is, flattened. Finished polishers are measured using a thickness measurement tool (such as the ADE 7 2 0 capacitance measurement tool discussed earlier) to determine their TTV. And / or STIR data, and select a group of wafers that exceed a specified flatness number 値 and a second group of wafers that satisfy the specified flatness number 値. These wafers may be measured and sorted based on overall flatness and / or local position flatness. Those wafers with ττν and / and s TIR that exceed the maximum specified 値 are usually discarded. The amount of discarded wafers typically ranges, for example, up to 3% of a given 2000 mm diameter wafer produced. However, for tighter flatness specifications, this number may increase to 10% to 30% of a given production. However, 'it has been found that such discarded wafers can be economically processed to change their flatness to an acceptable level. In this particular embodiment of the invention, the wafers traditionally prepared are selected into one or more groups based on their overall flatness and / or local position flatness. Wafers with TTVs and / or STIRs in those clusters with more than one of the largest defined dimensions were measured to produce a thickness of -18- This paper size applies the Chinese National Standard (CNS) M specification (210X297 mm)-:. Ί ^ Ji i I &quot; (Read the notes on the back and then fill out this page) 4 3 2 5 1 8 V. Description of the invention () 6 A7 B7 The Ministry of Standards and Industry of the Ministry of Economic Affairs of the Central Bureau of Work and F Cooperatives printed the information on the corridor. These wafers are then subjected to an additional raw material removal step, preferably;-an electro-assisted chemical silver engraving step, and optionally refinishing to remove any excess surface roughness and repair the wafer. Reflective surface. These additional steps operate in substantially the same way as the first embodiment of the present invention previously disclosed. Preferably, the eight sets of TTV and ^ STIR of the discarded wafer are reduced to approximately less than; better To about less than 0.4 m; even more preferably to less than about 0.3 m; even more preferably to less than about 0.2 m; and most preferably to about less than about 0.1 m. In addition, Although not required, it is hoped that after such an additional raw material removal step, The wafer has a surface roughness (RMS) of less than about 1.0 nm over an area of 1 mm mm. It is more desirable that Ra is less than about 0.5 nm over an area of 1 mm. For the purpose of the present invention, the crystal The flatness and roughness of the circle after the rough polishing step can be measured as desired using any suitable measurement mechanism to confirm that the wafer has reached the target flatness and / or the target coarse chain. On the other hand, the measurement mechanism may It is used to measure and generate thickness profile data for all conventionally prepared wafers. Then all wafers are subjected to a material removal step based on this thickness profile data, which is done in practically the same way as previously disclosed. Figure 5 (a) and 5 (b) illustrate the improvement in flatness of discarded wafers according to this specific embodiment of the present invention. These flattened wafers can be "kissed" and polished as desired. These specific embodiments of the invention advantageously improve the yield of a given semiconductor wafer by providing a method for recovering wafers that do not meet the target thickness. Another specific embodiment for all wafers is further downgraded Or delete (read the note on the back ^ a ^ ^ ^ then fill in this education) ^ Private --------- Order. 9. -19- This paper size is applicable to China National Standards (CNS) Ｍ 格 (210X297 public epidemic a 5 18 A7 B7 printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative) V. Invention Description (Π) The selection of flatness, such as increasing the cycle time of wafer preparation, is complicated. Disadvantages of material flow and increase of wafer manufacturing cost. The wafer planarization process of the present invention can also be prepared for a semiconductor wafer group with a strict TTV and / or STIR data distribution. That is, a group of at least about 10 substrates, preferably at least about 25 substrates, can be prepared with a wafer average TTV and / or STIR of no more than about, preferably about 0.7 / im, more Fortunately, it is about 0.5 m, and even more preferably about 0.3 m. Most preferably, it is about 0.2 m. In yet another embodiment of the present invention, the additional raw material removal step may be combined before the wafer's initialization / mechanical polishing or rough polishing. The hafnium removal step can be used to shape the wafer to compensate for any flatness reduction caused by the subsequent rough polishing step. For example, some rough polishing processes may give the wafer a convex shape. This additional raw material removal step can be used to repair this problem due to raw material removal, giving the wafer a concave profile before rough polishing. The subsequent rough grinding of the wafer then resulted in a wafer that was not protruding. Therefore, the combination of the raw material removal steps of the wafer before the rough polishing improves the wafer flatness of the wafer after the rough polishing compared to the flatness conventionally obtained after the rough polishing. Subsequent redundant polishing of the wafer usually does not reduce the flatness of the wafer. In each of the above embodiments, it may be desirable to selectively clean the wafer before and / or after raw material removal to remove materials such as solvent particles and metals that are attractive during the initial or intermediate steps and during raw material removal. Impurities such as MU and the like are deposited by the plasma. The wafer can be cleaned using any suitable cleaning procedure that does not substantially affect the thickness profile of the wafer. This (Please read the notes on the back before filling out this page) * * 1 ------- ^ Order —: ---------;-^-^ --- r.

A7 B7 4325 1 8 V. Description of the invention (ι0 cleaning procedures are well known in the art, including, for example, the RCA method (; described in F. Shimura, Semiconductor Silicon Hryctaj Tec.ji.n〇l〇 -£ X (Academic Press 1989), pp. 1 89-191), or a proper water rinse. Similarly, after a "kiss" polish, it may be desirable to selectively implement a proper cleaning procedure on the wafer Traditional procedures such as those discussed above with the material removal steps. Although the present invention is described in the context of a semiconductor wafer, it can still be applied to any semiconductor substrate that requires an ultra-flat surface, especially if it requires ultra-flat surfaces. Growth of an epitaxial layer on a flat wafer substrate. In addition, although the specific embodiments discussed above focus on planarizing the wafer so that the TT v and / or s TIR numbers reach the desired range discussed herein, one skilled in the art The specific embodiment of M can still be modified to prepare wafers with larger ττν and / * STiR numbers, if applied to lower-limit flatness specifications, especially TTV and / or STIR numbers less than about 5 &quot; m From the above point of view, we see that several solid and other advantageous results of the present invention will be obtained. Because the above structure and process can be changed in various ways without departing from the scope of the present invention, 'We try to make all The above description or the attached figures will be interpreted as described and not limited to understanding. -21-I-: .. I-, ——, Q 1 Order -r 0Ί (Please read the precautions on the back first (Fill in this page again.)

Claims (1)

4 3 2 5 1: &quot; ', No. 871〇5〇 Patent application in Chinese (Amended in July, 1989) Α8 Β8 C8 D8 The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative prints mi ι-a process for flattening a semiconductor wafer, the process includes: flattening the wafer to reduce the wafer's flatness variation to-no more than about A value of 50 μm, the flattened wafer has a front surface and a rear surface; thickness profile data at discrete positions of the wafer are generated, and the wafer has a front surface and a rear surface; The amount of raw material removed to reduce the flatness variation of subsequent wafers' decision includes the use of-calculation of the thickness contour data and an algorithm for a target thickness of 1 \; and the removal of raw materials from the front surface of the wafer to reduce the wafer The flatness variation of the thickness to approximately less than 1.0 mm is based on the decision; the flatness variation corresponds to the total thickness variation of the wafer or a partial total indication reading. 2. According to the process of item 1 of the scope of patent application, the thickness profile information is generated by the capacitance of the wafer in discrete locations in ① !, and the raw material is obtained by etching the front surface of the wafer with plasma. Removed. 3. A process for reducing the flatness variation of a polished semiconductor wafer exceeding the specification flatness variation value, the process includes: generating thickness profile data at discrete positions of the wafer, the wafer Having a front surface and a rear surface; deciding the amount of raw material to be removed at each discrete location to reduce the flatness variation of the wafer; the decision includes an algorithm using a calculated thickness profile data and a target thickness T t; and (Please read the notes on the back before filling this page) AB: C; D 4 3 2 5 1 8 VI. Patent application scope Remove raw materials from the front surface of the wafer to reduce the flatness of the wafer to less than about 1.0 m, which is removed at various discrete locations The amount of raw materials is based on the decision; the flatness variation corresponds to the total thickness variation or partial total of the wafer, and the reading is shown. 4. According to the process of the patent application Fanyuan No. 3, the thickness profile data is generated by measuring the capacitance of the wafer at discrete positions, and the raw material is moved by cutting the front surface of the wafer with the electric worm. Divide 5. According to the process of claim 1, 2, 3 or 4 of the patent application park, wherein the wafer has a flatness variation of less than 0-7 Am after the material removal step. 6. According to the process of claim 1, 2, 3 or 4 of the scope of patent application, wherein the wafer has a flatness variation of less than 0.5 jtzm after the raw material removal step. 7. According to the patent application park No. 1, 2, The process of 3 or 4, wherein the wafer has a flatness variation of less than about 0.2 μm after the raw material removal step. 8. The process according to item 1, 2, 3, or 4 of the patent application park, wherein the crystal circle has a flatness of about m after the raw material removal step. 9. The process according to claim 1, 2, 3, or 4, wherein the crystal circle is polished after the material removal step. -2- This paper is standard Chinese Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs