TW432518B - Flattening process for semiconductor wafers - Google Patents

Flattening process for semiconductor wafers Download PDF

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Publication number
TW432518B
TW432518B TW87105021A TW87105021A TW432518B TW 432518 B TW432518 B TW 432518B TW 87105021 A TW87105021 A TW 87105021A TW 87105021 A TW87105021 A TW 87105021A TW 432518 B TW432518 B TW 432518B
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Taiwan
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wafer
flatness
thickness
raw material
patent application
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TW87105021A
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Chinese (zh)
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Ankur H Desai
David L Vadnais
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Memc Electronic Materials Spa
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • H01L21/02005Preparing bulk and homogeneous wafers
    • H01L21/02008Multistep processes
    • H01L21/0201Specific process step
    • H01L21/02024Mirror polishing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

Process for the preparation of a wafer having a total thickness variation of less than about 1.0 mu m. The distance between the front and back surfaces of the wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the wafer in a stock removal step to reduce the thickness of the wafer to the target thickness, Tt, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and Tt.

Description

經濟部中央標準局員工消費合作社印製 4 3 2518 A7 ----- B7 五、發明説明(i ) —- 發明背景 本發明有關於-用來平坦化半導體晶圓的製程。特別是 ,本發明提供—種改善半導體晶圓全體平坦度及,或局部平 坦度的製程。它也提供以此製程所得之半導體晶圓的集團。 用做積體電路製造之起始物質的半導體晶圓必須符合確 實的表面平坦度需求。這種晶圓必須藉由如電子束顯影 (elytron beam_lithographic)或微影(ph〇t〇Hth〇grapH㈧ 製程而被磨光至特別地平坦以印刷電路於其上(或在沉積於 其上的半導體層上)。在該電子束描繪器(delineator)或光 學印表機的焦點處之晶圓平坦度對於電子束顯影(electron beam-lithographic)或微影(phot〇mh〇gr邛…)製程中 一制的影像來説是很重要的。晶圓表面的平坦度直接影響 到裝置線寬度能力,製程水準,良率以及產量。在裝置大 小上的持續降低和越來越嚴格的裝置製造規格正迫使半導 體製造咸準備越來越平坦的晶圓。 晶圓在平坦度上可以用整體平坦變動參數(例如,總厚度 變動(’’TTV")或總指.示讀數(,'TIRI|))或者用局部位置平坦 變動參數(例如,位置總指示讀數(” s TIR")或位置焦點平面 偏差("S F P D ’'))來表示。晶圓平坦度特性描述更詳細的討 論可在 F. S himura,Semiconductor Silicon Crystal T_echn〇l〇gy (Academic Press 1 9 8 9), ppl91-195 中找 到0 常常使用於測量整體平坦度變動的TT V,是晶圓最大和 最小厚度間的差異。晶圓中之TTV是晶圓磨光品質的一項 -4- 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210X297公蝥) (讀先閱讀背面之注意事頰再填寫本頁)Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 2518 A7 ----- B7 V. Description of the Invention (i)-Background of the Invention The present invention relates to a process for planarizing semiconductor wafers. In particular, the present invention provides a process for improving the overall flatness and / or partial flatness of a semiconductor wafer. It also provides a group of semiconductor wafers obtained from this process. Semiconductor wafers used as starting materials for integrated circuit manufacturing must meet solid surface flatness requirements. Such wafers must be polished to a particularly flat surface by a process such as an electron beam development (lithography) or lithography (ph0tothography) process to print a circuit thereon (or a semiconductor deposited thereon). Layer). The flatness of the wafer at the focal point of the delineator or optical printer is in the process of electron beam-lithographic or photolithography (phot〇mh〇gr 邛 ...) The image of one system is very important. The flatness of the wafer surface directly affects the device line width capability, process level, yield and yield. The continuous reduction in device size and the increasingly strict device manufacturing specifications are Forcing semiconductor manufacturing to prepare increasingly flat wafers. The flatness of a wafer can be measured using overall flatness variation parameters (for example, total thickness variation ("TTV ") or general indication. Indication reading (, 'TIRI |)) Or expressed by local position flatness variation parameters (for example, total position indication reading ("s TIR ") or position focus plane deviation (" SFPD")). The wafer flatness characteristic is described in more detail The discussion can be found in F. S himura, Semiconductor Silicon Crystal T_echn〇l0gy (Academic Press 1 9 8 9), ppl91-195 0 is often used to measure the overall flatness variation TTV, which is the largest and smallest of the wafer The difference in thickness. The TTV in the wafer is a part of the polishing quality of the wafer. -4- This paper size is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 cm). (Please read the notes on the back and fill in the cheeks first. (This page)

A7 432518 五、發明説明(2 ) 重要指標。常常使用於測量局部位置平坦度變動的S TIR ( 背參考中央焦距),是自一平行於該晶圓背表面並在該局部 位置與前表面相交的參考平面起之晶圓的小區域表面最大 正與負變動的和。一傳統磨光之半導體晶圓對任何2 5 m m X30mm的局部位置典型地會具有超過大約的TTV 和超過大約〇·5"πι的STIR(背參考中央焦距)。然而,這樣 的數値視實施製程條件而定且通常比〇 . 7 " m或〇 ;5 # m要大 得多。除非特別註明,此處所討論的所有STIR數値都是基 於背參考中央焦距參考表面。 傳統上來説,磨光的半導體晶圓準備是自一單晶金屬塊 經過修整’碟磨和在切片前的定位標籤而成爲個別的晶圓 。晶圓的邊緣被修整圓化以防止在進一步製程中晶圓的破 壞。該晶圓接著被覆蓋(以研磨漿處理)以移除由切片製程引 起的表面破壞並使各晶圓的相對表面平坦且平行。在該覆 蓋製程之後,該晶圓受化學蚀刻以移除由前面造型步驟所 產生的機械性破壞。最後,各晶圓的至少一個表面從事一 化學/機械磨光製程,諸如以一膠質矽石漿和—化學蝕刻劑 磨光該晶圓,以保證該晶圓具有高反射,無破壞的表面。 這些晶圓接著在包裝之前被揀選並清潔。平坦度超過一最 大規格値(根據TTV,STIR,等)的晶圓通常被丟棄。 傳統磨光技術’特別是化學/機械磨光技術,受限於他們 所能達到之晶圓平坦度和良率的水準。因此,能夠進一步 改善半導體晶圓平坦度及/或超越傳統數値之生產良率的方 法是有需求的。另外,能夠降低整體製程需求和傳統磨光 本紙張尺度適用中國國家標準(CNS ) A4規格(210X 297公釐) . ;; > ^-------Γΐτ-Τ----— ο-- (讀先閱讀背面之注意事項再填寫本頁) 經濟部中央榡毕局員工消贽合作社印5木 432518 A7 B7 經濟部中央標準局Μ工消費合作社印聚 五、發明説明(3 ) 製程的缺點而不降低晶圓平坦度的方法也是有需要的。 本發明的製程使用一物質移除工具,最好是一電漿輔助 化學蝕刻移除工具,與傳統磨光技術組合並正確地接續, 以降低平坦度變動及/或改善半導體晶圓的良率。 Poultney,U.S_ Patent No_ 5,563,709,討論 了測量學機構 ’特別是使用Hartmann-Shack感測器組態的機構,來測 量晶圓的總厚度變動。該測量學機構是位於—平坦化機構 ’諸如電漿輔助化學敍韵工具之上。在平坦化機構之上的 配置容許該測量學步驟和物質移除步驟能在一個單一的工 作站中發生並消去了對用於重疊測量學圖進入造形站等之 複雜的相互登記技巧的需要。 ¥〇win 等,U.S_ Patent No. 5,254,830,討論了使用—厚 度測量機構以產生表示半導體晶圓點對點厚度,特別是絕 緣體上矽(S 01)基體的矽薄膜的厚度,之輪廓資料的方法。 該輪廓資料被處理以產生對整個測量表面之停留時間對位 置的對映圖。這對映圖接著被使用來控制物質移除工具最 表面上的運動以局邵地自表面移除多餘原料而產生一具有 一致厚度之半導體層的s 〇 I晶圓。 發明摘要 因此,在本發明的幾個目的之中,可以記述爲用來改善 半導體晶圓平坦度的製程準備;—種用於具有大約小於10 "m之總厚度變動的半導體晶圓準備的製程;一種用於具有 大約小於之局部位置指示讀數的半導體晶圓準備的 製程用來準備-丰導體晶圓表面用於隨後在該表面A7 432518 5. Description of the invention (2) Important indicators. S TIR (Back Reference Central Focal Length), which is often used to measure the flatness variation of a local position, is the largest surface area of a small wafer from a reference plane that is parallel to the back surface of the wafer and intersects the front surface at the local position. The sum of positive and negative changes. A conventional polished semiconductor wafer will typically have a TTV exceeding approximately 0.5 and an STIR (back reference central focal length) exceeding approximately 0.5 for any local position of 25 mm x 30 mm. However, such a number depends on the implementation process conditions and is usually much larger than 0.7 m or 5 m. Unless otherwise noted, all STIR numbers discussed here are based on back-referenced central focal length reference surfaces. Traditionally, polished semiconductor wafers are prepared as individual wafers from a single crystal metal block, after being trimmed ' dish-grinded and positioning labels before slicing. The edges of the wafer are trimmed and rounded to prevent damage to the wafer during further processing. The wafer is then covered (treated with a slurry) to remove surface damage caused by the slicing process and keep the opposing surfaces of each wafer flat and parallel. After the capping process, the wafer is chemically etched to remove the mechanical damage caused by the previous modeling steps. Finally, at least one surface of each wafer is subjected to a chemical / mechanical polishing process, such as polishing the wafer with a colloidal silica slurry and a chemical etchant to ensure that the wafer has a highly reflective, non-destructive surface. These wafers are then sorted and cleaned before packaging. Wafers with flatness exceeding a maximum specification (according to TTV, STIR, etc.) are usually discarded. Traditional polishing techniques, especially chemical / mechanical polishing techniques, are limited by the level of wafer flatness and yield they can achieve. Therefore, there is a need for a method that can further improve the flatness of semiconductor wafers and / or production yields that surpass conventional data. In addition, it can reduce the overall process requirements and the traditional polishing of this paper. The standard of China Paper (CNS) A4 (210X 297 mm) is applicable; > ^ ------- Γΐτ-Τ ----— ο-- (Read the precautions on the reverse side before filling out this page) Employees of the Central Government Bureau of the Ministry of Economic Affairs shall print 5mu 432518 A7 B7, printed by the central government bureau of the Ministry of Economic Affairs of the Ministry of Economic Affairs and Consumer Cooperatives. 5. Description of the invention (3) There is also a need for a process that does not reduce wafer flatness. The process of the present invention uses a material removal tool, preferably a plasma-assisted chemical etching removal tool, which is combined with the traditional polishing technology and correctly connected to reduce the flatness variation and / or improve the yield of the semiconductor wafer. . Poultney, U.S. Patent No. 5,563,709, discusses a metrology mechanism, particularly a mechanism configured using a Hartmann-Shack sensor, to measure the total thickness variation of a wafer. The metrology mechanism is located on a flattening mechanism such as a plasma-assisted chemical rhyme tool. The configuration above the planarization mechanism allows this surveying step and substance removal step to occur in a single workstation and eliminates the need for complex mutual registration techniques for overlapping surveying maps into the forming station, etc. ¥ 〇win et al., U.S. Patent No. 5,254,830, discusses the use of a thickness measurement mechanism to generate a profile data representing the point-to-point thickness of a semiconductor wafer, especially the thickness of a silicon film on a silicon-on-insulator (S 01) substrate, and profile data. . The profile data is processed to produce a map of the dwell time versus position for the entire measurement surface. This map is then used to control the movement of the material on the top surface of the material removal tool to remove excess material from the surface locally to produce an SiO wafer with a semiconductor layer of uniform thickness. SUMMARY OF THE INVENTION Therefore, among several objects of the present invention, it can be described as a process preparation for improving the flatness of a semiconductor wafer; a method for preparing a semiconductor wafer having a total thickness variation of less than about 10 " m. Process; a process for preparing a semiconductor wafer with a local position indication reading that is less than about-for preparing a semiconductor wafer surface for subsequent use on the surface

f許先聞讀背面之注意事項再填寫本頁J ,1Τ οι. 4 3 25 1 8 a7 五、發明説明(4 ) 經濟部中央標準局貝工消资合作社印^ 薄膜或半導體層之配置的製程;—種用來在相對低之成本 下改善半導體晶圓生產良率的製程;_種用來在救回已丢 棄I半導體晶圓的製程;一種用來改善傳統上超過最大平 坦度規格之已平坦化之半導體晶圓的平坦度的製程;一種 用來消去半導體晶圓平坦度揀選的製程;一種用來在磨光 這種晶圓之前造形半導體晶圓的製程。 因此,簡短地説’本發明被導向一種具有大約小於… 政TTV和/或STIR的半導體晶圓之準備的製程。該晶圓使 用傳統技術而被第一次平坦化以降低該晶圓的ττν和/或 STIR至-中間値。在該晶圓前表面各離散位置之前後表面 的距離接著被測量以產生厚度輪廓資料,最好使用ade .9700電容探棒。另—方面,其他使用其他參考平面的測量 圣法(諸如能夠測量自晶圓表面反射回來的光或聲波的測量 機構)也可被使用來產生厚度輪廓資科。 然後多餘的原料在第二製程步驟中在該晶圓的前表面被 移除,以降低在該晶圓各離散點的厚度至一目標厚度L, 在各離散位置應被移除的原料量是在考慮厚度輪^料和 Tt之後蚊的。該晶圓也可能經過—額外的完成磨光步躁 。另外’該製程可以包括在製程中任何地方序列的一個或 多個傳統清潔步驟’最好是直接接著電漿輔助化學姓刻。 這序列以及多餘物質原料移除步驟造成了晶圓的準備在平 坦度數値和/或良率上優於目前傳統製程所能得到的β 本發明也導向-種用來平坦化根據傳統技術準備,而其 平坦度數値超過最大値的半導體晶圓的製程。根據本製程 (讀先閱讀背面之注意事項再填寫本頁) 4 、-= I --11 1.- οι. I i 1 .ji In g --I , 本紙張尺度適細國家標华 五 2B 1 R、發明説明( A7 B7 經"部中央標芈局負工消资合作社印製 ,半導體晶圓初始以傳統方式準備。然後晶圓的平垣度, 而未滿足最小可接受之平坦度數値的晶圓從事額二二 以進一步將其平坦化。 、 破篩選掉之晶圓的厚度輪廓資料依與以上所討論並用於 本,明第-具體實施例的類似方式而=餘原料 ,最好是經由電漿輔助化學蝕刻,而從晶圓的前表面被移 除’以降低該晶圓在各離散點之厚度至—目標厚度’丁 。 在各個離散位置處要移除的原料量是在考慮厚渡=廓資料 和Tt之後被決定。 另一方面,傳統準備之晶圓並未被揀選。取代的是,所 有晶圓要從事額外原料移除步驟。這額外的步驟可以消除 各別平坦度揀選步驟的需求,該處所需對各晶圓的總厚度 无動和/或位置總指示讀數分別可大於大約〇 . 5 " m和大約 0,3 a m。 本發明也導向一包含至少10個晶圓的晶圓集團,其晶圓 具有不超坶大約1 _ ο V m的平均總厚度變動和/或平均位置總 指示讀數,最好是大約0.7/zm,更希望是大約0.5"m,而 最理想的是大約0.2 a m。 其他的目的及特性一部份是顯而易見的,而一部份將在 此處以後指出。 圖形之簡軍説明 * '圖1(a)是許多傳統平坦化晶圓之初始TIR分佈和許多相同 晶圓在根據本發明一具體實施例之電漿輔助化學蝕刻之後 的TIR分佈的圖形説明。 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 111 jld-----4—-----Cr (諳先閣讀背面之注意事碩再填寫本頁) 經濟部中央標準局貝工消費合作社印製 4 3 251 8 五、發明説明(6 ) '圖1(b)是許多傳統平坦化晶圓之初始ττν分佈和許多相 同晶圓在根據本發明一具體實施例之電衆輔助化學银刻之 後的τ τ ν分佈的圖形說明。 .,圖1⑷是許多傳统平坦化晶圓之初始STIR分佈和許多相 同晶圓在根據本發明—具體實施例之電衆輔助化學蚀刻之 後的S ΤIR分佈的圖形說明。 ^圖2U)和2(b)是一群傳統平坦化晶圓之初始S.TIR分佈( 背參考中央焦距)和相同晶圓分別在根據本發明—具體實施 例(電漿輔助化學蝕刻之後的s T〗R分作(背參考中央焦距) 的圖形説明。 ^ 圖3(a)和3(b)是一群選自圖2(a)*2(b)所示晶圓之傳統 平坦化晶圓之初始STIR分佈(位置最適參考平面)和相同晶 圓分別在根據本發明一具體實施例之電漿輔助化學蝕刻之 後的STIR分佈(位置最適參考平面)的圖形說明。 .圖4(a)是根據本發明一具體實施例之許多傳統平坦化晶 圓之初始SFPD分佈的圖形説明。 、.—圖4(d)和4(b)和4(c)是一群選自圖4(昀所示晶圓之傳統 平坦化晶圓而在三個不同位置大小之電漿輔助化學蝕刻之 後的S F P D分佈的圖形説明。 圖5 (a)和5(b)是許多傳統平坦化及完成磨光之晶圓的初 始STIR分佈和相同晶圓分別在根據本發明—具體實施例之 電漿輔助化學蝕刻之後的STIR分佈的圖形説明。 、圖6是許多傳統平坦化晶圓的初始s τ〗尺分佈和相同晶圓 在根據本發明一具體實施例之電漿輔助化學蝕刻之後的 本紙ft尺ΙΐΙί則家;ί縛(CNS ) Λ4規格(2IGX 297公楚) ^~^ — I—.--Γ.--.---Q------Ί.^—------ (餚先閱讀背面之注意事項再填寫本頁) 432518 經濟部中央標準局Μ工消费合作社印製 A7 B7 五、發明説明(7 ) STIR分佈的圖形説明。 皮議具體實施例之詳細説明 根據本發明,已發現一半導體晶圓的整體及/或局部位置 平坦度以及一給定之生產之良率,可以藉著對一半導體晶 圓组合並正確地排列一額外之物質移除步驟,最好是—電 漿輔助化學蝕刻步驟,與傳統平坦化製程而提高。具有相 比於目前透過傳統製程所.得者有改善之整體及局部位置平 坦度變動數値可以根據本應用的製程來準備。 另外,該額外之物質移除步驟在傳統平坦化製程中的組 合可以造成正常地加入於平坦化製程中之一個或多個製程 壓迫的鬆弛。該晶圓在傳統製程中的物質移除速率和得到 之平坦度視各種操作因子,諸如溫度,壓力,接點物質及 處理技術,旋轉率和漿化合物。舉例來説,一較慢的磨光 速率通¥造成一較平坦的表面。這些變數典型地必須被嚴 格地控制以準備具有一致最小平坦度的晶圓。在爲達到目 標晶圓平坦度而對這些變數數値的選擇方面,較大的範圍 較可能組合額外之物質移除步驟進入傳統製程中。 本發明的製程使用切片自一單晶金屬塊的半導體晶圓爲 起始物質。矽是用於該晶圓較好的物質,因其傳導型式及 電阻率都非關鍵重要。該晶圓可能具有任何適用於一半導 體應用的直徑和目標厚度。舉例來説,直徑可能是4到8英 对(100到200 mm)或者更大,而厚度可能是475到725"爪 或者更大’厚度通常隨著直徑增加而增加β該晶圓也可能 具有任何晶體本性(〇 Γ丨e n t a t丨〇 η )。然而,通常該晶圓具有 ___ -10- 本紙張尺度適用下 (請先^讀背面之注意事項再填寫本頁) 、1Τ -9. 經濟部中央標準局員工消费合作社印製 432518 u A7 ---'__ _ B7_ 五、發明説明(8 ) 一 <100>或<1 1 1>晶體本性。 該晶圓在兩端被覆蓋以移除因切片製程引起的不—致破 壞,並改善該晶圓的平行度和平坦度。該覆蓋研磨漿典型 上是碳化鋁或矽與甘油的混合物,雖然其他適合的覆蓋漿 也已商品化。因此由於切片和覆蓋所致的機械性破壞實質 上可以藉著化學蝕刻而移除。酸蝕刻藥劑和鹼蝕刻藥劑都 已商品化。 .… . 傳統化學/機械磨光製程通常可被使用來降低一晶圓的總 厚度變動Γττν”)及/或位置總指示讀數(,_STIR。至,最好 分別是大約0 _ 7 A m或0.5 " m。然而,根據本發明準備之半 導體晶圓僅需要初始傳統製程步驟平坦化該晶圓至一個可 能通常超過傳統粗磨光步驟可達到的中間値。較好的情況 下,該晶圓的中間値TT V及/或S TIR大約小於5〆m ;較佳 地是大約小於4 μ m而最好是大約小於3 μ m ;而最理想情況 是大約小於2 V m。 另外’雖然不需要,希望平坦化之晶圓具有在1 mm X 1 mm的面積上大約小於1 . 〇 nm的粗糙度(RMS),Ra。最好是 Ra在1mm X 1mm的面積上大約小於〇.5 nm。對本發明的目 的來説’該晶圓的平坦度和粗链度在初使平坦化步驟之後 可以選擇性地用任何適合的測量機構來測量以確認該晶圓 已達到所要的中間平坦度及/或粗糙度數値。 在一説明的初始平坦化步驟中,—梦晶圓被職固到一陶 瓷磨光區塊上,而它接著會被固接到一粗磨光器的臂上。 當粗磨光開始時,該磨光器臂降低至它與磨光器的陶瓷轉 盤上的硬墊相接觸。然後該轉盤旋轉而安定鈉膠質矽漿和 -11 - 本纸張尺度適用中國國家#準(CNS )六4说格(210X2们公釐) f讀先閲讀背面之注意寧項再镇寫本頁) -丁 --° 經濟部中央標準局負工消费合作社印策 4 3 2 5 1 8 at _________B7 五、發明説明(9 ) -㈣刻劑被分配到該蟄子表面。對—p型晶圓來説,該晶 圓的表雨在大約9 lb/in2及大约50巧5。〇下大約4〇〇至6〇〇 秒而被磨光。此磨光自該晶圓的表面移除大約16到18# m 的矽(Si<1〇0>)並降低了該晶圓之低頻表面粗糙度至不超 過2,0 nm Ra。最好是,該低頻表面粗糙度在此磨光步驟中 被降低至大約1 2 nm Ra到2.0 nm Ra。對本發明的目的來 説,以Nomarski顯微鏡在50x倍率下或以Wyki>_2D顯微 鏡裝備1 Ox倍率鏡頭所觀察到的低頻表面粗糙度是在從i 〇〇 "m到1 mm的側面頻寬中垂直峰對谷測量不超過15 nm。 高頻表面粗糙度是如由光散射儀器或AFM在從丨V m到1〇p m的側面頻寬中垂直峰對谷測量不超過3 nm下所測量的一 般模糊不清。 安定鈉膠質矽漿(Sodium stabilized colloidal SiliCa slurries)在此技藝中是廣爲人知的,並已被描述於u s.f Xu first read the notes on the back before filling in this page J, 1T οι. 4 3 25 1 8 a7 V. Description of the invention (4) Printing process of the film or semiconductor layer configuration by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumers Cooperatives; -A process to improve the yield of semiconductor wafers at a relatively low cost; _ a process to recover discarded I semiconductor wafers; a process to improve what has traditionally exceeded the maximum flatness specification A process for flatness of a planarized semiconductor wafer; a process for eliminating flatness sorting of semiconductor wafers; a process for forming a semiconductor wafer before polishing such a wafer. Therefore, briefly, the present invention is directed to a process for the preparation of semiconductor wafers having approximately less than ... TTV and / or STIR. The wafer is planarized for the first time using conventional techniques to reduce the wafer's ττν and / or STIR to -middle chirp. The distances between the front and back surfaces at discrete locations on the front surface of the wafer are then measured to produce thickness profile data, preferably using an ade. 9700 capacitor probe. On the other hand, other measurement methods that use other reference planes (such as measurement mechanisms that measure light or sound reflected from the wafer surface) can also be used to generate thickness profile materials. Then the excess raw material is removed on the front surface of the wafer in the second process step to reduce the thickness at each discrete point of the wafer to a target thickness L. The amount of raw material that should be removed at each discrete location is The mosquito is considered after considering the thickness of the material and Tt. The wafer may also go through—additional polishing steps. In addition, 'the process may include one or more conventional cleaning steps sequenced anywhere in the process', preferably directly followed by plasma assisted chemical engraving. This sequence and the step of removing excess material and raw material cause the wafer preparation to be better in flatness number 値 and / or yield than the beta that can be obtained by current traditional processes. The process of semiconductor wafer whose flatness number exceeds the maximum. According to this process (read the precautions on the back before you fill in this page) 4 、-= I --11 1.- οι. I i 1 .ji In g --I, the paper size is suitable for national standard Hua 5 2B 1 R. Description of the invention (A7 B7 was printed by the Ministry of Standards and Technology Bureau of the Central Government Bureau of Consumers and Consumers Cooperatives. The semiconductor wafer was initially prepared in the traditional way. Then the wafer was flat, and the minimum acceptable flatness was not met. In order to further flatten the wafers, the thickness profile data of the wafers that have been screened out are in accordance with the methods discussed above and used in this, the first embodiment of the present invention, and the remaining materials are the best. It is plasma-assisted chemical etching, and is removed from the front surface of the wafer 'to reduce the thickness of the wafer at each discrete point to-target thickness' D. The amount of raw material to be removed at each discrete location is between It is determined after considering the thickness profile and Tt. On the other hand, traditionally prepared wafers have not been picked. Instead, all wafers are subjected to an additional raw material removal step. This additional step can eliminate individual flatness Needs for the picking step, where needed The total thickness and / or position indication readings of each wafer may be greater than about 0.5 m and about 0,3 am, respectively. The present invention is also directed to a wafer group comprising at least 10 wafers, the crystal The circle has an average total thickness variation and / or an average position total indication reading that does not exceed about 1 _ ο V m, preferably about 0.7 / zm, more preferably about 0.5 " m, and most preferably about 0.2 am Some of the other purposes and characteristics are obvious, and some of them will be pointed out here. Brief description of the graphics * 'Figure 1 (a) is the initial TIR distribution of many traditional planarized wafers and many of the same Graphical illustration of the TIR distribution of a wafer after plasma-assisted chemical etching according to a specific embodiment of the present invention. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 111 jld ----- 4— ----- Cr (read the notice on the back of the book, please fill in this page) Printed by Shellfish Consumer Cooperative of Central Bureau of Standards, Ministry of Economic Affairs 4 3 251 8 V. Description of Invention (6) 'Figure 1 (b) is The initial ττν distribution of many conventional planarized wafers and many of the same wafers are based on A graphical illustration of the distribution of τ τ ν after electrical assisted chemical silver engraving in a specific embodiment of the invention. Figure 1。 is the initial STIR distribution of many conventional planarized wafers and many of the same wafers according to the present invention-specific embodiments A graphical illustration of the STIR distribution after ZD-assisted chemical etching. ^ Figure 2U) and 2 (b) are the initial S.TIR distribution (back-referenced central focal length) of a group of traditional planarized wafers and the same wafers are based on The present invention—a specific example (a graphic illustration of s T R R after plasma-assisted chemical etching) (back reference central focal length). ^ Figures 3 (a) and 3 (b) are a group of traditional planarized wafers selected from the wafers shown in Figure 2 (a) * 2 (b). Graphical illustration of the STIR distribution (location optimal reference plane) after plasma-assisted chemical etching according to a specific embodiment of the present invention. Figure 4 (a) is a graphical illustration of the initial SFPD distribution of a number of conventional planarized wafers according to an embodiment of the present invention. Figures 4 (d) and 4 (b) and 4 (c) are a group of conventional planarized wafers selected from the wafers shown in Figure 4 (昀) after plasma-assisted chemical etching at three different positions. Graphical illustration of the SFPD distribution. Figures 5 (a) and 5 (b) are the initial STIR distributions of many conventional planarized and polished wafers, and the same wafers are respectively plasma-assisted according to the present invention-a specific embodiment. Graphical illustration of the STIR distribution after chemical etching. Figure 6 is the initial s τ distribution of many conventional planarized wafers and the paper ft ruler of the same wafer after plasma-assisted chemical etching according to a specific embodiment of the present invention ΙΐΙί is home; 缚 bound (CNS) Λ4 specification (2IGX 297), ^ ~ ^ — I —.-- Γ .--.---- Q ------ Ί. ^ ------- -(Please read the notes on the back before filling in this page) 432518 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, M Industrial Consumer Cooperative A7 B7 V. Description of the invention (7) Graphical description of the STIR distribution. According to the present invention, it has been found that the overall and / or local flatness of a semiconductor wafer and a given production yield can be achieved by The semiconductor wafer is assembled and correctly arranged with an additional material removal step, preferably-a plasma-assisted chemical etching step, which is improved compared to the conventional planarization process. It has an improvement compared to the current conventional process. The global and local position flatness variation numbers can be prepared according to the process of the application. In addition, the combination of the additional substance removal step in the conventional planarization process can cause one or more of the normal additions to the planarization process. Relaxation of process pressure. The material removal rate and flatness of the wafer in the traditional process depend on various operating factors, such as temperature, pressure, contact material and processing technology, spin rate and slurry compounds. For example, a Slower polishing rates result in a flatter surface. These variables typically must be strictly controlled to prepare a wafer with a uniform minimum flatness. In order to achieve the target wafer flatness, these variables are In terms of selection, a larger range is more likely to combine additional material removal steps into the traditional process. The process of the present invention uses A semiconductor wafer sliced from a single crystal metal block is the starting material. Silicon is a good material for this wafer, because its conductivity type and resistivity are not critical. The wafer may have any suitable for a semiconductor Applied diameter and target thickness. For example, the diameter may be 4 to 8 inches (100 to 200 mm) or larger, and the thickness may be 475 to 725 " claw or larger. The thickness usually increases as the diameter increases β This wafer may also have any crystal nature (〇Γ 丨 entat 丨 〇η). However, usually this wafer has ___ -10- This paper size is applicable (please read the precautions on the back before filling this page ), 1T -9. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 432518 u A7 ---'__ _ B7_ V. Description of the invention (8) A < 100 > or < 1 1 1 > The wafer is covered at both ends to remove non-destructive damage caused by the slicing process and improve the parallelism and flatness of the wafer. The overlay slurry is typically an aluminum carbide or a mixture of silicon and glycerol, although other suitable overlay slurry are also commercially available. Mechanical damage due to slicing and covering can therefore be removed essentially by chemical etching. Both acid etching agents and alkali etching agents have been commercialized. ... Traditional chemical / mechanical polishing processes can often be used to reduce the total thickness variation of a wafer Γττν ″) and / or the total position indication (, _STIR. To, preferably about 0 _ 7 A m or 0.5 " m. However, a semiconductor wafer prepared according to the present invention only requires an initial conventional process step to planarize the wafer to an intermediate chirp that may generally exceed that achievable with a conventional rough polishing step. Preferably, the crystal The middle 値 TT V and / or S TIR of the circle is about less than 5〆m; preferably less than about 4 μm and most preferably less than about 3 μm; and most ideally less than about 2 V m. No, it is desirable that the planarized wafer has a roughness (RMS) of less than 1.0 nm on an area of 1 mm X 1 mm, Ra. It is preferable that Ra is less than about 0.5 on an area of 1 mm X 1 mm. nm. For the purpose of the present invention, 'the flatness and thick chain of the wafer can be optionally measured with any suitable measuring mechanism after the initial flattening step to confirm that the wafer has reached the desired intermediate flatness. And / or roughness data. In the planarization step, the dream wafer is fixed to a ceramic polishing block, and it is then fixed to the arm of a rough polisher. When the rough polishing starts, the polisher arm Lower to the point where it comes into contact with the hard pad on the ceramic turntable of the polisher. Then the turntable rotates and stabilizes the sodium colloidal silica slurry and -11-This paper size is applicable to China National Standard #CNS (CNS) 6 4 cells (210X2men (Mm) f read the first note on the back of the page and write this page on Ningxiang)-Ding-° Printing policy of the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 3 2 5 1 8 at _________B7 V. Description of the invention (9)- An etchant is dispensed to the surface of the ladle. For a p-type wafer, the surface rain of the wafer is about 9 lb / in2 and about 50 ° C., and about 400 to 600 seconds. Polished. This polishing removes approximately 16 to 18 # m of silicon (Si < 100 >) from the surface of the wafer and reduces the low-frequency surface roughness of the wafer to no more than 2,0 nm Ra Preferably, the low-frequency surface roughness is reduced in this polishing step to approximately 12 nm Ra to 2.0 nm Ra. For the purposes of the present invention, a Nomarski microscope at 50 The low-frequency surface roughness observed at x magnification or with a Wyki> _2D microscope equipped with a 1 Ox magnification lens is a vertical peak-to-valley measurement of no more than 15 nm in the side bandwidth from 〇〇 " m to 1 mm. High Frequency surface roughness is generally ambiguous as measured by a light-scattering instrument or AFM in a sideband from 丨 V m to 10pm with vertical peak-to-valley measurements not exceeding 3 nm. Sodium stabilized colloidal SiliCa slurries) is well known in this art and has been described in us.

Patent No. 3,1 70,273 中。Syton HT-50,一種建議的 ,並已由 E . I · d u Ρ 〇 n t d e N e m 〇 u r s & C 〇 m p a n y 在商業 上應用的安定鈉膠質矽漿’具有4 9.2 _ 5 〇 . 5 %的二氧化矽含 量及35-50ym的分子大小。該安定鈉膠質矽漿在從大約5〇 到8 0 m 1 / m i η的流動速率下分配。 該驗性蝕刻劑最好是—具有ρ Η値範圍從丨i到丨4的月安強 化腐强溶劑。一適合的蝕刻溶劑可以包含從大約1 . 〇到1 · 5 wt.%的氫氧化鉀,從大約〇.5到13 wt.%的二氨乙烯和剩 餘爲蒸餾水。該鹼性蝕刻劑流通常在膠質矽漿流啓動1 2秒 後開始,並在膠質矽漿流停止後繼續大約6 〇秒。鹼性蝕刻 __ -12_ 本紙張尺度適用中國國家橾準(CNS ) A4規格(210X297公嫠) --.----L--.---Q^.-------1 J------οι (#先閏讀背面之注意事項再填寫本頁) 經濟部中央標嗥局員工消货合作社印繁 43 2 5 1 8 Α7 __ Β7 五、發明説明(10 ) 劑被提供在從大約8 0到1 2 0 m 1 / m i η範圍的流動速率下。雖 然一驗性蚀刻劑的使用在原料移除後並不需要,在不用鹼 性蚀刻劑的相同粗磨光中被磨光之晶圓間的原料移除中仍 有高度的差異。 該安定鈉膠質矽漿和鹼性蝕刻劑最好是被分配至—Patent No. 3, 1 70,273. Syton HT-50, a suggested and commercially available stable sodium colloidal silica slurry 'E. I. du Pontne Neurs & Cmpany' has 4 9.2 _ 5 0.5% Silicon dioxide content and molecular size of 35-50ym. The stable sodium colloidal silica slurry is dispensed at a flow rate from about 50 to 80 m 1 / m i η. The verification etchant is preferably a moon-enhanced strong solvent having a ρ Η 値 ranging from 丨 i to 丨 4. A suitable etching solvent may contain from about 1.0 to 1.5 wt.% Potassium hydroxide, from about 0.5 to 13 wt.% Diamethylene, and the remainder is distilled water. The alkaline etchant flow usually begins 12 seconds after the colloidal silica flow is started and continues for approximately 60 seconds after the colloidal silica flow is stopped. Alkaline etching __ -12_ This paper size is applicable to China National Standard (CNS) A4 specification (210X297 cm) --.---- L --.--- Q ^ .------- 1 J ------ οι (#Read the precautions on the back before filling out this page) Employees' Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs, India and India 43 2 5 1 8 Α7 __ Β7 V. Description of the Invention Provided at flow rates ranging from approximately 80 to 120 m 1 / mi η. Although the use of a qualitative etchant is not required after raw material removal, there is still a high degree of difference in raw material removal between wafers that have been polished in the same rough polishing without an alkaline etchant. The stable sodium colloidal silica and alkaline etchant are preferably distributed to—

Polyurethane impregnated felt 墊,諸如由 Rodel 〇f Scottsdale,Arizona在商業上應用的Suba H2墊。使用 於粗磨光或完成磨光中正確的磨光整在此枝藝中是廣爲人 知的3 接著該晶圓被以酸中止劑處理大約1 〇到4 〇秒以中和應用 在該晶圓的鹼性蝕刻劑和溶漿。該晶圓也在從大約1 〇 〇到 1 0 0 0 ml/miη的流動速率下以水漂洗大約1 〇到3 〇秒。該酸 中止劑及水之漂洗可以同時或依序地實施。該磨光臂接著 被舉起而陶瓷塊被解固並以水漂洗。 該酸中止劑包含一具有大约100, 〇〇〇到1,〇〇〇,〇〇〇之平均 分子量的多元醚(polyether)多燒(p〇ly〇l)和—有機或無機 酸或其混合物。一代表性的中止劑是由在蒸齒水中大約 0.01 到 0.1 v/t.%的多元酸(polyether) polyol,大約 0.2 到 0 _ 5 w t. % 的異丙貌(i s 〇 p r o p a η ο 1),大約 〇 . 5 到 5 . 〇 wt. %的過氧化氫(hydrogen peroxide)所組成,以醋酸或 硫酸調整至卩15値3.4到3.6。一適合的多元酸(9〇3^61;}161·) 多烷(polyol)是 Poly ox WSR N-3 000,由 Union Carbide 商業 化應用的水溶樹脂,並具有大約4 0 0,0 〇 〇的分子量。該酸 中止劑在大約4 0 0到8 0 0 m I / m i η的速率下分配。 本紙張尺度適用中國國家標準(CNS ) A4规格(210X297公釐) !d------ir—-----ζχ (諳先閲讀背面之注意事項再填寫本頁) 43 25 1 8 A7 五、發明説明(11 經濟部中央標準局1^工消贽合作社印製 在相始平坦化步驟之後,該晶固的點對點厚度輪廓資料 被產生並對應該晶圓前表面位置與在足夠數目之離散位置 處產生的資料以保證對該晶圓全部表面的覆蓋。因此S 教位置的數目至少爲2,最好至少10,更希望至少大約剛 ’再更好至少大約100G ’而對某些應用來説,最好的情況 是至少5,0 0 0。 使用來產生這資料的厚度測量工具可以是一個電容,光 干涉,F TIR,或機械(如微距儀)厚度測量工具。然而最好 疋,由具有至少大約〇 . 5 &quot; m,更希望是至少大約〇 ,丨&quot;加的 解析度之電容厚度測量工具。一具有大約〇1到〇 2&quot;111的 解析度之電容厚度測量工具已由ADE c〇rp〇raU〇n (Newton,ΜΑ)使用ADE 72⑽之商標而在萌業上應用。 然而最好使用ADE 9700電容厚度測量工具。在操作上, 在這些工具的平行板電容器中矽晶圓的使用導致電容的改 變。該電容改變可能有關於該晶圓之厚度及其有效介電常 數。其餘的討論集中在電容測量工具對説明目的的使用。 一個精於此技藝者可以修正在此揭示的具體實施例,以其 他在此技藝中熟知’且可測量基於參考平面之平坦度,而 與電容測量工具所使用的不同的測量機構來取代這電容測 量工具。 値得注意的’該晶圓TTV及/或STIR的降低可以使用對 厚度輪廓資料和該晶圓目標厚度T t做運算的演算法來計算 。舉例來説,要被移除的量可以藉由從在各離散位置上的 厚度輪廓資料減去目標厚度Tt所得兩數値的差而決定,其 ί — ι——d (請先閱讀背面之注意事項再填寫本頁) --ίΊ J---- 9. 本紙張尺度適用中國國家標4*· ( CNS ) Λ4規格(210 X 297公漦) • I - ....... I . - U ― 1 I ml 經濟部中央標準局員工消t合作社印製 432518 A7 ______________B7 五、發明説明(l2 ) 建乂 了在日日圓則表面各離散位置上要達到目標厚度t所必 須被移除的原料量,並因此最小化TTV及/或STIR。 一旦要從該晶圓各離散位置上移除的物質量被決定了, 這資訊就被處理而轉換爲一停留時間對位置的對應圖,其 被使用在原料移除步驟中控制原料移除工具。這原料移除 步驟可以使用任何能夠局部精準地從該晶圓前表面的小區 域移除原料的工具來執行。舉例來説,這工具寸以是一個 具有微磨光頭的化學/機械磨光工具。然而,最好它是一個 在 U.S. Patent Nos‘ 4,668,366,5,254,830,5,291,415, 5,375,064,5,376,224 及 5,4 91,571 中描述之型式的 pace 移除 工具,其已由IPEC/Precision,Inc.以PWS-200商標在商 業上應用了。 在該原料移除步驟之後,該晶圓具有小於丨&quot;m的TTV, 最好是具有大約小於0.7 &quot; m的TTV,再更好是具有大約小 於0.5a m的TTV,再更好是具有大約小於0.4&quot; m的TTV ,再更好是具有大約小於0.2 a m的TTV,+而最理想化是具 有大約小於0 1 &quot; m的TT V。另一方面或更進一步.説,該晶 圓具有小於1只m的STIR ’最好是具有大约小於〇.7α m的 STIR,再更好是具有大約小於0.5# m的STIR,再更好是 具有大約小於0.3&quot; m的STIR,再更好是具有大約小於0.2 y m的STIR,而最理想化是具有大約小於〇. 1 # m的STIR 。該晶圓最終的TTV及/或S TIR値藉由精確地映射該晶圓 的厚度並使用該映射圖在原料移除步驟中精準薄化該晶圓 。在該原料移除步驟期間,最好是有至少l.Oym的原料自 -15- 本紙张尺度適用中國國家標準(CNS ) A4规格(2丨0&gt;&lt;297公釐) : Γ- . 0^------Ί ^ J-------ΟΊ {諳先閏讀背面之注意寧項再填寫本頁) ^251 0 A7 B7 五、發明説明(13 ) 眾晶圓移除,更好是有至少2.〇&quot;m,再更好是有至少大約 m的原料在原料移除步驟中自該晶圓移除。 在原料移除之前及/或之後,該晶圓可依意思清潔以移除 諸如溶毁粒子和在初始平坦化步驟中引入的金屬及在原料 移除期間藉由電漿而沉澱在晶圓表面的硫等等的雜質。該 晶圓可能使用任何適合而不會實質上影響該晶圓厚度輪廓 的清潔程序來清潔。這種清潔程序在此技藝中爲人所熟知, 舉例來説’包括RCA方法(啪述於F. Shimura, SemicnndHr.tnr .Silicon Crystal Technology (Academic Press 1 98 9), pp. 1 8 9 -1 9 1 ) ’或一正確的水漂洗。 在原料移除之後,該晶圓可依意思實施一&quot;吻觸,,(或完成 )磨光以降低表面粗糖度(r m s ),R a。電漿晶圓薄化製程通 常會留下帶有高度表面粗輕度(r m S)的&lt;5夕晶圓表面,例如以 一原子力顯微鏡(A F Μ)所測得的一般。因此,最好電漿钱 刻之晶圓表面的粗糙度被降低至—小於該粗糙程度的値。 取好’邊粗糖度R &amp;,被降低至1 m m X 1 m m面積上大约 1.0 nm的數値,更好些,是該粗糙度,被降低至1 mm X 1 mm面積上大約0·5 nm的數値,而最佳的情況,該粗糙 度Ra,被降低至1 mmX1 mm面積上大約1.0 nm的數値》 吻觸磨光並非如鏡般地降低反射光(模糊)而加強該晶圓表 面的鏡射性。一未磨光之晶圓在其表面上包括高及低頻粗 链度組成。高頻粗糙度由於模糊而導致表面高度光散射。 該”吻觸”磨光最小化了高和低頻粗糙度並降低了模糊。 決定移除量的演算法如下:決定電漿蝕刻之表面的峰 -16- 本紙張尺度適用中國國家標準(CNS ) A4規格(2】0X297公釐) (諳先閱讀背面之注意事項再填寫本頁)Polyurethane impregnated felt pads, such as the Suba H2 pad commercially used by Rodeloff Scottsdale, Arizona. The correct finish used in rough or finish polishing is well known in this art. 3 The wafer is then treated with an acid stopper for about 10 to 40 seconds to neutralize the application on the crystal. Round alkaline etchant and solvent. The wafer is also rinsed with water at a flow rate from about 1000 to 1000 ml / miη for about 10 to 30 seconds. The acid-stopping agent and the rinsing with water may be performed simultaneously or sequentially. The polishing arm is then lifted and the ceramic block is solidified and rinsed with water. The acid terminator comprises a polyether polyether (polyol) having an average molecular weight of about 100,000 to 10,000, and an organic or inorganic acid or a mixture thereof. . A typical stopping agent is a polyether polyol of about 0.01 to 0.1 v / t.% In steamed water, and an isopropyl appearance of about 0.2 to 0 _ 5 w t.% (Is 〇propa η ο 1 ), Consisting of about 0.5 to 5.0 wt.% Hydrogen peroxide, adjusted to 卩 15 値 3.4 to 3.6 with acetic acid or sulfuric acid. A suitable polyacid (90.3 ^ 61;) 161 ·) polyol is a water-soluble resin that is commercially used by Poly ox WSR N-3 000, and has about 4 0,000. Molecular weight. The acid-terminating agent is dispensed at a rate of about 400 to 800 m I / m i η. This paper size applies to China National Standard (CNS) A4 specification (210X297 mm)! D ------ ir —----- ζχ (谙 Please read the notes on the back before filling this page) 43 25 1 8 A7 V. Description of the invention (11 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, 1 ^ Industrial Consumers' Cooperative. After the initial flattening step, the crystal-solid point-to-point thickness profile data is generated and corresponds to the position of the front surface of the wafer and a sufficient number. The data generated at discrete locations to ensure the coverage of the entire surface of the wafer. Therefore, the number of S teach positions is at least 2, preferably at least 10, more preferably at least about 'and better at least about 100G' and for some For applications, the best case is at least 5, 0 0 0. The thickness measurement tool used to generate this information can be a capacitive, optical interference, F TIR, or mechanical (such as a macrometer) thickness measurement tool. However, most Anyway, a capacitor thickness measurement tool having a resolution of at least about 0.5 &quot; m, and more preferably at least about 〇, 丨 &quot; plus. A capacitor thickness having a resolution of about 〇1 to 〇2 &quot; 111 The measurement tool has been developed by ADE c〇r p〇raUn (Newton, MA) is used in the Moe industry using the ADE 72⑽ trademark. However, it is best to use the ADE 9700 capacitor thickness measurement tool. In operation, the use of silicon wafers in parallel-plate capacitors for these tools. Changes in capacitance may be related to the thickness of the wafer and its effective dielectric constant. The rest of the discussion focuses on the use of capacitance measurement tools for illustrative purposes. A person skilled in the art can modify the specifics disclosed herein This embodiment replaces the capacitance measurement tool with another measurement mechanism that is well known in the art and that can measure the flatness based on the reference plane, and which is different from that used by the capacitance measurement tool. Note that the wafer TTV and The reduction in STIR can be calculated using an algorithm that operates on the thickness profile data and the target thickness T t of the wafer. For example, the amount to be removed can be calculated from the thickness profile data at discrete locations. Determined by subtracting the difference between the target thickness Tt and two numbers 其 — ι — d (Please read the precautions on the back before filling this page)-) J ---- 9. This paper Standards apply to China National Standard 4 * · (CNS) Λ4 specifications (210 X 297 cm) • I-....... I.-U ― 1 I ml Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, printed by a cooperative 432518 A7 ______________B7 V. Description of the Invention (l2) The amount of raw materials that must be removed to achieve the target thickness t at various discrete positions on the surface of the yen and yen, and thus minimize TTV and / or STIR. Once from the crystal The amount of material removed at each discrete position of the circle is determined, and this information is processed and converted into a dwell time versus position map that is used to control the material removal tool in the material removal step. This raw material removal step can be performed using any tool capable of locally and accurately removing raw materials from a small area on the front surface of the wafer. For example, this tool is a chemical / mechanical polishing tool with a micro-polish. However, preferably, it is a pace removal tool of the type described in US Patent Nos' 4,668,366, 5,254,830, 5,291,415, 5,375,064, 5,376,224, and 5,4 91,571, which have been developed by IPEC / Precision, Inc. The PWS-200 trademark is commercially used. After the raw material removal step, the wafer has a TTV of less than &quot; m, preferably a TTV of less than about 0.7 &quot; m, even more preferably a TTV of less than about 0.5am, and even more preferably A TTV less than about 0.4 &quot; m, and even more preferably a TTV with less than about 0.2 am, and most ideally a TTV with less than about 0 &quot; m. On the other hand, or even further, it is said that the wafer has an STIR of less than 1 m, preferably having an STIR of less than about 0.7 m, still more preferably having an STIR of less than about 0.5 m, and even more preferably 1 has an STIR less than about 0.3 &quot; m, even more preferably has an STIR less than about 0.2 ym, and most preferably has an STIR less than about 0.1 #m. The final TTV and / or STIR of the wafer accurately maps the thickness of the wafer and uses the map to accurately thin the wafer during the material removal step. During this raw material removal step, it is preferable to have at least l.Oym of raw materials from -15- This paper size is applicable to Chinese National Standard (CNS) A4 specifications (2 丨 0 &gt; &lt; 297 mm): Γ-. 0 ^ ------ Ί ^ J ------- 〇Ί (谙 Please read the note on the back and fill in this page first) ^ 251 0 A7 B7 V. Description of the invention (13) Removal of many wafers More preferably, there is at least 2.0 m, and even more preferably, at least about m of raw materials are removed from the wafer in the raw material removing step. Before and / or after the raw material is removed, the wafer can be cleaned as desired to remove materials such as dissolved particles and metals introduced during the initial planarization step and deposited on the wafer surface by plasma during raw material removal. Impurities like sulfur. The wafer may be cleaned using any cleaning procedure that is suitable without substantially affecting the thickness profile of the wafer. This cleaning procedure is well known in the art, for example, 'including the RCA method (described in F. Shimura, SemicnndHr.tnr. Silicon Crystal Technology (Academic Press 1 98 9), pp. 1 8 9 -1 9 1) 'Or a correct water rinse. After the raw material is removed, the wafer may be subjected to &quot; kissing, and (or completed), polishing as desired to reduce the surface coarse sugar content (r m s), R a. Plasma wafer thinning processes often leave <5x wafer surfaces with a high degree of surface roughness (r m S), as measured by an atomic force microscope (AFM), for example. Therefore, it is desirable that the roughness of the wafer surface etched by plasma is reduced to a value smaller than this roughness. Take the 'Roughness R &amp; of the side and reduce it to a number of approximately 1.0 nm on an area of 1 mm X 1 mm, and more preferably, the roughness is reduced to approximately 0.5 nm on an area of 1 mm X 1 mm. The roughness Ra is, in the best case, reduced to a value of about 1.0 nm in an area of 1 mm × 1 mm. Kissing polishing does not reduce the reflected light (blurring) like a mirror to strengthen the wafer. Specularity of the surface. An unpolished wafer includes high and low frequency coarse chain components on its surface. High-frequency roughness results in a high degree of light scattering on the surface due to blurring. This "kiss touch" polishing minimizes high and low frequency roughness and reduces blur. The algorithm to determine the removal amount is as follows: determine the peak of the plasma etched surface -16- This paper size applies the Chinese National Standard (CNS) A4 specification (2) 0X297 mm page)

Q ,-=-°Q,-=-°

TT

C A7 B7 432518 ----__ 五、發明説明(I4 ) Γ’Ρ”)對谷(&quot;V”)粗糙度,r(p_v) ; (2)使用一完成型溶(如 稀釋Glanzox)而設計_磨光製程以移除大約3r(p_v)到 4r(p-v);以及(3)傳統11(:入型式清潔。移除這小量的矽通 常不會損傷該晶圓的平坦度。 通常,在這磨光步驟中會移除大約I到3〇() nan〇meters 的矽。這磨光可以在一使用如稀釋氨水安定膠質矽漿及傳 統磨光設備的化學/機械磨光製程中被實施。建.議的氣水安 定膠質矽漿是Glanzox 3 900 ,它已由FujimiC A7 B7 432518 ----__ 5. Description of the invention (I4) Γ'P ") Roughness (&quot; V") roughness, r (p_v); (2) Use a complete solution (such as diluted Glanzox) The design and polishing process is designed to remove about 3r (p_v) to 4r (pv); and (3) traditional 11 (: in-type cleaning. Removing this small amount of silicon usually does not damage the flatness of the wafer. Usually, about 1 to 30 (nanometers) of silicon is removed during this polishing step. This polishing can be performed in a chemical / mechanical polishing process using dilute ammonia to stabilize colloidal silicon slurry and traditional polishing equipment It was implemented. The recommended gas-water stabilization colloidal silica gel is Glanzox 3 900, which has been developed by Fujimi

Incorporated of Aichi Pref· 452, japan在商業上應用 。Glanzox 3900具有大約8到10%的矽含量及大約〇.〇25 卢m到〇 . 〇 3 5 # m的分子大小。如果氨水安定膠質矽漿沒有 在使用前稀釋’該磨光之晶圓不會像以稀釋溶漿處理的一 般平坦。大約一份矽漿到十份去離子水的稀釋法是較建議 的0 '广型晶圓通常做完成磨光大約3 〇 〇秒,然後是停止狀態。 對P ·型晶圓來説傳統完成磨光時間是大約2 4 〇秒。在磨光之 後,該基體可隨意思實施適當的清潔程序,諸如一標準清 潔溶劑如h2o-h2o2-nh4oh的使用。 本發明的這一具體實施例在具有分別小於0.7 V m和0.5 Θ m的TTV及/或STIR之超平坦晶圓的準備上提供了特別的 優點。另一方面,對平坦度規格低至〇.7&quot;m ττν和〇·5β m STIR來説,接近1〇〇%的良率是可能的。因此,本具體 實施例消除了平坦度規格只需要分別大於〇 . 7 P m和〇 . 5芦m 的TTV及/或STIR的晶圓之平坦度揀選的需要。傳統晶圓 -17- 本紙張尺度適用中國國家標準(CNS ) Λ4規格(210Χ 297公釐) -ft 讀 背 ιέ 之 注 意 事 項 再 頁 經濟部中央標準局員工消贽合作社印?本 A7Incorporated of Aichi Pref. 452, Japan is commercially used. Glanzox 3900 has a silicon content of about 8 to 10% and a molecular size of about 0.0225 m to 0.35 #m. If the ammonia stabilized colloidal silicon slurry is not diluted before use, the polished wafer will not be as flat as that treated with a dilute solution. The dilution method of about one part of silicon slurry to ten parts of deionized water is more recommended. 0 'wide wafers are usually polished for about 300 seconds and then stopped. For P-type wafers, the conventional polishing time is approximately 240 seconds. After polishing, the substrate can be subjected to appropriate cleaning procedures, such as the use of a standard cleaning solvent such as h2o-h2o2-nh4oh. This particular embodiment of the invention provides particular advantages in the preparation of ultra-flat wafers with TTV and / or STIR less than 0.7 V m and 0.5 Θ m, respectively. On the other hand, for flatness specifications as low as 0.7 &lt; m ττν and 0.5 β m STIR, a yield close to 100% is possible. Therefore, this specific embodiment eliminates the need for flatness specifications that only require TTV and / or STIR wafer flatness sorting of greater than 0.7 P m and 0.5 μm, respectively. Traditional wafer -17- This paper size applies the Chinese National Standard (CNS) Λ4 specification (210 × 297 mm) -ft Read the note of the matter Note page Reprint by the staff of the Central Standards Bureau of the Ministry of Economic Affairs? Ben A7

4 3 2 5 1 8 經濟部中央標準局炅工消t合作社印^ 準備製程需要這種平坦度揀選。另外,本發明的製程在傳 統平垣化和磨光步驟的處理上也提供了特別的優點。這些 優點出現在選擇初始平坦化及磨光變數値時額外的靈活性 上’藉由額外物質移除步驟之組合而使得數値的選擇變得 可能。 ’ 镯 1〇),1(b),2(a),2(b),3(a),3(b),4(a),4(b),4(c),4(d)和 6说明了根據本發明具體實施例在平坦度上的改善'。 在一第二具體實施例中,該原料移除步驟可被組合到晶 圓準備製程中而在傳統晶圓準備之後。通常,已經由傳統 製程準備的晶圓,亦即平坦化後完.成磨光者,被使用厚度 測量工具(諸如前面討論的A D E 7 2 0 0電容測量工具)測量以 決疋i們的TTV及/和STIR數植,並揀選進一群超過一明 確平坦度數値的晶圓’和一第二群的滿足該明定平坦度數 値的晶圓。這些晶圓可能被測量並基於整體平坦度及/或局 邵位置平坦度來揀選。那些具有超過最大明定値之ττν及/ 和s TIR的晶圓通常就被丟棄。丟棄的晶圓量通常的範圍, 舉例來説,高到一給定之2 〇 〇 m m直徑晶圓生產的3 %。然 而’對較緊的平坦度規格來説,這數値可能增加到給定生 產的1 0 %到3 0 %。 然而’已經發現這樣的被丟棄之晶圓可以被經濟地處理 以改吾其平坦度至一可接受的程度。在本發明的這個具體 實施例中,傳統上準備的晶圓基於其整體平坦度及/或局部 位置平坦度而被楝選成一群或多群。在那些群中具有超過 一最大明定値之TTV及/和STIR的晶圓被測量以產生厚度 -18- 本紙张尺度適用中國國家標準(CNS ) Μ規格(210X297公釐) - : . Ί ^ Ji i I &quot; (讀先聞讀背面之注意事項再填寫本頁) 4 3 2 5 1 8五、發明説明(】6 A7 B7 經漪部中央標準局負工消f合作社印製 輪廊資料。然後這些晶圓被實施一額外的原料移除步驟, 最好是;-電衆輔助化學银刻步驟,和選擇的再次完成磨光 以移除任何多餘的表面粗糙度並修復該晶圓的可反射表面 。這些額外的步驟以實際上與先前所揭示本發明第—具體 實施例相同的方式操作。 八組 最好是,該丢棄晶圓的TTV及^STIR被降低至大約小 於;更好是至大約小於〇.4#m ;再更好是至大約小 於0.3广m :再更好是至大約小於〇.2 /^m ;而最理想是,至 大約小於0·1ρ m。另外,雖然不需要,仍希望在這樣的額 外原料移除步驟之後,該丟棄晶圓具有在1 mm mm面 積上大約小於1.0 nm的表面粗糙度(RMS),。較希望是 Ra爲在1 mrnX ;! mm面積上大約小於〇 5 nm。對本發明的 目的來説,該晶圓在粗磨光步驟之後的平坦度和粗糙度可 隨意思使用任何適合的測量機構來測量以確認該晶圓已達 到目標平坦度及/和目標粗链度。 另一方面,該測量機構可被使用來對所有傳統準備之晶 圓測量並產生厚度輪廓資料。然後所有的晶圓基於這厚度 輪廓資料而實施一原料移除步驟,用實際上與先前所揭示 相同的方式來做。圖5 (a)和5 ( b)説明了根據本發明這一具 體貫施例對已丟棄晶圓在平坦度上的改善。這些平坦化之 晶圓可随意思實施”吻觸&quot;磨光。 本發明的這些具體實施例藉由提供一種復原未滿足目標 厚度之晶圓的方法’有利地改善了給定半導體晶圓生產的 良率。另一處理所有晶圓的具體實施例進—步降低或消去 (讀先開讀背面之注^一^^^再填寫本育) ^私--------- 訂 .9. -19- 本紙張尺度適用中國囡家標隼(CNS ) Μ現格(210X297公疫 a 5 18 A7 B7 钰濟部中央標率局貝工消費合作社印製 五、發明説明(Π ) 了有關平坦度楝選’諸如增加晶圓準備之週期時間,複雜 的材料流程’以及增加晶圓製造成本的缺點。 本發明的晶圓平坦化製程也能夠做爲具有嚴格TTV及/和 STIR數値分佈的半導體晶圓集團的準備。也就是指,至少 大約1 0個基體的集團,最好是至少大約2 5個基體,可以被 準備而具有不超過大約的晶圓平均TTV及/和STIR ,最好是大約0.7/im,更好是大約〇.5&quot;m,再更好是大約 〇 · 3 # m ’最理想是大約〇 2 # m。 在本發明的又另一具體實施例中,該額外原料移除步驟 可以组合在該晶圓的初始化學/機械磨光,或粗磨光之前。 蓀原料移除步驟可以用來造形該晶圓以彌補任何由於隨後 I粗磨光步驟所致的平坦度下降。舉例來説,某些粗磨光 製程可能給予該晶圓凸的外形。該額外原料移除步驟可以 被使用來修補由於移除原料所致的這個問題,在粗磨光之 前給予該晶圓凹的外形。於是該晶圓隨後的粗磨光造成了 沒有凸出的晶圓。因此,該晶圓在粗磨光之前原料移除步 驟的组合,相對於傳統上在粗磨光之後所得的平坦度,其 改善了該晶圓在粗磨光之後的晶圓乎坦度。該晶圓隨後的 冗成磨光通常不會使該晶圓的平坦度下降。 在以上各個具體實施例中,可能希望在原料移除之前及/ 或之後選擇性的清潔該晶圓以移除諸如溶裝粒子和在初始 或中間步驟中引人的金屬及在原料移除期間藉由電漿而沉 Μ㈣等等的雜質。該晶圓可以使用任何不會 實質上影響該晶圓厚度輪廓的適當的清潔程序來清潔。這 (請先閱讀背面之注意事項再填寫本頁} * *1 -------^訂—:---------;--^--^---r .4 3 2 5 1 8 The Central Bureau of Standards, Ministry of Economic Affairs, Machining and Consumer Cooperatives, etc. ^ The preparation process requires such flatness picking. In addition, the process of the present invention also provides special advantages in the processing of the conventional spheronization and polishing steps. These advantages appear in the additional flexibility in selecting the initial planarization and polishing variables ′, which makes the selection of data possible through a combination of additional substance removal steps. '' Bracelet 1〇), 1 (b), 2 (a), 2 (b), 3 (a), 3 (b), 4 (a), 4 (b), 4 (c), 4 (d) And 6 illustrate the improvement in flatness according to a specific embodiment of the present invention '. In a second embodiment, the raw material removal step may be combined into the wafer preparation process after the conventional wafer preparation. Usually, wafers that have been prepared by traditional processes, that is, flattened. Finished polishers are measured using a thickness measurement tool (such as the ADE 7 2 0 capacitance measurement tool discussed earlier) to determine their TTV. And / or STIR data, and select a group of wafers that exceed a specified flatness number 値 and a second group of wafers that satisfy the specified flatness number 値. These wafers may be measured and sorted based on overall flatness and / or local position flatness. Those wafers with ττν and / and s TIR that exceed the maximum specified 値 are usually discarded. The amount of discarded wafers typically ranges, for example, up to 3% of a given 2000 mm diameter wafer produced. However, for tighter flatness specifications, this number may increase to 10% to 30% of a given production. However, 'it has been found that such discarded wafers can be economically processed to change their flatness to an acceptable level. In this particular embodiment of the invention, the wafers traditionally prepared are selected into one or more groups based on their overall flatness and / or local position flatness. Wafers with TTVs and / or STIRs in those clusters with more than one of the largest defined dimensions were measured to produce a thickness of -18- This paper size applies the Chinese National Standard (CNS) M specification (210X297 mm)-:. Ί ^ Ji i I &quot; (Read the notes on the back and then fill out this page) 4 3 2 5 1 8 V. Description of the invention () 6 A7 B7 The Ministry of Standards and Industry of the Ministry of Economic Affairs of the Central Bureau of Work and F Cooperatives printed the information on the corridor. These wafers are then subjected to an additional raw material removal step, preferably;-an electro-assisted chemical silver engraving step, and optionally refinishing to remove any excess surface roughness and repair the wafer. Reflective surface. These additional steps operate in substantially the same way as the first embodiment of the present invention previously disclosed. Preferably, the eight sets of TTV and ^ STIR of the discarded wafer are reduced to approximately less than; better To about less than 0.4 m; even more preferably to less than about 0.3 m; even more preferably to less than about 0.2 m; and most preferably to about less than about 0.1 m. In addition, Although not required, it is hoped that after such an additional raw material removal step, The wafer has a surface roughness (RMS) of less than about 1.0 nm over an area of 1 mm mm. It is more desirable that Ra is less than about 0.5 nm over an area of 1 mm. For the purpose of the present invention, the crystal The flatness and roughness of the circle after the rough polishing step can be measured as desired using any suitable measurement mechanism to confirm that the wafer has reached the target flatness and / or the target coarse chain. On the other hand, the measurement mechanism may It is used to measure and generate thickness profile data for all conventionally prepared wafers. Then all wafers are subjected to a material removal step based on this thickness profile data, which is done in practically the same way as previously disclosed. Figure 5 (a) and 5 (b) illustrate the improvement in flatness of discarded wafers according to this specific embodiment of the present invention. These flattened wafers can be "kissed" and polished as desired. These specific embodiments of the invention advantageously improve the yield of a given semiconductor wafer by providing a method for recovering wafers that do not meet the target thickness. Another specific embodiment for all wafers is further downgraded Or delete (read the note on the back ^ a ^ ^ ^ then fill in this education) ^ Private --------- Order. 9. -19- This paper size is applicable to China National Standards (CNS) M 格 (210X297 public epidemic a 5 18 A7 B7 printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Shellfish Consumer Cooperative) V. Invention Description (Π) The selection of flatness, such as increasing the cycle time of wafer preparation, is complicated. Disadvantages of material flow and increase of wafer manufacturing cost. The wafer planarization process of the present invention can also be prepared for a semiconductor wafer group with a strict TTV and / or STIR data distribution. That is, a group of at least about 10 substrates, preferably at least about 25 substrates, can be prepared with a wafer average TTV and / or STIR of no more than about, preferably about 0.7 / im, more Fortunately, it is about 0.5 m, and even more preferably about 0.3 m. Most preferably, it is about 0.2 m. In yet another embodiment of the present invention, the additional raw material removal step may be combined before the wafer's initialization / mechanical polishing or rough polishing. The hafnium removal step can be used to shape the wafer to compensate for any flatness reduction caused by the subsequent rough polishing step. For example, some rough polishing processes may give the wafer a convex shape. This additional raw material removal step can be used to repair this problem due to raw material removal, giving the wafer a concave profile before rough polishing. The subsequent rough grinding of the wafer then resulted in a wafer that was not protruding. Therefore, the combination of the raw material removal steps of the wafer before the rough polishing improves the wafer flatness of the wafer after the rough polishing compared to the flatness conventionally obtained after the rough polishing. Subsequent redundant polishing of the wafer usually does not reduce the flatness of the wafer. In each of the above embodiments, it may be desirable to selectively clean the wafer before and / or after raw material removal to remove materials such as solvent particles and metals that are attractive during the initial or intermediate steps and during raw material removal. Impurities such as MU and the like are deposited by the plasma. The wafer can be cleaned using any suitable cleaning procedure that does not substantially affect the thickness profile of the wafer. This (Please read the notes on the back before filling out this page) * * 1 ------- ^ Order —: ---------;-^-^ --- r.

A7 B7 4325 1 8 五、發明説明(ι〇 種清潔程序在此技藝中爲人所熟知,舉例來説包括,RCA 方法(;描述於 F. Shimura,Semiconductor Silicon Hryctaj Tec.ji.n〇l〇-£X (Academic Press 1989),pp. 1 89-191),或者一正 確的水漂洗。相類似地,在”吻觸”磨光之後,可能希望 選擇性地對晶圓實施適當的清潔程序,諸如以上與原料移 除步驟一起討論的傳統程序。 儘管本發明被描述於半導體晶圓的上下文中.,·它仍可應 用於一般對任何需要超平坦表面的半導體基體上,特別是 需要超平坦晶圓基體的磊晶層生長。另外,儘管以上討論 的具體實施例集中在平坦化晶圓以使TT v及/和s TIR數値 達到此處所討論希望的範圍,一個精於此技藝者仍可修正 Μ具體實施例來準備具有較大ττν及/*STiR數値的晶圓 ,如果應用在較低限制的平坦度規格的話,特別是大約小 於5&quot;m的TTV及/和STIR數値。 從以上的觀點來說,我們看到本發明的幾個固的和其他 有利的結果會得到。 由於以上的結構和製程可以在不離開本發明的範圍下做 各種改變’我們企圖使所有包含於以上説明或所附圖形者 將能被如說明而被演繹而不只爲有限的了解。 -21 - I-:.. I-,——,Q 1 訂-r 0Ί (請先閱讀背面之注意事項再填寫本頁) 雜濟部中决播準局員工消费合作社印A7 B7 4325 1 8 V. Description of the invention (ι0 cleaning procedures are well known in the art, including, for example, the RCA method (; described in F. Shimura, Semiconductor Silicon Hryctaj Tec.ji.n〇l〇 -£ X (Academic Press 1989), pp. 1 89-191), or a proper water rinse. Similarly, after a "kiss" polish, it may be desirable to selectively implement a proper cleaning procedure on the wafer Traditional procedures such as those discussed above with the material removal steps. Although the present invention is described in the context of a semiconductor wafer, it can still be applied to any semiconductor substrate that requires an ultra-flat surface, especially if it requires ultra-flat surfaces. Growth of an epitaxial layer on a flat wafer substrate. In addition, although the specific embodiments discussed above focus on planarizing the wafer so that the TT v and / or s TIR numbers reach the desired range discussed herein, one skilled in the art The specific embodiment of M can still be modified to prepare wafers with larger ττν and / * STiR numbers, if applied to lower-limit flatness specifications, especially TTV and / or STIR numbers less than about 5 &quot; m From the above point of view, we see that several solid and other advantageous results of the present invention will be obtained. Because the above structure and process can be changed in various ways without departing from the scope of the present invention, 'We try to make all The above description or the attached figures will be interpreted as described and not limited to understanding. -21-I-: .. I-, ——, Q 1 Order -r 0Ί (Please read the precautions on the back first (Fill in this page again.)

Claims (1)

4 3 2 5 1:&quot;'、 第871〇5〇ϋ專利中請案 中文申請專利範園修正本(89年7月) Α8 Β8 C8 D84 3 2 5 1: &quot; ', No. 871〇5〇 Patent application in Chinese (Amended in July, 1989) Α8 Β8 C8 D8 經濟部中央標隼局員工消費合作社印製 mi ι·—種用來平坦化一半導體晶圓的製程,該製程包括: 平坦化該晶圓以降低該晶圓的平坦度變動至—不超 過大約5 Ο μ m的數值,該平坦化之晶圓具有前表面和 後表面; 產生在該晶圓離散位置處的厚度輪廓資料,該晶圓 具有前表面和後表面; 決定在各個離散位置處要被移除的原料量以降低續 晶圓的平坦度變動’決定包括使用—運算厚度輪廊資 料和一目標厚度1\的演算法;以及 從該晶圓的前表面移除原料以降低晶圓的平坦度變 動至大約小於l.〇#m ’在各個離散位置處被移除的原 料量是基於該決定; 該平坦度變動對應於該晶圓的總厚度變動或局部總 指示讀數。 2. 根據申請專利範圍第1項的製程,其中厚度輪廊資料是 籍由』!1里晶圓在離散位置的電容來產生,而原料是藉著 以電漿蝕刻該晶圓的前表面來移除。 3. —種用來降低一已完成磨光之半導體晶圓超過—規格平 坦度變動數值的平坦度變動的製程,該製程包括: 產生在該晶圓離散位置處的厚度輪廓資料,該晶圓 具有前表面和後表面; 決定在各個離散位置處要被移除的原料量以降低該 晶圓的平坦度變動’該決定包括使用一運算厚度輪廓 資料和一目標厚度T t的演算法;以及 (請先閱讀背面之注意事項再填寫本頁)The Ministry of Economic Affairs Central Standards Bureau employee consumer cooperative prints mi ι-a process for flattening a semiconductor wafer, the process includes: flattening the wafer to reduce the wafer's flatness variation to-no more than about A value of 50 μm, the flattened wafer has a front surface and a rear surface; thickness profile data at discrete positions of the wafer are generated, and the wafer has a front surface and a rear surface; The amount of raw material removed to reduce the flatness variation of subsequent wafers' decision includes the use of-calculation of the thickness contour data and an algorithm for a target thickness of 1 \; and the removal of raw materials from the front surface of the wafer to reduce the wafer The flatness variation of the thickness to approximately less than 1.0 mm is based on the decision; the flatness variation corresponds to the total thickness variation of the wafer or a partial total indication reading. 2. According to the process of item 1 of the scope of patent application, the thickness profile information is generated by the capacitance of the wafer in discrete locations in ① !, and the raw material is obtained by etching the front surface of the wafer with plasma. Removed. 3. A process for reducing the flatness variation of a polished semiconductor wafer exceeding the specification flatness variation value, the process includes: generating thickness profile data at discrete positions of the wafer, the wafer Having a front surface and a rear surface; deciding the amount of raw material to be removed at each discrete location to reduce the flatness variation of the wafer; the decision includes an algorithm using a calculated thickness profile data and a target thickness T t; and (Please read the notes on the back before filling this page) AB:C;D 4 3 2 5 1 8 六、申請專利範圍 從該晶圓的前表面移除原料以降低晶圓的平坦度變 動至大約小於1 · 0 m,在各個離散位置處被移除的原 料量是基於該決定; 該平坦度變動對應於該晶圓的總厚度變動或局部總 ,示讀數。 4. 根據申請專利範園第3項的製程,其中厚度輪廓資料是 藉由測量晶圓在離散位置的電容來產生,而原料是藉著 以电衆I虫刻遠晶圓的前表面來移除》 5. 根據申請專利範園第1、2、3或4項的製程,其中該晶 圓在原料移除步驟之後具有大約小於〇_7Am的平坦度 變動。 6. 根據申請專利範圍第1、2、3或4項的製程,其中該晶 圓在原料移除步驟之後具有大約小於〇.5jtzm的平坦度 變動 7. 根據申請專利範園第1、2、3或4項的製程,,其中該晶 圓在原料移除步驟之後具有大約小於0.2仁m的平坦度 變動。 8. 根據申請專利範園第1、2、3或4項的製程,其中該晶 圓在原料移除步驟之後具有大約小於1〇)以m的平坦度 變動。 9. 根據申請專利範圍第1、2、3或4項的製程,其中該晶 圓是在原料移除步驟之後被磨光。 -2- 本紙張尺度逍用中國國家標準(CNS ) A4現格(210X297公釐) (請先閲讀背面之注意事項再填寫本頁)AB: C; D 4 3 2 5 1 8 VI. Patent application scope Remove raw materials from the front surface of the wafer to reduce the flatness of the wafer to less than about 1.0 m, which is removed at various discrete locations The amount of raw materials is based on the decision; the flatness variation corresponds to the total thickness variation or partial total of the wafer, and the reading is shown. 4. According to the process of the patent application Fanyuan No. 3, the thickness profile data is generated by measuring the capacitance of the wafer at discrete positions, and the raw material is moved by cutting the front surface of the wafer with the electric worm. Divide 5. According to the process of claim 1, 2, 3 or 4 of the patent application park, wherein the wafer has a flatness variation of less than 0-7 Am after the material removal step. 6. According to the process of claim 1, 2, 3 or 4 of the scope of patent application, wherein the wafer has a flatness variation of less than 0.5 jtzm after the raw material removal step. 7. According to the patent application park No. 1, 2, The process of 3 or 4, wherein the wafer has a flatness variation of less than about 0.2 μm after the raw material removal step. 8. The process according to item 1, 2, 3, or 4 of the patent application park, wherein the crystal circle has a flatness of about m after the raw material removal step. 9. The process according to claim 1, 2, 3, or 4, wherein the crystal circle is polished after the material removal step. -2- This paper is standard Chinese Standard (CNS) A4 (210X297 mm) (Please read the precautions on the back before filling this page) 經濟部中央標隼局員工消费合作社印裝Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs
TW87105021A 1997-04-03 1998-04-02 Flattening process for semiconductor wafers TW432518B (en)

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US6200908B1 (en) 1999-08-04 2001-03-13 Memc Electronic Materials, Inc. Process for reducing waviness in semiconductor wafers
US6189546B1 (en) * 1999-12-29 2001-02-20 Memc Electronic Materials, Inc. Polishing process for manufacturing dopant-striation-free polished silicon wafers
US6508953B1 (en) * 2000-10-19 2003-01-21 Ferro Corporation Slurry for chemical-mechanical polishing copper damascene structures
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US6613591B1 (en) * 2002-03-07 2003-09-02 Memc Electronic Materials, Inc. Method of estimating post-polishing waviness characteristics of a semiconductor wafer
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