TW405171B - Flattening process for epitaxial semiconductor wafers - Google Patents

Abstract

Process for the preparation of an epitaxial wafer having a total thickness variation and/or site total indicated reading of less than about 1.0 mu ms. The distance between the front and back surfaces of the epitaxial wafer at discrete positions on the front surface is measured to generate thickness profile data. Additional stock is removed from the front surface of the epitaxial wafer in a stock removal step to reduce the thickness of the epitaxial wafer to the target thickness, Tt, with the amount of stock being removed at each of said discrete positions being determined after taking into account the thickness profile data and Tt.

Description

^ 05171 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (Background of the Invention, the invention relates to-a process for flattening epitaxial semiconductor wafers. In particular, the present invention provides an improved overall epitaxial semiconductor wafer. The flatness and / or partial flatness of the spear is shown. The epitaxial semiconductor wafer includes a base wafer and / or multiple layers of substances deposited on the base wafer. It also provides a collection of epitaxial semiconductor wafers obtained by this process. Epitaxial is an important process in the semiconductor industry to achieve the electrical characteristics required for this semiconductor substance. For example, a lightly doped epitaxial layer grown on a highly doped 4 substrate makes a €] ^ 〇3 device Due to the low impedance of the substrate, it is idealized in terms of latch-up immunity. Other advantages such as precise control of the dopant concentration profile and auto-oxygen liberation can also be achieved. Epitaxial semiconductors used as the starting material for integrated circuit manufacturing The wafer must meet certain exact surface flatness requirements. Such epitaxial wafers must be developed by e.g. sub-beam development (electrcm beam_iith〇gra phic) or photolithographic processes to be polished to a particularly flat surface with printed circuits printed thereon. The wafer flatness at the focal point of the electron beam descriptor or optical printer is to the electron Beam lithography or photolithographic processes are important for consistent images. The flatness of the wafer surface directly affects the device line width capability, process level, yield and yield. Continuous reductions in device size and increasingly stringent device manufacturing specifications are forcing semiconductor manufacturing waste to prepare increasingly flat wafers. Epitaxial wafers can use overall flatness variation parameters (such as total thickness variation ( " TTV ") or general indication reading (" TIR ")) or use local position-4 * This paper size is applicable to China National Standard (CNS) Λ4 specification (2 丨 0X297mm) (Please read the precautions on the back first Fill out this page again} -11 A7 B7 405171 V. Description of the invention (2) Flat variation parameters (for example, the total position indication (" STIR ") or position focus plane deviation (" SFPD ")). A more detailed discussion of the wafer flatness characterization can be found in F. Shimura, Semiconductor Silicon Cjystal Techn0J_〇 ^ (Academic Press 1989), ppl91-195. Frequently used The TTV for measuring the overall flatness variation is the difference between the maximum and minimum thickness of the epitaxial wafer. The TTV in the wafer is an important indicator of wafer polishing quality. The STIR (Back Reference Central Focal Length), which is often used to measure local position flatness variations, is taken from the surface of a small area of a wafer parallel to the back surface of the wafer and intersecting the front surface at the local position with the front surface. The sum of the big positive and negative changes. A conventional polished epitaxial semiconductor wafer usually has an STIR (back reference center focal length) of more than about 0.7 // m = TTV and more than about 0.5 " m at any local position of 25 mm x 30 mm. However, the number of court samples depends on the implementation process conditions and is generally better known than 07 # 111 or 0.5 #. Unless otherwise noted, all 37111 figures discussed here are based on back-referenced central focal length reference surfaces. Through-hanging, the epitaxial layer is formed by, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE) 'in a highly ventilated state by thermal evaporation or low-pitched. Chemical vapor deposition is commonly used because it is the most flexible and cost-effective way to grow on semiconductor materials. Generally speaking, the chemical vapor phase contains volatile reactants @ SiH (: l3, 丨 2 or SiH4) and the introduction of a carrier gas (usually hydrogen)-an epitaxial reactor including semiconductor wafers eae㈣L Bu Er The long-term factors are the type of reactants' temperature, pressure, air flow rate == meter record Lai Cai. (Please read the precautions on the back before filling out this page) Order-Central Standards Bureau, Ministry of Economic Affairs, Employee Consumer Cooperatives, Printing Economy The Ministry of Standards and Standards Bureau, Beigong Consumer Cooperatives Co., Ltd., India 405171 V. Description of Inventions (3) Tens of thousands. The description of the epitaxial semiconductor wafer manufacturing process is disclosed in, for example, uspatat

Nos. 4,926,793 * 4,925,809. An epitaxial semiconductor wafer prepared according to a conventional epitaxial technique usually has an epitaxial layer thickness in the range of about 1 m to 100 m. The thicknesses of ττν and STIR of conventional epitaxial wafers are about 20% of the thickness of the epitaxial layer. As the thickness of the epitaxial layer increases, the TTV * STIR of the epitaxial wafer usually also increases. Traditional epitaxial techniques do not deposit epitaxial layers inconsistently. For example, an epitaxial wafer prepared in a wafer reactant usually exhibits a radial change in flatness. In addition, as the thickness of the epitaxial layer grows, it becomes more and more difficult to maintain a uniform and flat epitaxial wafer β. Therefore, it is possible to further improve the flatness of the epitaxial semiconductor wafer and / or surpass the traditional production yield method There is demand. In addition, a method that can reduce the overall process requirements and the disadvantages of the traditional polishing process without reducing the flatness of the wafer is also needed. The process of the present invention uses a correct sequence of additional material removal tools, preferably a plasma-assisted chemical etching removal tool step, to improve overall thickness variation and / or yield of epitaxial semiconductor wafers.

Mumola, U.S. Patent 5,419,803 discusses a method for planarizing microstructures. A microstructure or a sequence of microstructures on the surface of the substrate is covered by a -planarization layer, the substance completely covers the microstructure. Then — a plasma-assisted chemical etching tool is used to lower the coating, especially the oxide coating, to a desired minimum thickness measured with respect to a microstructure having a maximum height on the substrate surface.

Zarcmin et al., US Patent No. 5,254,830, discusses the use of a thickness measurement mechanism to generate the point-to-point thickness of a semiconductor wafer, especially absolute -6- This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm)-( (Please read the notes on the back before filling out this page)

* 1T A7 B7 4051 ^ 1 V. Description of the invention (4. Method of profile data for the thickness of a silicon film on a silicon substrate (soi). The profile material is processed to generate a dwell time for the entire measurement surface. Bitmap. This map is then used to control the movement of the topmost surface of the material removal tool to locally remove excess material from the surface to produce a SC) I wafer with a semiconductor layer of uniform thickness.

Pcmltney ’u.S_ Patent No. 5,563 ,,’ discusses the use of a metrology mechanism, particularly a mechanism configured using a Hartmann_shack sensor to measure the total thickness of crystal 15. The metrology mechanism is located on a planarization mechanism, such as a plasma-assisted chemical radon tool. The configuration on the planarization mechanism allows the metrology step and the material removal step to take place in a single workstation and eliminates the need for complicated mutual registration techniques for overlapping survey maps into the forming station and the like. The invention is drawn by the Central Bureau of Standards, the Ministry of Economic Affairs, the Beige Consumers Cooperatives. Therefore, among the several purposes of the present invention, it can be described as a process preparation for improving the flatness of epitaxial semiconductor wafers; Manufacturing process for epitaxial semiconductor wafers with a thickness variation of 1,0m; one = epitaxial semiconductor with wafers with local bit 2 indication readings less than about m; wafer preparation process; a sculpture by growing the epitaxial layer before growth ~ Improvement of the surface of the round substrate—the manufacturing process of the flatness of the epitaxial semiconductor wafer: a method to improve the yield of the semiconductor wafer at a low cost == a process—to flatten the surface of the epitaxial semiconductor Process of the selected area. Therefore, in short, the present invention is directed to a process for preparing epitaxial semiconductor wafers having a TTV and / or STiR of less than about ιααm.

This paper rule Longcai_Jiaxian (CNS A7 B7 V. Description of the invention I layer is grown on the front surface of a wafer substrate to form an interface between the front surface and the low surface of the epitaxial layer. On the wafer The distances between the top surface of the epitaxial layer and the back surface of the wafer substrate at the respective top positions of the upper surface are then measured to generate thickness profile data. It is best to use ADE 9700 capacitor probes. On the other hand, other ones using other reference planes Measurement methods (such as a measurement mechanism that can measure light or sound reflected from the upper surface of the epitaxial layer) can also be used to generate thickness profile data. The excess material is then removed from the upper surface of the epitaxial layer, preferably via a plasma Assisted chemical etching to reduce the total thickness of the epitaxial layer at each discrete point of the wafer to a target total thickness L. The amount of raw material that should be removed at each discrete position is determined after considering the thickness profile data and T The use of the excess material and raw material removal step results in wafer preparation being better in flatness ratio and / or yield than that achieved by current traditional processes. The present invention is also directed to a process in which the original The material removal step is performed based on the average point-to-point profile data, not the point-to-point thickness data of the prepared individual wafers. Although the profile data may be based on a single-point epitaxial profile of epitaxial semiconductor crystal SJ, the best It is measured and leveled

Central Ministry of Economic Standards and Industry Standards «* Cooperative Seal I: Generated from point-to-point profile data of at least two epitaxial wafers prepared from bulk wafers prepared under conditions similar to those of planarized wafers. This raw material removal step is then implemented, as discussed in the previous paragraph, based on the thickness sore cluster data on average more than the thickness profile data of the individual epitaxial wafers being flattened. ^ This month is also oriented to the “kind of process” where the material removal step is averaged using the point-to-point thickness profile data generated previously discussed and the paper dimensions A7 A7 405171 before the epitaxial layer grows. V. Description of the invention (6 (Please (Read the notes on the back before filling this page.) It is applied to the epitaxial wafer substrate. By using the thickness profile data to average, the raw materials are removed from the front surface of the wafer substrate to create a sculptured surface. It is actually a mirror image (or reverse profile) of a theoretical epitaxial wafer surface represented by the average of the thickness profile data. After the surface of the substrate is sculpted, the epitaxial layer is grown in a conventional manner. The invention also Guide a process in which raw materials are selectively removed from the upper surface of the epitaxial layer or the front surface of the wafer substrate. A selective region of the epitaxial wafer surface, especially a point-to-point region of the peripheral surface of the crown The thickness profile data is generated and used to control the material removal step according to the algorithm discussed previously. On the other hand, the material removal can be based on generating a representative Epitaxial wafers or sampled epitaxial wafers have average point-to-point thickness profile data. In addition, the perimeter (or other desired section) of the front surface of the wafer substrate can be sculpted before the epitaxial layer grows to compensate for the unwanted selected surface The total thickness variation of the area and / or the local position indication reading. The present invention is also directed to a wafer group comprising at least 10 epitaxial wafers, the wafers of which have an average total thickness variation of no more than about 1.0 mm and / Or the average position always indicates the reading, preferably about 0.7 " m, more preferably about 〇5 " m 'even better is about 0.3 # m' and most preferably about 〇2 " m The other goals and characteristics of the Indian Consumers' Cooperative Consumer Cooperative in the Central Bureau of Standards of the Ministry of Economics are partly obvious, and part of them will be pointed out here. Brief description of the figure Figure 1 is a cross section of an epitaxial semiconductor wafer Figure 2. Figure 2 is a probability map of the local flatness distribution of a group of epitaxial wafers that have undergone plasma-assisted chemical etching after the epitaxial layer has been grown. -9 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X 297mm) A7 B7-~~~~~ 4J〇L5Lm 5. Description of the invention (7) 2 The reference characteristics of the application indicate the corresponding parts of many points in the drawing. For details of the examples, please read the words first Note on the back side, please fill in this hundred. According to the present invention, it has been found that the overall and / or local bit f flatness of an epitaxial semiconductor wafer and a given production yield can be obtained by combining a semiconductor = circle combination and Correctly arrange an additional material removal step, preferably-electrical, auxiliary chemical etching step, and traditional planarization processes to improve. The flatness of the epitaxial wafer depends partly on the flatness of the wafer substrate and the epitaxial layer. Depending on the flatness. Improve the flatness of the wafer substrate or the flatness of the epitaxial layer, both of which can improve the flatness of the epitaxial wafer. Therefore, the material removal step is preferably inserted into an epitaxial process, after the conventional wafer substrate is prepared, and before or after the epitaxial layer is grown on the wafer substrate. Printed by the Consumer Cooperative of the Central Government Bureau of the Ministry of Economic Affairs During the epitaxial growth, the precipitation rate of silicon in each part of the wafer substrate is an equation that is sensitive to the temperature profile and the gas flow pattern in the reactants in various variables. To produce the most consistent epitaxial layers, attention must be paid to these airflow and temperature adjustments. In fact, the $ 's consistency is not achieved, and the thickness of the epitaxial layer will change on the surface of the circle. In order to equalize changes in airflow and temperature, the substrate and wafer are rotated frequently during the precipitation. In a single wafer reactant, the wafer is usually rotated about its center, producing a thickness variation close to the radiation symmetry on the epitaxial layer. In a group of reactants, the axis of rotation is usually not the same as the axis of symmetry of the wafer, so the epitaxial thickness variation on the obtained wafer is not symmetrical. In another case, thickness variation is a characteristic of reactant type and operating conditions and can be accurately predicted. This improved process allows the preparation of an epitaxial wafer with lower total thickness variations (" ττν ") and / or localized locations than those available through current conventional processes. ______ _ 10- This paper size applies to China Standard (CNS) Λ4 specification (210X297 Gongchu) ~-Printed by A Bei Gong Consumer Cooperative of Central Standards Bureau of the Ministry of Economic Affairs A7 — 4,0% ^-____ 5. Description of the invention (8) Indication reading (" STIR ") . In addition, inserting an additional material removal step in a conventional epitaxial process can increase the yield for a given production and relax the flatness requirements of the wafer substrate on which the epitaxial layer is grown. It also provides greater flexibility in the selection of process conditions for epitaxial layer growth. The process of the present invention uses a semiconductor wafer sliced from a single crystal metal block as a starting material. Silicon is a better material for this wafer, because its conductivity and resistivity are not critical. The wafer may have any diameter and target thickness suitable for half-conductor applications. For example, the diameter may be 4 to 8 inches (100 to 200 nm) or more, and the thickness may be 475 to 725 jum or more. 'Thickness usually increases as the diameter increases. The wafer may also have any crystalline orientation. Referring now to FIG. 1, in a first embodiment, the wafer substrate 2 is flattened to form an ultra-flat wafer. The wafer is preferred. It has a TTV of less than 1 # m, more preferably has a TTV of less than about 0.7 ^ ^ ^ TTV, even more preferably has a TTV of less than about 0.5 // m, even more preferably has a TTV of less than about 〇2 " m TT V 'and the most ideal is to have a τ d v less than about 〇 1 " m. On the other hand or more, the wafer wafer preferably has a STIR less than 1 " It is better to have a STIR less than about 0.7 # m, still more preferably to have a STIR less than about 0.5 " m, even more preferably to have a STIR less than about 0.2 " m and most preferably it is less than about 0.2 STIR of approximately 0.1 m. Preparation of wafers that meet this flatness specification can be used, for example, PACE-based technologies disclosed in US Patent Nos. 4,668,366, 5,254,830, 5,291,415, 5,375,064, 5,376,224, and 5,491,571. The precise wafer forming equipment using this technology has been developed by IPEC / Precision (Bethel, -11 · This paper size applies to China National Standard (CNS) A4 specification (2 丨 OX 297 mm) (Please read the precautions on the back first Refill this page) Order-__405171 37 V. Description of the invention (9 ) One by one: Two ^ C〇nnectcut) Commercialized application under the trademark of Pws_200.-Please read the precautions on the back before filling in this page) Because the material removal step in the specific embodiment of the present invention is from this The epitaxial layer of the epitaxial layer removes the material, which usually results in a reduction in the thickness uniformity of the epitaxial layer. When the extra raw material removal step flattens the epitaxial wafer prepared from a wafer substrate having a large ττν and / or STIR number It may also reduce the thickness of the epitaxial layer. If ττν and / or 87111 of the substrate is too large, the point corresponding to the peak ridge position of the substrate will be lower than an acceptable minimum 可接受. Therefore, the wafer substrate's For TTV and / or STIR, it is better to use less than the consistent variation of the epitaxial layer to avoid reducing the thickness of the epitaxial layer below the acceptable minimum. Generally, the wafer substrate on which the epitaxial layer is grown should preferably have a thickness of 1 mm. Thickness (rms) of less than about 10 nm over an area of X 1 mm. More preferably, less than about 0.5 nm over an area of 1 mm X 1 mm. Even more preferably less than about 0 over an area of j mm XI mm. .25 ηπ1. However, plasma wafer thinning Process often leaves a large amount of surface roughness of the wafer surface of the substrate (rms), such as to force electron microscope (At〇mic F〇ree Microscope) (AFM) is generally measured. Therefore, it is best that the plasma substrate has a reduced roughness on the surface of the wafer substrate of the consumer cooperative of the Ministry of Economic Affairs, Central Bureau of Standards and Consumers, which is lower than this roughness. This can be easily done with a light polishing process, kiss polish. The algorithm to determine the removal amount is as follows: (1) Determine the peak (" P ") of the surface of the plasma and the valley (" v. Roughness, r (p_v); (2) use a complete solution Pulp (such as dilute G1 anzox) and design a polishing process to remove about 3r (pv) to 4r (pv); and (3) traditional RCA type cleaning. Remove this -12- This paper size applies Chinese national standards ( CNS) Λ4 specification (2 丨 0X 297 mm) A7 --4M41U __ ^ 5. Description of the invention (10) A small amount of silicon usually does not damage the flatness of the wafer. Considering the need to control TTV and / or STIR, the crystal The circular substrate 2 includes any substance that mechanically supports other layers and can process the structure without constituting an epitaxial source of impurities. Such substances include 'such as-basic semiconductor substances or a compound semiconducting material (or for non-epitaxial films) Shen Dian, substances such as polycrystalline shatters, glass substances such as quartz 'ceramic materials such as alumina, aluminum nitride, or silicon carbide). Shatter is a more recommended substance for wafer substrates 2 due to its conductive type and Resistivity is not a critical decision. Wafer substrate 2 with front surface 3 and back surface 4 Is treated in such a way that an epitaxial layer 5 is formed on the front surface 3, wherein an interface is formed between the front surface 3 and the epitaxial layer ㈣ lower surface 6. The thickness of the epitaxial layer 5 will depend on the type of the precipitated substance, the epitaxial reactant conditions , And the characteristics of the required device. These factors can be processed to produce the epitaxial layer of the desired thickness. Preferably, the epitaxial layer 5 is composed of silicon. However, the substance of the epitaxial layer 5 can be derived from other substances such as silicon-germanium alloys. For a layer of silicon, the thickness traditionally required will be between about 1.0 // 111 and 100 " 111, and usually the thickness is between about 2.0 "! ^ And 25.0 am. In addition, Although the epitaxial layer is preferably formed by chemical vapor deposition, other methods may be used to deposit the epitaxial layer 5 on the wafer base 2. After the epitaxial layer 5 is grown, the point-to-point thickness profile information of the epitaxial semiconductor wafer 1 is used. The equations generated and corresponding to the positions on the surface 7 above the epitaxial layer 5 generate enough discrete number of position data to ensure the full surface coverage of the epitaxial wafer! Therefore, the number of discrete positions, the most It is at least 2, more preferably at least 10, still more preferably at least about 丨 〇〇, and even more preferably at least about -13. The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm) (Please read the precautions on the back before filling out this page.) The Central Government Standards Bureau of the Ministry of Economic Affairs, China

* 1T111 --- I i I-I — I--1— 1. II .II II. A7 B7 5. Printed by the Shellfish Consumer Cooperative of the Order and Standards Bureau of the Ministry of Invention and Economy, 1,000, which is best in some applications It is at least about 5000. The thickness measurement tool used to generate this information can be a capacitive, optical interference, FTIR, or mechanical (such as a macrometer) thickness measurement tool. Preferably, however, it is determined by a capacitor thickness measurement tool having a resolution of at least about 0.5 μm, and more preferably at least about 0 ## 111. A capacitor thickness measurement tool with a resolution of about 〇1 to 〇2 has been commercially used by ADE cropara (R) (NeWton, MA) under the trademark ADE 7200. However, it is best to use the ADE 9700 capacitor thickness measurement tool. In operation, the use of silicon wafers in the parallel-plate capacitors of these tools results in a change in capacitance. The capacitance of the capacitor may be related to the thickness of the wafer & its effective dielectric constant. The rest of the discussion focuses on the use of capacitance measurement tools for illustrative purposes. A person skilled in the art can modify the specific embodiment disclosed herein to replace the capacitance measurement tool with another measurement mechanism that is well known in the art and measures flatness based on a different reference plane from the capacitance measurement tool. . It should be noted that the epitaxial wafer HHTvwBnR can be calculated using algorithms based on the thick f-profile data and the target thickness of the wafer. For example, the amount to be removed can be determined by The ^ contour data at the position is determined by subtracting the difference between the target thickness and the number of millimeters, which must be two =: two sides, 6 =: _ to reach the original amount of the target thickness Tt and therefore take the miniaturized TTV and / Or STIR. = If desired, the thickness of the wafer substrate τ "... can be measured for inclusion in the algorithm. For example, the algorithm can be modified to provide a target thickness so that the difference between" ... Less than .--- „--------- (Please read the precautions on the back before filling this page)

--- Order -------, _ 〆 -I— j I I I I —l · — m Γ I.. 1 m i I --I I I · -14-

1 I. I A7 B7 V. Description of the invention (l2 In the = algorithm, such elements can ensure that the thickness of the epitaxial layer is not reduced below a minimum acceptable number at various discrete points.

I-After the mass of the material to be removed from each of the departure locations on the upper surface 7 of the outer k layer 5 is determined, the material removal information is processed and converted into a corresponding map of the residence time versus location for use in the raw material transfer. The removal step controls the material removal tool. This raw material removal can be performed using any tool capable of locally and accurately removing raw materials from a small area on the upper surface 7 of the epitaxial layer 5. The tool can be, for example, a chemical / mechanical polishing tool with a micro-polish. However, I'll take the aforementioned type of pace removal tool. After the raw material removal step, the upper surface 7 of the epitaxial layer 5 has a TTV of less than about 1.0 am, and preferably has a TTV of less than about 0 &quot; ττν, even more preferably, has less than about 0.2 m & TTV, and most ideally has less than about 0 m &quot; m MTV. On the other hand, or even further, 'the upper surface 7 of the epitaxial layer 5 has an STIR of less than about 1.0 μm & STIR, preferably has an STIR of less than about 0.7 m, and even more preferably has an impact of less than about 0 claws. It is even better to have less than about 0.3 &quot;, and the most ideal is to have less than about 0.1 Mm of STIR printed by the cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The final ττν and / or ^^ 値 of the wafer is achieved by accurately mapping the thickness of the epitaxial wafer 1 and using the map to accurately thin the wafer in the raw material transfer step. During the raw material removal step, it is preferred that at least l &quot; m of raw material be removed from the wafer, more preferably at least 2.0 / m, and even more preferably at least about 40m of raw material in the raw material. The wafer is removed from the wafer in a removing step. Before and / or after the raw material is removed, the epitaxial wafer can be cleaned according to the intention. The 15 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (2Ι0 × 297 mm) A7 405171 V. Description of the invention (13) · Remove Impurities such as slurry particles and metals introduced during the initial planarization step, and sulfur deposited on the wafer surface by the plasma during raw material transfer. The epitaxial wafer 1 may be cleaned using any cleaning procedure suitable without substantially affecting the thickness profile of the wafer. This cleaning procedure is well known in the art, including, for example! ^ Eight methods (described in F. shimura, ^^ nductor-mi con_Crystal T. rhnnln ^ y (Academic Press 1 989), pp 189_191), or a correct water rinse. After the raw material is removed, the upper surface 7 of the epitaxial layer 5 may be polished according to the meaning and preferably a "kiss" to reduce the surface roughness (rms) after the raw material is removed. The procedure is actually the same as the previous one, although the polishing time may be further lengthened to reduce non-mirror reflected light (blurring) and enhance the specularity of the above 7. An unpolished wafer includes a high degree on its surface. And low-frequency roughness. High-frequency roughness causes high light scattering on the surface due to blurring. 菘 L kiss &quot; polishing minimizes high- and low-frequency roughness and reduces blurring. Preferably, the surface roughness is reduced to In the area of 25 &quot; W is less than about Η. Generally, about ^ to 300nometers of silicon are removed during this polishing step. After polishing, the epitaxial wafer is selectively implemented. Appropriate cleaning procedures, such as those discussed above with the material removal steps. &Amp; Figure 2 illustrates the improvement in flatness according to a specific embodiment of the present invention. In another-specific embodiment of the present invention, The raw material removal step It is implemented based on the average of the point-to-point thickness profile data, not the prepared point-to-point thickness profile data ^. It is found that it is substantially equivalent to the use (please read the notes on the back before filling this page) Order-Economy Printed by the Central Bureau of Standards of the People ’s Republic of China for the production of printed materials. A7 B7 The epitaxial semiconductor wafer produced by the Central Bureau of Standards of the Ministry of Economic Affairs ’Consumer Cooperative ’s printed substrates with substantially similar characteristics will be subject to change under similar conditions. This type is particularly reproducible in a single-see: circle = reproducible point-to-point thick spot called a circle reactant. Therefore, a representative epitaxial iJt θ ^. ^ A is called a circle or is prepared under the same conditions The outer == selected point-to-point thickness of the perimeter data can be generated to create a point profile data average. For those epitaxial reactants that produce highly reproducible points 2 TIR type <epitaxial crystal 111, the point pair ·, ·: The degree of corridor data can be averagely based on data obtained from a single-r surface wafer in the reactant, rather than from two or more epitaxial crystals = The average number of known data. Therefore, the number of epitaxial wafers measured to obtain the average point-to-point thickness profile data is at least about 10, and preferably at least about 25. To be = divided by the desired TTV and / The physical mass of the 5iUTlR number can be calculated using an operator-like algorithm that is actually calculated from the target thickness and the thickness of the discrete bits at each discrete bit I, as discussed previously. M This information is processed and converted into dwell time versus position. The corresponding map is used to control the raw material removal tool in the raw material removal step. An epitaxial wafer prepared from the same epitaxial reactant, or the same epitaxial reactant that actually resembles a DTV and / or STIR type 'Once thickness profile data After the average has been determined, it can be processed without using a measurement mechanism to generate individual wafer point-to-point thickness profile data. "Referring again to FIG. 1 'In another embodiment, before the epitaxial layer 5 grows' raw material removal The steps are implemented on the front surface 3 of the wafer base 2 using the point-to-point thickness profile data generated as discussed above. The raw material is root (Please read the notes on the back before filling this page}

1T »— ^ n —ij. .. I n I-1 ______-17- Paper (CNS) grid (21GX297) Chu A7 405171 V. Description of the invention (15) Based on the point-to-point thickness profile data averaged and self-crystallized The front surface 3 of the circular substrate 2 is removed to sculpt the front surface 3 of the wafer substrate 2, in which the sculptured surface is actually a mirror image of the surface of the wafer epitaxial layer averaged according to the point-to-point thickness profile data. The surface of the sculpture actually complements ττν and / or stir, which is commonly found in epitaxial layers grown according to this embodiment of the present invention. After the front surface 3 of the wafer substrate 2 has been sculpted, it is preferably polished, kissed, and the epitaxial layer 5 is grown in a conventional manner. Finishing of the upper surface of the epitaxial layer is generally not required. However, if desired, the upper surface 7 of the epitaxial layer 5 may be implemented-an additional substance removal step to further reduce the remaining TTV and / or STIR of the wafer. If this additional substance removal step is carried out,-once all the substance removal steps have been completed, the epitaxial layer top surface 7 is preferably subjected to a "kiss touch" finish as previously discussed. On the other hand, the thickness of the wafer substrate 2 is generated and the raw material is removed from the front surface 3 to prepare an ultra-flat surface instead of just a sculptured surface. After the front surface 3 of the wafer substrate 2 is flattened, it is preferably "kissed", polished, and the epitaxial layer 5 is grown in a conventional manner. Referring again to FIG. 1, in another embodiment of the present invention, the crown of an outer conductor is selectively removed. During the epitaxial growth, the Hit on the printed edge of the Central Consumer Bureau of the Ministry of Economic Affairs of the wafer substrate printed on the edge is often 0. The edge near the edge has a faster growth than the other areas of the substrate and is created on the outer periphery of the front surface of the wafer substrate. Out of the crown 'or-ask (area. The crown is often considered to be the largest TTV and / or STIR of the epitaxial wafer. This crown can be selectively moved according to the specific embodiment of the invention discussed above Exactly, the thickness of the point-to-point thickness data can be on the upper surface of epitaxial layer 5 ___ -18- The paper size is suitable for financial affairs (CN7) A4 specifications (2Ι () χ ^^ ~ ρ A7 405171 V. Invention description (16) The periphery (or other selected area) of 7 is generated and used to control the material removal tool according to the previously discussed algorithm and the obtained dwell time versus position map. On the other hand, this material removal can be It is based on averaging the perimeter & point-to-point thickness profile generated from the preparation of epitaxial wafers under conditions similar to those of unsculpted wafers. On the other hand, the periphery of the front surface 2 can be The epitaxial layer was sculpted before growing. This sculpture caused the sculptured surface 3 to be convex on the periphery of the wafer substrate. The epitaxial layer 5 was grown on the front surface 3 of the wafer substrate 1, which caused the return Due to the elimination or reduction of the τΤν and / or STIR of the side crown. Although these other specific examples illustrate the selective raw material removal of the side crown, such selective material removal can be performed on the epitaxial layer or the wafer substrate. This can be achieved at any discrete location on the surface. In order to reduce cycle time or other achievable processing benefits, processing of epitaxial layers or wafer substrates smaller than the entire surface is desired. In each of the above specific embodiments, it may be desirable to move the material Selectively clean the corresponding epitaxial wafer and / or wafer substrate 2 before and / or after to remove particles such as slurry particles and metals introduced in the initial or intermediate steps and by plasma during raw material removal Impurities such as sulfur deposited on the wafer surface, etc. The epitaxial wafer 1 and the wafer base 2 may use any appropriate cleaning procedure that does not substantially affect the BEI circle thickness profile. This cleaning procedure is well known in the art and includes, for example, the RCA method (described in Shimura, Semiconductor Silicon Crystal T-hnolnpy (Academu Press 1 989), ρ · 189 · 19ι) or ' Correct water rinsing. Similarly, after "kissing" polishing, you may want to selectively implement appropriate cleaning procedures on the wafer, such as the above and raw material removal steps. -19- This paper size applies Chinese national standards (CNS) A4 specification (210X 297 mm) A7 405171 V. Description of the invention (17) The traditional procedure discussed at the beginning. Each specific embodiment of the present invention has a lower TTV and / or STIR offers special advantages in the preparation of ultra-flat epitaxial wafers. The process of the present invention also provides special advantages in relaxing the TTV and / or 8-foot-1 requirements of the wafer substrate where the epitaxial layer is grown. Dagger offers special advantages over traditional planarization, buffing and epitaxial layer growth steps. These advantages appear in the flexibility of selecting the initial flattening and polishing variables. This combination of material removal steps makes the selection of data possible. . On the other hand, for flatness specifications as low as 0.7 &quot; m TTV and 0.5 &quot; m STIR, a yield close to 100% is possible. Therefore, this specific embodiment eliminates the need for flatness specifications that only require the flatness picking of TTV and / or STIR wafers that are larger than 0 m. Traditional wafer preparation processes require such flatness picking. In addition, the wafer planarization process of the present invention is capable of forming epitaxial semiconductors with a strict distribution of ττν and / and STIR numbers. This means that at least about a set of substrates, preferably at least about 25 substrates that can be prepared with a wafer average tintin of not more than about 1.0 and / and STIR 'preferably about 0 ", more preferably about 0", and even more preferably about 0.3 &quot; m' The most ideal is about 〇2㈣. In addition, such a wafer stack can be prepared such that the minimum thickness of the epitaxial layer does not exceed 2.0 y ij in all locations of the epitaxial layer]. Although the specific embodiment discussed above focuses on the planarization of a single-layer epitaxial wafer, a person skilled in this art can still modify the specific embodiment to apply to -20- This paper standard applies to the Chinese national standard (CMS> A4 Specifications (2 丨 〇X 297) Please read the notes on the back before filling out this page) Order printed by the Central Standards Bureau of the Ministry of Economic Affairs, Zhengong Consumer Cooperative I I- I. I · 405171 V. Description of the invention (18) On multi-layer epitaxial wafers. Similarly, although the specific embodiments discussed above focus on planarizing epitaxial wafers to bring the TTV and / or STIR numbers to the desired range discussed herein, a person skilled in the art can still modify This specific embodiment prepares an epitaxial wafer with a larger TTV and / or STIR number, if it is applied to a lower limit flatness specification, especially a TTV and / or STIR number less than about 5 # m. From From the above point of view, 'we see that several objects of the present invention and other advantageous results will be obtained. Because the above structure and process can be changed in various ways without departing from the scope of the present invention', we try to make all The above description or the attached figures will be interpreted as explained and not only for a limited understanding. (Please read the notes on the back before filling this page) 21-This paper size applies to China National Standard (CNS) A4 (2 丨 OX 297 mm)

Claims (1)

~ 405171 VI. Patent application Fanyuan θ is used for the preparation of epitaxial wafers with a flatness variation of less than 1.0 &quot; m, the epitaxial wafer includes-a wafer substrate with a front surface and a back surface and-has an upper surface An epitaxial layer is formed on the surface and the lower surface. The process includes: growing an epitaxial layer on the surface of the G-round substrate to form the epitaxial wafer; the wafer substrate has a flatness variation of less than about 10 A m; An interface is formed between the front surface of the circular substrate and the lower surface of the epitaxial layer; thickness profile data at discrete locations of the epitaxial wafer are generated, and the production of the thickness profile data includes measuring the upper surface of the wafer substrate and the upper surface of the epitaxial layer above. The distance at each discrete location on the surface; determines the amount of raw material to be removed at each discrete location to reduce the flatness variation of the epitaxial wafer. The decision includes calculations using a calculated thickness profile and a target thickness Tt Method; and removing the raw material from the upper surface of the epitaxial layer to reduce the flatness variation of the wafer to not more than large, at each discrete position = the amount of raw material is based on Decision; total thickness variation of the flatness of the wafer corresponding to variation thereof refers to not reading or topical. . g, k, quasi bureau member i Consumer Co., Ltd. printed 2 ·, according to the process of applying for patents on page &quot;, where the thickness profile asset is measured by measuring the capacitance of the wafer at discrete locations, and the raw materials are produced by In order to avoid slurry etching, the front surface of the epitaxial layer of the wafer is removed. 3. The process according to item (2) of the patent application, wherein after the material removal step, the epitaxial wafer has a flatness of less than about 0 7 &quot; m. -22- This paper is of the right size (献) 2 297 rounding. Ⅵ. The scope of patent application Today · According to item liu of the scope of patent application, there is a flatness variation of less than O.hm. Among them ^ round substrate with ^ Gen ^ please specialize in the production of item ⑷ ^ in the original, π ^ gift 0 &quot; m of the raw material is removed from the epitaxial layer and the epitaxial wafer is polished after the raw material removal step . Except 6 ·: = a process for preparing an epitaxial printing circle with a variation of flatness less than U ..., the process includes:, generating a thickness profile of at least-the first epitaxial crystal solid; the first: the wafer includes a front surface And the back surface of the first wafer substrate and-and 2 surface and lower surface epitaxial layers,-the front surface of the first wafer substrate and the lower surface of the epitaxial layer-the interface; the production of thickness profile data, the burden Measure the distance between the upper surface of the first epitaxial layer and the rear surface of the wafer substrate at discrete positions on the upper surface; generate the thickness profile data from at least the first epitaxial wafer to prepare the thickness profile data average; An epitaxial layer is grown on the front surface of the second wafer substrate to form a first epitaxial wafer. The wafer substrate includes a first round substrate Sa having a front surface and a rear surface, and an epitaxial layer having an upper surface and a lower surface. The front surface of the second wafer substrate and the lower surface of the epitaxial layer form an interface; determining the amount of raw materials to be removed at various discrete locations to reduce the flatness variation of the second epitaxial wafer, the decision includes using— Calculated thickness: average profile data and a target thickness &amp;algorithm; and _ remove raw materials from the upper surface of the epitaxial layer of the core two epitaxial wafer to reduce the flatness variation of the second epitaxial wafer to no more than about 〖 Claw, the amount of raw material removed at various discrete positions in the scope of the patent application is based on the decision. • 23- This paper χΛSuitable Finance Standard (CNS) Α4ΜΛ (2Ϊ〇 ^ 97 ^^) 405171 The change in degree corresponds to the change in the total thickness of the wafer or a local reference of 7 · ?; "Patent Fan Yuan No. 1" process, in which the thickness profile data is precisely measured from the capacitance of the wafer at discrete locations. : It is by engraving the front surface of the epitaxial layer of the second wafer electrically: The process of the range item 6 or 7 in which the raw material removal step = the moving epitaxial wafer has a flatness less than about G ~ m 9 According to the process of claim 6 or 7 of the patent application, during the "material transfer" step, there is &gt; about! 〇 &quot; m of raw material is removed from the epitaxial layer, and the second epitaxial wafer is After the raw material removal step, it is polished. quot; The process of preparing epitaxial wafers with a flatness variation of m, the process includes: printing by the Central Standards Bureau of the Ministry of Economic Affairs of the Shelley Consumer Cooperative to produce thickness profile information for at least one first epitaxial wafer; the first epitaxial wafer includes A first wafer substrate having a front surface and a rear surface and an epitaxial layer having an upper surface and a lower surface, the front surface of the first wafer substrate and the lower surface of the first epitaxial layer forming an interface; the generation of thickness profile data Including measuring the distance between the upper surface of the first epitaxial layer and the rear surface of the first wafer substrate at discrete positions on the upper surface; preparing the thickness profile data average from the thickness profile data generated from at least the first epitaxial wafer;离散 To be removed at discrete locations on the front surface of a first wafer substrate. -24 · I Paper Standard (CNS) A4 · (21 ^ iT A8 Βδ C8 D8 405171 The amount of raw materials in the scope of patent application, the second wafer substrate Hehong η I has a front surface and a rear surface, and must include an algorithm that uses a thickness profile data ^ ^; Ziqian Junyi and -target thickness Tt from the second epitaxial crystal The front surface removes the raw material to create a sculpture surface, which is moved at each position. The amount of raw material is based on this decision; and an epitaxial layer is grown on the front surface of the second wafer substrate to form a second epitaxial crystal. circle. u. According to the manufacturing process of the patent, the thickness profile data of μ is generated by measuring the capacitance of at least the first wafer at discrete positions, and the raw material is electrically etched the epitaxial layer of the second wafer. To remove the front surface. 12. A process for selectively removing an epitaxial wafer crown, the epitaxial wafer including a wafer substrate having a front surface and a rear surface and an epitaxial layer having an upper surface and a lower surface, the process The method includes: growing an epitaxial layer on the front surface of the wafer substrate to form the epitaxial wafer, the wafer substrate has a flatness variation of less than 丨 .〇 # m, and the front surface of the wafer substrate and the epitaxial layer Lower surface formation-interface; generating the thickness profile data of the epitaxial wafer area where the crown is located, the generation of the thickness profile data includes measuring the distance between the back surface of the epitaxial wafer substrate and the upper surface of the epitaxial layer at discrete positions on the upper surface ; Determine the amount of raw material to be removed at various discrete locations to eliminate the dream crown, the decision includes the use of an algorithm to calculate the thickness profile data and the target thick household Tt; give the epitaxial layer from the epitaxial wafer Remove the raw material on the upper surface to actually eliminate 25 paper sizes. Applicable to China National Standard (CNS) A4 specifications (210X297 mm) I .11 I (Please wash and read the precautions on the back before filling in Page) Ministry of Economic Affairs Bureau of Standards staff printed consumer cooperatives ABCD, Central Standards Bureau, Ministry of Economic Affairs, Employees' Cooperative Co-operative Printing 405171 VI. Scope of patent application = edge crown, the amount of material to be charged at each scattered w is based on the process of item 13 = Γ :: range, where thickness The profile data is ": Γ two circles of capacitors are generated at discrete positions, and the raw material is refined by« shoe engraving the epitaxial layer of the epitaxial wafer. According to the system of the patent application No. 12 or 13: After the raw material removal step, it is polished. Bu I India 5. An epitaxial semiconductor wafer group, including at least! ◦Epitaxial semiconductor wafers with an average wafer flatness variation that does not exceed approximately 1.0 y.m. 16. According to the epitaxial semiconductor wafer group under the scope of application for patent No. 15, the thickness of the epitaxial layer of each epitaxial semiconductor wafer is greater than 2. 0 // m at all positions of the epitaxial layer. 17. According to the wafer group of patent application No. 丨 5 or 丨 6, the group contains at least 25 wafers. 26 This paper size applies to China National Standard (CNS &gt; A4 size (210X297 mm)