JP2000033563A - Control method for polishing margin and manufacture of wafer by use of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a very effective control method for a polishing margin when a wafer such as SOI wafer of an SOI layer having a diffusion layer which requires the control of a minute polishing margin is polished. SOLUTION: In a control method of polishing margin when a wafer is polished, at least one SOI wafer is polished in accordance with the same conditions as the other wafer to be polished, and polishing margin is calculated from a film thickness of an SOI layer before and after polishing the SOI wafer to control the polishing margin. In a control method of polishing margin when a plurality of wafers are polished at the same time, at least one SOI wafer is polished together with the other wafer to be polished at the same time, and polishing margin is calculated from a film thickness of SOI layer before and after polishing SOI wafer to control the polishing margin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for managing a polishing allowance when polishing a wafer and a method for manufacturing a wafer using the method, and more particularly, to manufacturing an SOI wafer having a diffusion layer in an SOI layer. The present invention relates to a method of managing a polishing allowance in a case.

[0002]

2. Description of the Related Art In manufacturing a semiconductor wafer,
When polishing a wafer, it may be necessary to control a minute polishing allowance. For example, when manufacturing an SOI wafer having a buried diffusion layer at the bottom of the SOI layer,
It is necessary to control the polishing allowance with high precision.

For example, in order to manufacture an SOI wafer having a high-concentration buried diffusion layer of Sb or the like at the bottom of the SOI layer, usually, as described in Japanese Patent Laid-Open No. 5-136108, A technique is used in which a bond wafer in which impurities are diffused and a base wafer having an oxide film formed on the surface are bonded.

However, when impurities are diffused on the surface at a high concentration, the surface is roughened. If the surface is bonded as it is, voids may be generated at the bonding interface or the bonding strength may be reduced. I understood.

Therefore, it has been proposed to bond the bond wafer after slightly polishing the high-concentration impurity diffusion surface (removal amount: 0.1 μm) before bonding. Such an extremely small polishing allowance is performed under the polishing conditions of the finish polishing in the production of a normal mirror-surface wafer (Japanese Patent Laid-Open No. Hei 9-11612).
No. 5).

However, the diffusion depth of the high-concentration diffusion layer is usually at most about 3 μm, and the impurity concentration becomes higher near the surface to be removed by polishing. In addition, there is a large difference in the characteristics of the manufactured SOI wafer. Therefore, it is necessary to accurately control the polishing allowance of the high concentration diffusion layer.

[0007] Conventionally, when it is not necessary to particularly precisely control the polishing allowance, when managing the polishing allowance, polishing (primary polishing, secondary polishing: coarse polishing) having a relatively large polishing allowance is required. As a method of managing the polishing allowance, measure the thickness of the wafer before and after polishing, determine the polishing rate by reading the difference,
A method of setting a polishing time so as to provide a necessary allowance has been adopted.

At this time, as a method of measuring the thickness of the wafer, a contact-type measuring instrument such as a dial gauge is mainly used, and when the wafer is polished by fixing the wafer to a polishing plate with wax, a polishing plate is used. The measurement was performed with the wafer adhered.On the other hand, a wafer holding hole called a template was provided on the polishing plate, and the wafer was inserted therein and polished.In the case of so-called wax-free polishing, the wafer was taken out of the template and measured. . In addition, when a non-contact capacitance type thickness measuring instrument having relatively high measurement accuracy is used, a step of cleaning and drying the wafer after polishing is indispensable in any of the above polishing methods.

On the other hand, in the case of the finish polishing with a small polishing allowance, the same method as described above cannot accurately grasp the polishing allowance because the polishing allowance is small. It is said that the purpose is to improve the surface roughness remaining after polishing and has little effect on the finished thickness of the wafer after polishing, so that it is not necessary to control an accurate polishing allowance.

[0010]

However, in the case of polishing a high concentration diffusion layer in the production of an SOI wafer having the buried diffusion layer, the polishing allowance is 0.1 μm.
Therefore, it is necessary to control the polishing allowance with an accuracy of at least ± 0.01 μm. However, in any of the above-mentioned measurement methods, the measurement accuracy is about ± 0.1 μm, so that it is not possible to sufficiently control the polishing allowance.

Therefore, a method is used in which the depth of the diffusion layer before and after polishing is measured by a destructive inspection such as a spread resistance measurement method (SR method), and an appropriate polishing time is set in advance. In this method, it is not possible to immediately cope with a polishing rate that is delicately changed when the polishing cloth or the polishing liquid is replaced or used frequently, and consequently, it is not possible to suppress variations in the polishing allowance.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and is intended for polishing a wafer that requires a fine polishing allowance management as in the case of manufacturing an SOI wafer having an SOI layer having a diffusion layer. In addition, the main object of the present invention is to provide an extremely effective method for controlling a polishing allowance, thereby manufacturing a wafer with a precisely controlled allowance and manufacturing a high-quality SOI wafer using the wafer. To make things possible.

[0013]

According to a first aspect of the present invention, there is provided a method for managing a polishing allowance when polishing a wafer, wherein at least one SOI wafer is used. A polishing allowance management method characterized by polishing under the same conditions as other wafers to be polished, calculating a polishing allowance from the thickness of the SOI layer before and after polishing the SOI wafer, and managing the polishing allowance.

As described above, at the time of polishing a wafer, at least one SOI wafer is polished under the same conditions as the other wafers, and a polishing allowance is calculated from the thickness of the SOI layer before and after the polishing of the SOI wafer. If you manage the polishing cost, SO
Since the thickness of the SOI layer of the I wafer can be calculated extremely accurately and easily, the management of the polishing allowance can be performed very accurately and effectively.

Further, at least one SOI wafer (hereinafter sometimes referred to as a monitor wafer) for polishing allowance management is used.
By polishing under the same conditions as wafers and other wafers to be polished, it is possible to immediately and accurately feed back the polishing rate, which changes slightly depending on the frequency of use and replacement of the polishing cloth or polishing solution, and it can be used for a long time. This is also effective when managing the polishing allowance continuously.

According to a second aspect of the present invention, there is provided a method for managing a polishing allowance when simultaneously polishing a plurality of wafers, wherein at least one SOI wafer is polished simultaneously with another wafer to be polished. Then, a polishing allowance is calculated by calculating a polishing allowance from the thickness of the SOI layer before and after polishing the SOI wafer and managing the polishing allowance.

As described above, when simultaneously polishing a plurality of wafers, at least one SOI wafer is polished simultaneously with another wafer to be polished, and a polishing allowance is determined based on the thickness of the SOI layer before and after polishing the SOI wafer. By calculating and managing the polishing allowance, the thickness of the SOI layer of the SOI wafer can be calculated extremely accurately and easily, so that accurate management of the polishing allowance can be performed.

By polishing at least one SOI wafer for polishing allowance management at the same time as a plurality of wafers to be polished, a polishing rate which is slightly changed depending on the replacement of the polishing pad or polishing liquid or the frequency of use is reduced. Feedback can be instantly and accurately provided, and this is also effective when managing the polishing allowance continuously for a long time. In particular, since the polishing is performed at the same time, the polishing allowance can be more accurately managed.

In this case, it is preferable that the SOI wafer for controlling the polishing allowance has the same shape, crystal orientation and impurity concentration as the wafer to be polished. Thus, the SOI wafer for polishing allowance management has the same shape, crystal orientation, and the same as the wafer to be polished.
If the wafer has the impurity concentration, the monitor wafer and the wafer to be polished are polished in the same manner, and the polishing allowance can be more accurately controlled.

Here, that the SOI wafer has the same shape as the wafer to be polished means that the thickness of the entire wafer, the shape of the orientation flat, the notch, etc. are the same, and the same crystal orientation and the same impurity concentration are used. To have means that the crystal orientation and impurity concentration of the SOI layer of the SOI wafer are the same as the wafer to be polished. However, the term “identical” as used herein means that the specifications are the same, and does not mean that the details are the same.

Further, as described in claim 4, it is preferable that the thickness of the SOI layer of the SOI wafer for controlling the polishing allowance is 10 μm or less. This is the S for polishing cost management.
This is because if the thickness of the SOI layer of the OI wafer is 10 μm or less, the thickness of the SOI layer can be measured extremely accurately and simply in a short time by a conventional optical method. Therefore, by setting the thickness of the SOI layer to 10 μm or less, the management of the polishing allowance can be performed accurately and promptly, and the polishing operation is not delayed.

As described in claim 5, the wafer to be polished may have a diffusion layer on the polished surface. For example, as described above, when manufacturing an SOI wafer having a buried diffusion layer, a wafer having a diffusion layer on a polished surface is polished as a bond wafer, and the polishing allowance is controlled with an accuracy of ± 0.01 μm. However, the method of managing the stock removal according to the present invention is particularly effective in such a case.

Further, as described in claim 6, the wafer is manufactured by polishing the wafer by using the method of managing a stock removal according to any one of claims 1 to 5. In the method, the polishing process can be easily controlled so that the variation in the polishing allowance is extremely small, so that the quality and productivity of the manufactured wafer can be improved.

Further, as described in claim 7, the wafer manufactured by the wafer manufacturing method according to claim 6 is a high quality wafer having extremely small variation in polishing allowance.

Further, as described in claim 8, the wafer manufactured by the method for manufacturing a wafer according to claim 6 and another wafer are bonded via an oxide film, and one of the wafers is thinned. The method for manufacturing an SOI wafer, which is characterized by manufacturing an SOI wafer, is extremely effective for manufacturing an SOI wafer, particularly an SOI wafer having a buried diffusion layer, and provides a high-quality SOI wafer with high uniformity at high productivity. Can be manufactured.

Hereinafter, the present invention will be described in more detail.
The present invention is not limited to these. The inventor of the present invention has conducted intensive research on a method of managing a wafer polishing allowance that can be applied when accurate management of a wafer polishing allowance is required, such as an SOI wafer having a buried diffusion layer.

As described above, in a method in which the depth of the diffusion layer before and after polishing is measured by a destructive inspection such as a spread resistance measurement method (SR method) and an appropriate polishing time is set in advance, the polishing operation is not performed. It is not possible to immediately respond to a polishing rate that slightly changes during the polishing, and it is not possible to suppress variations in the polishing allowance.

In such a case, if the monitor wafer is mixed with the product wafer to be polished for managing the polishing allowance, and the thickness of the monitor wafer before and after polishing is measured,
There is a possibility that the polishing rate that changes during the polishing operation can be responded immediately.

However, when a normal wafer such as a silicon wafer having a thickness of about 600 μm is used as the monitor wafer, the measurement is performed by a dial gauge or a capacitance-type thickness measuring instrument as described above. The thickness measurement accuracy is about ± 0.1 μm, and cannot meet the required measurement level.

Therefore, the inventor of the present invention has conceived of using a SOI wafer as the monitor wafer and calculating a polishing allowance from the thickness of the SOI layer before and after polishing the SOI wafer to manage the polishing allowance. In this SOI wafer, it is more accurate and easier to accurately measure the thickness of the thin SOI layer on the buried oxide film than to measure the entire thickness of a normal wafer.

The film thickness of the SOI layer can be measured by, for example, an optical interference method for measuring the film thickness utilizing mutual interference between reflected light from the surface of the SOI layer and the surface of the buried oxide film. In this case, when the thickness of the SOI layer is sufficiently small, the measurement can be performed using visible light.
When the thickness of the I layer is 10 μm or less, the S layer is formed with an extremely high accuracy of ± 0.01 μm by an optical interference method using visible light.
The thickness of the OI layer can be measured (Japanese Unexamined Patent Publication No.
No. 4249).

In carrying out the method of managing the stock removal according to the present invention, it is possible to carry out the method even if the wafer polishing method is a single wafer type polishing method for polishing wafers one by one. A batch-type polishing method for simultaneously polishing wafers is also possible. In this case, in the single wafer type polishing method, at least one monitor wafer may be polished under the same conditions for every several wafers to be polished, and the polishing allowance may be controlled. In at least one product wafer at the same time
One monitor wafer may be polished.

In this case, the SOI for controlling the polishing allowance is used.
The wafer preferably has the same shape, crystal orientation, impurity concentration, surface roughness, etc. as the product wafer to be polished. This is because if these conditions are different between the monitor wafer and the product wafer, the polishing progress rates of the monitor wafer and the product wafer may be different. If these conditions of the monitor wafer and the product wafer are the same, the polishing progress rate of the monitor wafer and the wafer to be polished becomes the same, and the polishing allowance can be more accurately managed.

For example, when the product wafer is provided with an orientation flat and a notch, it is preferable that the monitor SOI wafer is also provided with the same orientation flat and notch.
The SOI layer of the polishing allowance management wafer preferably has substantially the same crystal orientation and impurity concentration as the product wafer.

More specifically, when a wafer having a diffusion layer on a polishing surface is polished, a wafer for controlling a polishing allowance can be manufactured by, for example, the same specification as a high-concentration diffusion wafer to be polished ( After a supporting substrate is bonded to a wafer having no diffusion layer with a shape and crystal orientation via an oxide film, the supporting substrate is thinned to produce an SOI wafer, and the surface of the SOI layer of the SOI wafer has the same surface as the product wafer. Can be obtained by performing diffusion under the following conditions.

Alternatively, high-concentration diffusion is performed on a wafer having the same shape as that of the high-concentration diffusion wafer to be polished and without a diffusion layer under the same conditions as the product wafer, and the wafer is transferred to a supporting substrate via an oxide film. After bonding, it can also be manufactured by thinning until the high concentration diffusion layer is exposed by polishing. Alternatively, a wafer having a high impurity concentration may be prepared in advance, and an SOI wafer may be manufactured so that the wafer becomes an SOI layer.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to embodiments, but the present invention is not limited to these. In the following embodiments, the SOI wafer used for polishing allowance management has the same shape, crystal orientation, and impurity concentration as the product wafer to be polished.

(Embodiment 1) For example, when a large-diameter wafer such as an 8-inch wafer is polished by using a single-wafer polishing apparatus, one wafer is loaded on one polishing plate. Are polished one by one. SOI such that the total thickness is almost the same as the product every several wafers to be polished with a diameter of 8 inches
If a wafer is prepared as a polishing allowance monitor, an accurate polishing allowance can be grasped, and the data can be fed back to the setting of the polishing time of the next wafer.

In this case, as shown in FIG. 1, for example, the monitor wafer is first polished, the polishing allowance is accurately measured, the polishing conditions are controlled, and then 19 product wafers are polished under the same conditions. Then, the process of polishing the monitor wafer again to confirm the polishing allowance can be repeated. The frequency at which the wafer for polishing allowance management is charged depends on the magnitude of the change in the polishing rate in the polishing step. When the fluctuation of the polishing rate is relatively large, such as immediately after the replacement of the polishing cloth or the polishing liquid, for example, one monitor wafer may be prepared for ten product wafers, or when the fluctuation of the polishing rate is small. For example, one monitor wafer may be prepared for 30 product wafers.

Even if the necessary polishing allowance is about 0.1 μm, the SOI wafer as the polishing monitor wafer can be used repeatedly about 30 times.
Therefore, implementation of the present invention does not significantly affect the cost.

The method of applying the present invention to a single-wafer polishing process is suitable for polishing a large-diameter wafer having a diameter of 8 inches or more. Since the wafers are processed one by one, An advantage is that even when the diameter of the wafer is increased, the wafer can be easily handled.

(Embodiment 2) When a 5-inch wafer is polished using a batch-type polishing apparatus, for example, five wafers can be charged on one polishing plate.
Since four polishing plates are polished simultaneously per batch, a total of 20 plates / batch can be processed.

As shown in FIG. 2, one of the 20 sheets has an SOI having a total thickness almost equal to that of the product.
If a wafer is provided as a polishing allowance monitor, an accurate polishing allowance can be grasped for each polishing batch, and the data can be fed back to polishing conditions such as the polishing time of the next batch.

Assuming that the necessary polishing allowance is about 0.1 μm, the SOI wafer as a polishing monitor is
About 30 batches can be used repeatedly. Therefore, even if the present invention is implemented, it is not so much affected in terms of cost as described above.

In this method, the polishing allowance can be measured for each batch of polishing, so that it is preferably used when the polishing rate is relatively large, for example, immediately after replacement of the polishing pad or polishing liquid. . In addition, since the monitor and the product are polished at the same time, the management of the polishing allowance can be performed more accurately. Further, depending on the degree of fluctuation of the polishing rate, the use of the monitor can be reduced to every two batches or every three batches.

(Embodiment 3) As in Embodiment 2, when a 5-inch wafer is polished by a batch-type polishing apparatus, one of four plates (20 sheets) per batch is used.
After polishing the plate (5 sheets) using an SOI monitor wafer, the average value of the polishing allowance of the 5 monitors was determined.
The polishing time is adjusted so as to be a target polishing allowance, and the polishing of the second batch and thereafter is performed.

At this time, as shown in FIG. 3, after the second batch, for example, up to the fifth batch, without using a monitor, only 20 products were polished with the use of a monitor, and then the SOI was again performed at the sixth batch.
The process of checking the polishing allowance using one plate containing only the monitor can be repeated.

This method is effective when the polishing rate is relatively stable. Since one plate is constituted only by the SOI monitor, the thickness does not necessarily have to be the same as that of the product wafer. Has the advantage of being simple. Since the average value of the polishing allowance is also obtained for five wafers, more accurate monitoring is possible.

The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the scope of the claims of the present invention. It is included in the technical scope of the invention.

For example, in the above embodiment, when manufacturing an SOI wafer having a high-concentration buried diffusion layer at the bottom of the SOI layer, description has been made mainly on polishing a wafer having a diffusion layer on a polishing surface. The present invention is not limited to this, and the present invention can be applied even when polishing other types of wafers.

For example, if the present invention is applied to the finish polishing of a normal wafer, it is possible to accurately grasp the polishing allowance of the finish polishing which has not been accurately grasped conventionally, which is useful in quality control. Becomes

[0052]

As described above, in the present invention, an SOI wafer is used as a wafer for polishing allowance management and its S
By calculating the polishing allowance from the SOI layer film thickness before and after polishing the OI wafer and managing the polishing allowance, the polishing allowance can be controlled extremely accurately. This is extremely useful when high-precision management of the polishing allowance is required, for example, when manufacturing an SOI wafer having the same.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing an aspect of a first embodiment.

FIG. 2 is an explanatory diagram showing an aspect of a second embodiment.

FIG. 3 is an explanatory diagram showing an aspect of a third embodiment.

[Explanation of symbols]

1. Monitor wafer, 2. Product wafer, 3. Polishing plate.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshifumi Watari 1393 Yashiro Yashiro, Shohan-shi, Nagano F-term in Nagano Electronics Co., Ltd.

Claims (8)

[Claims] 1. A method for managing a polishing allowance when polishing a wafer, wherein at least one SOI wafer is polished under the same conditions as another wafer to be polished, and a film of an SOI layer before and after polishing of the SOI wafer is provided. A method for managing a polishing allowance, comprising calculating a polishing allowance from a thickness and managing the polishing allowance. 2. A method of managing a polishing allowance when simultaneously polishing a plurality of wafers, wherein at least one SOI wafer is polished at the same time as another wafer to be polished, and the SOI wafer is polished.
A method for managing a polishing allowance, comprising calculating a polishing allowance from a thickness of an SOI layer before and after polishing a wafer and managing the polishing allowance. 3. The polishing apparatus according to claim 1, wherein the SOI wafer for controlling the polishing allowance has the same shape, crystal orientation, and impurity concentration as the wafer to be polished. How to manage teens. 4. The polishing allowance management method according to claim 1, wherein the thickness of the SOI layer of the SOI wafer for managing the polishing allowance is 10 μm or less. . 5. The method according to claim 1, wherein the wafer to be polished has a diffusion layer on a polished surface. 6. A method for manufacturing a wafer, comprising manufacturing a wafer by polishing the wafer using the method for managing a stock removal according to any one of claims 1 to 5. 7. A wafer manufactured by the method for manufacturing a wafer according to claim 6. 8. A SOI wafer is manufactured by bonding a wafer manufactured by the method for manufacturing a wafer according to claim 6 and another wafer via an oxide film, and thinning one of the wafers. SOI wafer manufacturing method.