447050 A7 B7 五、發明說明（ 發明領域 本發明係有關於平坦化製 表程 更.仔細來說，本發明係 (清先閲讀背面之注意事項再填寫本頁) 為改善之彳I;學機械研磨製程。 發明背景： 傳統半導體的形成系統是使用 暴覆幻製程或雙重料(例如雙重軍馬覆蓋)製程，其中金 屬賴入絶緣體中而秦出的金吳,以化學機械研磨方式 移除。9化學_研磨於表面將笔致對晶片表面整弊來 說不是非常的办平坦。因為内部在金#導線、，形成的輪廓會 在不J層中气覆毛積，使晶片表气的平坦度又名加不良， 因此在金I第六層的i坦度比較4 -層為差。 發明目的及概沭： 於此本發明的目的在於提供一種用以一種平气化具 有不规則輪廓半蓬體表面的亨法。此方法包括塗佈—研磨 η 中止孕於半導體表、面：沉積_填補層於研磨中毛層之上， 此填補層之厚度大於不規细輪廓的爆度；且選擇性研磨此 •Λ 填補層向下至研攀中止層。 - 半導體表面包含一療丧金辱導線溥覆蓋住j介電 (層:、‘，研磨u層與填補層的位置在金屬導，線層.與内介電層 之d’堤補層充.)真f石jljl他廓，研.<1土止層&也交包每不 規挈輪,廓’選擇性研磨後移除了填留下研磨中 止〈層〕’所栏座留的篇補層只有在不規則輪廓之中。填補層 r 第2頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Α7 Β7 1470 50 五、發明說明（ 的厚度大於研磨中止層。選擇性的研麻勺 π评既的研磨包括選擇J[生的化學 機蜷研磨。不規則輪廓包括半導體表面因化學機_械研磨造 成的刮瘪或凹陷。中止層包括氮化矽且填補層包括—氧.化 β。 另生產積體電路晶片的發明方法包括形成戚平坦 化一金屬導線層，形成一内介電層於金屬導線層之上及重 覆形成金屬導線層、平坦化金屬導線層及形成内介電層。 平面包括金屬導線層的第一研磨，而此第一研磨形成金屬 導線層上的不規則輪廓。平面亦包括在金屬導線層上塗佈 研磨中止層。填補層再沉積於研磨中止層上，填補層的厚 度大於不規則輪廓的深度且用以平坦化的選擇性研磨填 補層向下至研磨中止層。在半導體晶片中，研磨中止層與 填補層的位置在每金屬導線層與内介電層之間。填補層充 填入不規則輪廓3 研磨中止層内含不規則輪廓，選舉性研磨大致上移除 了填補層且使研磨中止層遣留下來，所以殘留的填補層只 有在不規則輪廓之中。選舉性研磨包括化學機械研磨。不 規則輪廓包括半導體表面一個以上的刮痕或凹陷。中止層 包括氮化夺且填補層包括一氧化物。金屬導線層包括—鑲 嵌金屬導線層。 依據本發明，一積體電路晶片包括至少一具有不規則 輪廓之金屬導線層、一研磨中止層於金屬導線層之上（此 研磨中止層内含不規則輪廓）、一填補層於此不規則輪廓 令及一内介電層在研磨中止層與填補層之占。填,層實質 第3頁 本紙張尺度適用中國國家標規格⑵〇_ X 297 > ---- —IU/,·.'* 裝--- <請先閱讀背面之注意事項再填寫本頁) 幻· 經濟部智慧財產局員工消費合作杜印製 4 4 7 0 5 0 圖示如下 A7 B7 五、發明說明（） 上減小了不规則輪廓。不規則輪廓包括—個以上在半導體 表面因化學機械研磨造成的刮痕或凹陷。中 τ 增巴括氮化 矽且填補層包括—氧化物。 本發明修正了先前内介電屬沉積於晶片表面的不平 整，即防止不规則輪廓在下一金屬導線面的複製，並防止 了金屬的短路。更仔細來說’藉由介電材料選擇性的化學 機械研磨。本發明平坦化了在低位埴诖ήΑ人+ ρ τ u亙唭補的介電材料，而 選擇性的化學機械研磨在覆蓋層就终止 、 J 凡復盖增即做 為研磨中止層用。 圖式簡軍說明： 由以下本發明中較佳具體實施例之細節描狀，可以對 本發明之目的、觀點及優點有更佳的了解。本發明之參考 第1圖為具有不規則輪廓之積體電路金屬導線之二 思、 圖； 弟2圖為具有不規則輪廓及研磨中止層之積體電路金屬 導線之示意圖； {諝先閱讀背面之注意事項再填寫本頁〕 裝 訂 經濟部智慧財產局員工消費合作杜印製 線 導 屬 金 路 電 體 積 之 層 補 填 及 廓 輪 則 規； 不圖 有意 .具示 為之 圖 3 第 意 示 之 線 導 屬 金 路 電 體 積 之 廓 輪 則 規 不 有 具 為 圖 4 第 圖 及 圖 程 之 例 施 實 體 具 佳 較 明 發 本 示 表 為 圖 5 第 A 第 ^47050 A7 B7 五、發明說明（） 圖號#照說 - 13 基材 20 鑲嵌導線 21 不規則輪廓 23 不規則輪廓 30 覆蓋層/研磨中止層 40 填補層 經濟部智慧財產局員工消費合阼狂申契 發明詳細說gu- 參考第1圖的圖示’上述之不规則輪廓以剖面圖的方 式來敘述。仔細來說’第1圖闡述了在基材形成的鑲 嵌導線20及不規則輪廓21、23。當不規則輪廓21為不 均勻之化學機械研磨製程之產物時’不規則輪廓23可被 視為凹槽或剖痕。 本發明修正了先前内介電層沉積之晶片表面上的不 平整，因此防止不規則輪廓在下一金屬導線層的複製，所 以也避免了金屬的短路。更仔細來說，藉由介電材料選擇 性的化學機械研磨’本發明平坦化了在低位置填補的介電 材料，而此選擇性的化學機械研磨在覆蓋層就終止了，此 覆蓋層即做為研磨中止層用。 在化學機械研磨之後，將一層以高密度電漿（HDP)或 電漿化學氣相沉積法（PECVD)所形成之薄膜（例如小於 lOOnm)，沉積於整個晶圓上做為研磨中止或”覆蓋層 "3 0(例如氮化矽），如第2圖所示。 在研磨中止層至少包含如同以上所述可供選擇性研 磨的物質，然而，在較佳的具體實施例中，在研磨中止層 使用氮化矽’ V用以改良線路20與内介電材料的附著。 第5頁 本紙張尺度適用少國國家標準（CNS)A4規格（2i0 X 297公釐） <諳先閲讀背面之注意事項再填寫本頁) -裝 訂·-447050 A7 B7 V. Description of the Invention (Field of the Invention The present invention is more about flattening the tabulation process. To be more specific, the present invention (clearly read the precautions on the back before filling out this page) is the improvement of I; Grinding process Background of the invention: The conventional semiconductor formation system uses a blasting process or a dual-material (such as dual military-horse covering) process, in which metal is deposited in an insulator and Jin Wu is removed by chemical mechanical polishing. 9Chemical_Grinding on the surface will cause the pen to be not very flat for the whole surface of the wafer. Because the inside of the gold wire, the contour formed will be covered with hair in the non-J layer, which will make the wafer's surface flatness. Also known as bad, so the frankness of the sixth layer of gold I is 4-layer is bad. Purpose and summary of the invention: The purpose of the present invention is to provide a flattened semi-smooth with irregular contours. This method includes coating-grinding η to suspend pregnancy on the semiconductor surface and surface: depositing a filling layer on the ground wool layer, the thickness of this filling layer is greater than the degree of irregularity of the irregular contour; and selecting Sex Grind this. Λ The filling layer goes down to the research stop layer.-The surface of the semiconductor contains a conductive wire to cover j dielectric (layer :, ', the position of the grinding u layer and the filling layer is on the metal conductor, the wire layer D 'bank fill layer with inner dielectric layer.) True f stone jljl other profile, research. ≪ 1 soil stop layer & also outsource every irregular wheel, profile' selective grinding removed Fill in the post-grinding interruption [layer] 'The remaining supplementary layer is only in the irregular contour. The filling layer r Page 2 This paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) Α7 Β7 1470 50 V. Description of the invention (The thickness is greater than the grinding stop layer. Selective grinding hemp π evaluation of grinding includes the selection of J [raw chemical mechanical grinding. Irregular contours include semiconductor surface due to chemical mechanical_ mechanical grinding Scratches or depressions caused. The stop layer includes silicon nitride and the filling layer includes oxygen. Β. Another inventive method of producing integrated circuit wafers includes forming a flattened metal wire layer and forming an internal dielectric layer on the metal. Over and over the wire layer to form a metal wire layer, a planarized metal wire layer, and An internal dielectric layer is formed. The plane includes a first grinding of the metal wire layer, and the first grinding forms an irregular contour on the metal wire layer. The plane also includes a grinding stop layer coated on the metal wire layer. The filling layer is then deposited on On the grinding stop layer, the thickness of the filling layer is greater than the depth of the irregular contour and the selective grinding filling layer for flattening goes down to the grinding stop layer. In a semiconductor wafer, the position of the grinding stop layer and the filling layer is per metal wire. Between the layer and the inner dielectric layer. The filling layer is filled with an irregular contour. 3 The grinding stop layer contains an irregular contour. The electrified grinding roughly removes the filling layer and leaves the grinding stop layer behind, so the remaining filling layer Only in irregular contours. Electoral grinding includes chemical mechanical grinding. The irregular contour includes more than one scratch or depression on the semiconductor surface. The stop layer includes nitride and the fill layer includes an oxide. Metal wire layers include—embedded metal wire layers. According to the present invention, an integrated circuit chip includes at least one metal wire layer having an irregular contour, a grinding stop layer on the metal wire layer (the grinding stop layer contains an irregular contour), and a filling layer is irregular here. The contour and the inner dielectric layer occupy the grinding stop layer and the filling layer. Fill in, layer essence page 3 This paper size applies Chinese national standard specifications 〇〇 X 297 > ---- —IU /, ·. '* Pack --- < Please read the notes on the back before filling in this Page) Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du printed 4 4 7 0 5 0 The diagram below is A7 B7 5. The description of the invention () reduces the irregular contour. Irregular contours include more than one scratch or dent on the semiconductor surface caused by chemical mechanical grinding. The middle τ is silicon nitride and the filling layer includes oxide. The present invention corrects the unevenness of the previous deposition of the internal dielectric material on the wafer surface, that is, prevents the reproduction of the irregular contour on the next metal wire surface, and prevents the short circuit of the metal. In more detail, 'selective chemical mechanical polishing by dielectric materials. The present invention flattens the dielectric material supplemented at a low price, A + + ρ τ u 亘 唭, and the selective chemical mechanical grinding is terminated at the cover layer, and J is used as a grinding stop layer when the coverage is increased. Brief description of the drawings: The objects, viewpoints, and advantages of the present invention can be better understood from the following detailed description of the preferred embodiments of the present invention. The reference figure 1 of the present invention is the second thought and diagram of integrated circuit metal wires with irregular contours; the second figure is a schematic diagram of integrated circuit metal wires with irregular contours and a grinding stop layer; {谞 read the back first Please note this page before filling in this page] Binding of the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs, Du Duan line guide is a layer filling and profile rule of Jinlu Electric Volume; it is not intended. It is shown in Figure 3. The wire guide that belongs to the volume of the golden circuit is not shown in Figure 4. The figure and the example of the program are shown in Figure 5. The invention is shown in Figure 5. Section A ^ 47050 A7 B7 V. Description of the invention ( ) Drawing ## Talking-13 Base material 20 Inlaid wire 21 Irregular contour 23 Irregular contour 30 Covering / grinding stop layer 40 Filling layer Employee Intellectual Property Bureau Consumer Consumption Manifesto Invention Details of the Ministry of Economic Affairs The diagram of FIG. 1 is described in the form of a cross-sectional view. To elaborate, FIG. 1 illustrates the embedded conductive wire 20 and the irregular contours 21 and 23 formed on the substrate. When the irregular contour 21 is a product of an uneven chemical mechanical polishing process, the 'irregular contour 23 can be regarded as a groove or a crack. The present invention corrects the unevenness on the surface of the wafer on which the inner dielectric layer was previously deposited, and thus prevents the reproduction of the irregular contour on the next metal wire layer, thereby avoiding the short circuit of the metal. In more detail, by selective chemical mechanical polishing of the dielectric material, the present invention flattens the dielectric material filled at a low position, and this selective chemical mechanical polishing is terminated at the cover layer, which is Used as a polishing stop layer. After chemical mechanical polishing, a thin film (eg, less than 100 nm) formed by high-density plasma (HDP) or plasma chemical vapor deposition (PECVD) is deposited on the entire wafer as a grinding stop or "cover" Layer " 30 (such as silicon nitride), as shown in Figure 2. The grinding stop layer contains at least a substance that can be selectively ground as described above, however, in a preferred embodiment, the grinding The stop layer uses silicon nitride 'V to improve the adhesion between the circuit 20 and the internal dielectric material. Page 5 This paper is applicable to the national standard (CNS) A4 specification (2i0 X 297 mm) < 谙 read the back (Notes on this page, please fill out this page)
If/. 147050 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 然後以高密度電漿或電槳化學氣相沉積法"填補I，層 40 ’如此提出了足夠的厚度用以充填金屬化學機械研磨後 產生最深（例如200-300nm)的凹陷或刮痕，同第3圖所示。 任何適合的材料都可以用來作為填補層4 〇，而之後會被 選擇性的研磨至研磨中止層，例如填補層40可以至少包 含HDP氧化層、PECVD氧化層、旋塗氧化層或熱流氧化 層等。 接下來，在半導體表面進行選擇性化學機械研磨。以 較快的逮率研磨移除填補層4 0，再如第4圖所示向下研 磨至覆蓋層3 0以產生一平面結構。例如，使用碎基的研 漿於選擇性移除氧化層4 0。而包含鈽土或其它研磨料的 研漿可用來單單只對填補層4 0做的選擇性移除。最好是 利用較堅硬的研磨墊，使除了在刮痕23及凹陷2 1中的填 補物外’其它的都自覆蓋層表面被移除。遗留在覆蓋層3〇 範圍的填補物量並不是很重要，因為剩餘的填補物及覆蓋 層是經過選擇可相容於内介電材料層，而介電材料層將在 隨後的製程中以沉積形成。因為氮化物層的高硬度，不會 有新的缺陷（如刮痕）生成。 設定選擇性化學機械研磨的步驟一直到覆蓋看就停 止’之後用填補材料40充填遺留的凹陷》及本發明以此 方式修補氧化層平面的一致厚度以達成—般金屬中介電 材料平坦化的要求。 在此也使用一般的方法來控制研磨。例如，可以把研 磨時間限制在特定的時間完成（例如丨分鐘）。此外，研聚 第6頁 本紙張尺度適用令國國家標準（CNS)A4規格（210 X 297公釐） — -------ΙΊ I - I I (請先閱讀背面之注意事項再填寫本頁)If /. 147050 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () Then fill it with a high-density plasma or electro-chemical paddle chemical vapor deposition method "I, layer 40 'thus proposed a sufficient thickness It is used for filling metal to produce the deepest (eg 200-300nm) depressions or scratches after CMP, as shown in Figure 3. Any suitable material can be used as the filling layer 40, and then it is selectively ground to the grinding stop layer. For example, the filling layer 40 may include at least an HDP oxide layer, a PECVD oxide layer, a spin coating oxide layer, or a thermal flow oxide layer. Wait. Next, selective chemical mechanical polishing is performed on the semiconductor surface. The filling layer 40 is removed by grinding at a faster rate, and then ground down to the covering layer 30 as shown in FIG. 4 to produce a planar structure. For example, a ground-based slurry is used to selectively remove the oxide layer 40. The slurry containing vermiculite or other abrasives can be used to selectively remove only the filling layer 40. It is preferable to use a harder abrasive pad so that everything except the filler in the scratches 23 and the depressions 21 is removed from the surface of the cover layer. The amount of filling material left in the cover layer 30 is not very important, because the remaining filling material and cover layer are selected to be compatible with the internal dielectric material layer, and the dielectric material layer will be formed by deposition in the subsequent process. . Due to the high hardness of the nitride layer, no new defects (such as scratches) are generated. Set the step of selective chemical mechanical polishing until the coverage stops and then fill the remaining depressions with the filling material 40 "and the invention repairs the uniform thickness of the oxide plane in this way to achieve the requirements of flattening of general dielectric materials . General methods are also used here to control the grinding. For example, grinding time can be limited to a specific time (for example, minutes). In addition, on page 6 of this paper, the paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) — ------- IΊ I-II (Please read the precautions on the back before filling in this page)
-I-G --fo- 1470 5〇 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（ 可以做為化學性的取樣，因此當有 m ,, Λ 何覆蛊層材料30 4 研及中偵測出的時候，研磨的製程就可以馬上金士 製程的討論如同在帛5圖令的表示。更仔：：說，在 步驟60中金屬導線層2〇形成。然後金屬導線層在步 驟η中研磨，並在步驟62中塗佈上研磨中止層3〇。接 下來，在步驟63中沉積填補層40。在步騾M會施以被 選擇性的研磨至研磨中止層3〇為止。然後，在步驟65中 形成内介電層。在最後的步騾66中，重覆形成金屬導線 層平坦化金屬導線層及形成内介電層至所有的金屬導線 層都完成為止。 之後進行一般習知的製程順序中，以形成下一金屬 層。本發明未影響到覆蓋的内介電層（事實上本發明改進 了内介電層的黏著），或結構的厚度（事實上因為平坦度的 增加’内介電層的厚度可能會有增減）。所以’無需為了 對於本發明中採用附加層的做法進行補償’而在一般製程 採行其它的修正方法。再者，本發明可用於增加整體結構 中所有金屬導線層的平坦度。 使用本發明，化學機械研磨中過度研磨的金屬量會減 少。本發明重要的優點之一是製程時間的知短’而另一項 優點則是當額外的連結層的產生後，最惡劣輪廓的情況存 在。以此方式，雙重鑲嵌金屬導線比一般的方式更容易展 開，例如晶片可有至少八層的金屬導線層° 在金屬化學機械研磨，後本發明立即插入附加的步 第7頁 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） <請先閱讀背面之注意事項再填寫本頁)-IG --fo- 1470 5 0 Printed by A7 B7 of the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (can be used for chemical sampling, so when there are m ,, Λ and coating materials 30 4 research and When it is detected, the grinding process can be immediately discussed in the King's process as shown in Figure 5. More :: Say, the metal wire layer 20 is formed in step 60. Then the metal wire layer is in the step η is ground, and a grinding stop layer 30 is applied in step 62. Next, a filling layer 40 is deposited in step 63. In step 骡 M, selective grinding is performed until the grinding stop layer 30 is applied. Then, an internal dielectric layer is formed in step 65. In the last step 66, the metal wire layer is formed and the metal wire layer is planarized and the internal dielectric layer is formed until all the metal wire layers are completed. Then, the general process is performed. In the conventional process sequence, the next metal layer is formed. The present invention does not affect the covered inner dielectric layer (in fact, the invention improves the adhesion of the inner dielectric layer), or the thickness of the structure (in fact because of the flatness Increase of 'inner dielectric layer (Thickness may increase or decrease). So 'no need to compensate for the use of additional layers in the present invention' in the general process to adopt other correction methods. Furthermore, the present invention can be used to increase all metal wire layers in the overall structure Using the present invention, the amount of over-abrasive metal in chemical mechanical polishing will be reduced. One of the important advantages of the present invention is that the process time is short, and another advantage is that when an additional bonding layer is produced, The worst contours exist. In this way, the double-inlaid metal wire is easier to unfold than the normal way. For example, the wafer can have at least eight metal wire layers. After the metal is chemically and mechanically polished, the present invention inserts an additional step immediately. 7 pages of this paper size are applicable to Chinese National Standard (CNS) A4 (210 X 297 public love) < Please read the precautions on the back before filling this page)
，以產生下一層的介電材料沉積°在不規則輪廊在] 驟 1470 50To produce the next layer of dielectric material deposited at irregular contours] step 1470 50
五、發明說明（ 層：製疋前’以金屬的化學機械研磨修補不規則輪廓，以 避免不可補救的缺陷形成β 本發明解決的問題可以發生於任何形式的研磨，而且 本發明也可以應用於任何種類的研磨。相似地，本發明對 非電邊化學氣相沉積法氧化層之内介電層-樣有效，如t 密度電'氧化層'摻氣氧化層及其它低介電常數介電： 料除了氮化矽以外的薄膜材料，如果它們可與金屬導線 黏結並與填補材料40有不同的研磨速率，就可使用它們 做為覆蓋層及研磨中止I 30。除了電漿化學氣相沉積法 氧化物的其G介電材料，如果它們與覆蓋層/研磨中止層 J〇有不同的研磨速率，可用來做為填補材料40。 在半導體製程中使用本發明的最大優點就是本發明 提供緊密的結構，例如使用銅雙重鑲嵌做為〇 . 2 5 及 0，1 8 μιη接線製程，特別是在有很多金屬導線層的情況下 (例如四層以上）。 而且’本發明極適合應用在内介電材料化學機械研磨 的步驟中。在内介電材料沉積後及下一金屬層圖案化前， 利用本發明移除不規則輪廓。此種內介電材料化學機械所 磨的步驟有可能會造成孔裸露並導致在晶片及晶圓上姨 外的電容改變。而且，内介電材料化學機械研磨本身會在 殘留氧化層留下刮痕，刮痕以金屬充填，而這也可能造成 下一層金屬的短路。而化學機械研磨標準内介電氧化層的 厚度與平坦度控制著是否需要再次重覆施行，且内介電封 料的厚度均等需要被重新估量與嚴密地控制等因素，將導 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） <請先閱讀背面之注意事項再填寫本頁) 裴 訂---------線卜r 經濟部智慧財產局員工消費合作杜印製 4T〇 5〇 Α7 Β7 五、發明說明（ 致上述缺點之發生。 相反地’利用本發明在内介電材料沉積或孔蚀刻都不 需要做調整，而且沒有孔裸露、孔過蚀刻或電容的考量· 相對於層中氧化物化學機械研磨，在本發明中選擇性氧化 層化學機械研磨中的研磨中止比較容易實施。另外，以本 發明不需要控制測量，，殘留氧化物，，；因為研磨時間振（例 如一分鐘）及研磨中止層的作用，研磨I的損耗率也低| 且產能也更高了。此外’由於附加上研磨中止層的向更 度 > 選擇性氧化層化學機械研磨將不會產生刮痕的缺陷。 本發明的實施技術並不僅限於已陳述之具體實施 例，而未脫離本發明所揭示之精神下所完成之等效改變或 修飾，均應包含在下述之申請專利範圍内。 C請先閲讀赀面之注意事硪再填寫本頁) 裝 * — I I-- 線卜 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4规格（210 X 297公釐〉V. Description of the invention (Layer: Before making the puppet, the irregular contour is repaired by chemical mechanical grinding of the metal to avoid the formation of irreparable defects. The problem solved by the present invention can occur in any form of grinding, and the present invention can also be applied to Any kind of grinding. Similarly, the present invention is effective for dielectric layers in the oxide layer of non-electrical edge chemical vapor deposition, such as t-density electrical 'oxide layer', gas-doped oxide layer and other low dielectric constant dielectrics. : For thin film materials other than silicon nitride, if they can be bonded to metal wires and have a different grinding rate from the filling material 40, they can be used as a cover layer and grinding stop I 30. In addition to plasma chemical vapor deposition The G dielectric materials of the process oxides can be used as the filling material 40 if they have different grinding rates from the cover layer / grind stop layer J. The greatest advantage of using the invention in semiconductor processes is that the invention provides compactness Structure, such as using copper dual damascene as 0.25 and 0,18 μιη wiring process, especially when there are many metal wire layers (such as four Above). And the invention is very suitable for the step of chemical mechanical polishing of the inner dielectric material. After the inner dielectric material is deposited and before the next metal layer is patterned, the invention is used to remove irregular contours. The steps of chemical mechanical grinding of the dielectric material may cause the holes to be exposed and cause the capacitance on the wafer and the wafer to change. Moreover, the chemical mechanical polishing of the internal dielectric material will leave scratches and scratches on the residual oxide layer. The traces are filled with metal, and this may also cause a short circuit to the next layer of metal. The thickness and flatness of the dielectric oxide layer in the chemical mechanical polishing standard controls whether it needs to be repeated and the thickness of the internal dielectric sealing compound is equally required. Factors such as re-evaluation and tight control will apply the paper size to the Chinese National Standard (CNS) A4 (210 X 297 mm) < Please read the notes on the back before filling this page) Pei Ding --- ------ Liner r Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed 4T〇5〇Α7 B7 V. Description of the invention (causes the above disadvantages to occur. Conversely, 'use the invention No adjustments are required for electrical material deposition or hole etching, and there is no consideration of hole exposure, hole over-etching, or capacitance. Compared to the oxide chemical mechanical polishing of the layer, the grinding of the selective oxide layer chemical mechanical polishing is stopped in the present invention. It is relatively easy to implement. In addition, in the present invention, there is no need to control the measurement, residual oxide, and; because of the grinding time vibration (such as one minute) and the role of the grinding stop layer, the loss rate of grinding I is also low | In addition, 'Due to the addition of the grinding stop layer, the chemical oxidation of the selective oxide layer will not cause the defect of scratches. The implementation technology of the present invention is not limited to the specific embodiments that have been stated without departing from Equivalent changes or modifications made under the spirit disclosed in the present invention should all be included in the scope of patent application described below. C Please read the notes on the front page before filling out this page.) Installation * — I I-- Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with China National Standard (CNS) A4 (210 X 297) Mm>