TW525257B - Improvement method of forming integrated circuit shallow trench isolation region - Google Patents

Abstract

A method of planarization treatment a surface of a semiconductor substrate during formation of shallow trench isolation (STI) region is provided, which can prevent dishing occurred in wide STI region and prevent erosion occurred in the smaller silicon nitride region on the surface of the semiconductor substrate. First, in a platform, a chemical mechanical polishing (CMP) process is performed with a high (product of rotary platen pressure and rotary platen speed) to planarize the semiconductor substrate with a higher material removal rate and a lower selectivity and thus the production capacity is increased. Subsequently, when the end point is detected, the substrate is moved to a second platform for a second CMP process using a low (product of rotary platen pressure and rotary platen speed) to continue planarizing the semiconductor substrate, in which the low polishing rate can control the thickness of the trench oxide of the STI region and thus reduce dishing and erosion phenomena.

Description

525257 —---- Case No. 88100509__Year Month _Revision__ V. Description of the Invention (1) [Field of the Invention] The present invention relates to a method for chemical / mechanical planarization (CMP) of a semiconductor substrate and Device. More specifically, the present invention relates to a method and a device for planarizing a semiconductor substrate, which can reduce the occurrence of shallow dishing in a wide 'trench isolation region, and enable nitrogen on the surface of the semiconductor substrate. Erosion of siliconized compounds is minimized. [Explanation of Known Techniques] Chemical / mechanical planarization (CMP) of semiconductor substrates has been widely known by those skilled in the art. A description of CMP technology can be found in Zhang Junyan and Shi Min, ULSI Technology, published by McGraw-Hill Co. Inc., New York, 1996 — pages 434 — 439, and in the first figure after the description. The requirement for polishing the dielectric layer is to effectively remove unwanted materials while maintaining the flatness of the entire substrate surface. The CMp procedure involves chemical and mechanical grinding to remove material. Referring to FIG. 1, the grinding table 100 of the CMP machine is provided with a rotating disc 5. A polishing pad 10 is attached to the turntable 5. A semiconductor substrate 20 is fixed = on a wafer stage 15. The wafer stage 15 is lowered and the semiconductor substrate 20 is brought into contact with the polishing pad 10. The wafer stage 5 is rotated at a speed irrespective of the turntable 5, and the wafer stage 15 is adjusted to apply pressure to the turntable 5. The polishing slurry 25 is supplied from the polishing slurry supplier 30 to ensure that the polishing pad 10 is evenly wetted, and the polishing slurry 25 is appropriately supplied and recovered. The grinding slurry 25 mainly includes colloidal silica (colloidal si 1ica) suspended in a potassium hydroxide (KOH) solution. A CMP machine can have several grinding tables 100.

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) Connected to the soil grinder:

Carrying arms (cassette-to-cassette handlers and automatic wafer loaders.) The basic polishing mechanism for grinding silicon dioxide is similar to the removal rate of mechanical and mechanical removal. The removal rate can be pres ^ 〇n's eqUati〇n means R = Kppv Among them, R is the removal rate of the material, P is the pressure between the semiconductor substrate 20 and the rotating disk 5, ν is the relative rate between the semiconductor substrate 20 and the rotating disk 5, and Kρ is a proportional constant.

Preston's constant κρ is a function of the mechanical properties of the silicon dioxide dielectric layer, such as the equations of hardness and Young's parameters, polishing slurry, and the structural surface of the polishing pad. The material removal rate during flattening is mechanically studied ... With face description. However, as far as the microscopic phenomenon of grinding process is concerned, the system includes two parts: science and mechanics. Although the exact grinding process mechanism is not yet fully understood, the understanding so far has divided the chemical program part into four stages. In the first stage, the hydrogen element is bonded to the oxide surface of the semiconductor substrate 20. In the second stage, the hydrogen bond between the polishing slurry 25 and the semiconductor substrate 20 is bonded together. In the third stage, grinding slurry 25 and semiconductor win base! The silicon element of 20 is bonded to a common oxygen atom in the form of "molecular tritium." In the fourth stage, the polishing slurry 25 carrying the molecular silicon is removed, thereby removing the material on the surface of the semiconductor substrate 20. The above-mentioned stages have three important implications: the grinding process is not just abrasion of the semiconductor substrate 20 by the grinding of the silica of the polymer 25. The presence of water.

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The pH value of the solution affects the size and composition of the hydrogen bonds to determine its effectiveness. The most important factor is the formation of stone soil with a size between 10nm and 90nm. Furthermore, the particles of the grinding slurry 25 are often used in the grinding slurry 25. It is clear from the Preston's equation that the removal rate r is directly related to the applied pressure p and the speed v of the turntable. The material removal rate shown in Fig. 4 'and the selection rate of the chemical / mechanical flattening polishing process shown in Fig. 5 are related to the product of the pressure of the turntable and the speed of the turntable. Please refer to Figs. 2A and 2B to discuss the problems encountered when the conventional CMP is used to process a semiconductor substrate with a shallow trench isolation region (ST 丨) using conventional polishing techniques. An If silicon (SiOd layer 210) is formed on the upper surface of the semiconductor substrate 200. On the silicon dioxide layer 210, a layer of silicon nitride (Six Ny) is deposited to form a planarization termination layer 2 1 5. An optical lithography mask (not shown) is formed on the chemical treatment termination layer 2 1 5. The above-mentioned optical lithography mask is subjected to an exposure procedure to form a pattern defining shallow grooves 205a, 205b, 205c, and 205d, and then the optical The lithographic mask performs a development process to expose areas where the semiconductor substrate 200 will form shallow trenches 205a, 205b, 205c, and 205d. The surface of the semiconductor substrate 200 is exposed to an etchant, and the planarization is sequentially removed. Process the termination layers 2 1 5, the Si 2 layer 2 1 0, and a portion of the semiconductor substrate 2 00 to form shallow trenches 205a, 205b, 205c, and 20 5d. A 3 丨 02 filler is deposited on the semiconductor substrate On the surface of 200. This step of depositing the filling material can usually be achieved by OrTEOS chemical vapor deposition (CVD) or spin-on-glass (S0G) procedures, which are well known to those skilled in the art. Then, using the above The described CMP procedure removes Si 02 filler 22 0.

525257 V. Description of the invention (4) The step of grinding and removing the Si 02 filler 220 is performed until the surface thereof is equal to the leveling treatment termination layer 2 1 5. However, the conventional CMP procedure causes three forms of problems on the surface of the semiconductor substrate 2000. The first problem is shown in section I of Fig. 2B. The surface of the semiconductor substrate 2000 is excessively polished, causing the planarization termination layer 215 of the SixNy material to suffer from erosion and thinning. The second question is shown in section Π of Figure 2B. The surface of the semiconductor substrate 2000 was over-polished again. However, in this example, the polishing of the turntable caused over-grinding and shallow dishing. This shallow dishing phenomenon occurs in the area where large shallow trenches 205c and 205d are distributed, which completely removes the planarization termination layer 207. The third question is shown in the section dish in Figure 2B. The surface area of the semiconductor substrate 200 is insufficiently polished, so that the Si 02 filler 2 2 0 remains on the surface of the semiconductor substrate 200. The present invention is used to control the rate of the grinding mill by placing a process field. The Tsai field can be used in a semi-directed electric field. The Tsai field is in US Pat. No. 5,575,706 of Tsai et al. Improved mechanical planarization of the surface of semiconductor wafers. A switch is applied between the semiconductor wafer stage and the polishing pad. The semiconductor wafer stage and the "influence polishing removal speed wafer wafer stage" Uniformity with the material removal of the polishing pad. You can further control the application of the material to the area.-The polishing device body wafer stage and polishing pad proposed by Shuang et al. Are novel. Control to be ground

525257 V. Description of the invention (5) Device for grinding slurry concentration on the surface of a semiconductor substrate. Controlling the concentration of the polishing slurry and the polishing removal rate will improve the uniformity of the polishing removal rate on the surface of the semiconductor wafer.

U.S. Patent No. 4,671,851 to Beyer et al. Discloses a method for removing protrusions (^ 1) 11 ^ 1 ^ 3) on the surface of a silicon substrate after a 1-step removal process, usually a ridge shape Si〇2 prominence, called "bird, s heads". This invention is achieved by applying MCMp treatment to the surface of a silicon substrate. 3 The Shi Xi substrate has been covered with a polishing stop barrier layer, usually a CyD-programmed SisN4 layer. Because it withstands a higher CMP polishing rate than that covered on a flat portion of the substrate surface, the SisN4 layer on the top of the bird's head arc and the underlying Si02 protrusion can be removed. In this way, the CVD layer is unexpectedly only used as a research or etching stop barrier layer on a flat portion of the substrate surface. The difference in these polishing rates can be changed by applying different pressures to the polishing pads. The success of the CMP process in flattening these protrusions depends on the chemistry of the polishing solution. In this respect, the grinding slurry, which is dominated by the S 100 solution, has proven its effectiveness.

The polishing rate ratio between SiO2 and S "N4 must be between the lower limit of 4 to 1 and the upper limit of 40 to 1.

The U.S. Patent to Subamanian et al. Teaches a process for grinding and flattening a filling material overlying a semiconductor substrate. In one embodiment, 'a second planarization layer is deposited on the filling material, and a portion of the filling material is removed while leaving other portions. The pressure of the polishing pad of the CMP device is adjusted to generate a first pressure during the polishing procedure. Then, the other parts of the filling material were removed, and the CMP device was operated at a second pressure. According to 525257 and (6) of the polishing program, the selectivity can be maintained by reducing the pressure of the polishing pad in the second-stage polishing process. In the second embodiment, after the first-stage grinding process is performed, the remaining part of the filling material is removed by an etching process. In view of this, it is an object of the present invention to provide a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region. Another object of the present invention is to provide a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region, so as to prevent the planarization treatment termination layer of the nitride material from being invaded. The present invention also has the object of providing a method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region, so as to avoid shallow dishing in a larger area of the shallow trench isolation region. Yet another object of the present invention is to partially dioxygenate the termination layer above the semiconductor substrate on the surface of the semiconductor substrate in the trench isolation region. A method for planarizing a shallow trench is provided to avoid the planarization of the fossil layer left on the silicon nitride material. In order to achieve the above and other objectives, the present invention proposes to rationalize the surface of a semiconductor substrate with a shallow trench isolation Methods. = High-speed "product of the pressure of the turntable and the speed of the turntable" under the conditions of implementation: / mechanical flattening grinding order to flatten the semiconductor-based "product of the pressure of the turntable and the speed of the turntable" conditions, ^ material removal rate And lower selection rate to improve well 1 (Zhongzhiquan Tongbai, throughput). Then check the silicon nitride termination refining end point. θ 疋 Road out to detect when the end point of the grind used to indicate that the nitrogen-cut region has been exposed is detected

525257, invention description (7) $ and use a low "product of turntable pressure and turntable speed" to implement a flattening / mechanical planarization polishing process to continue flattening the semiconductor substrate by slowing the polishing rate In order to control the thickness of the trench oxide in the shallow trench isolation region, the shallow dish depression and erosion phenomenon are reduced. The "Hai method further includes a step of buffing the surface of the semiconductor substrate to remove the residue of the above-mentioned chemical / mechanical planarization polishing process, and to remove microscratches on the surface of the semiconductor substrate. The method for planarizing the surface of a semiconductor substrate having a shallow trench isolation region is completed on a chemical / mechanical planarization (CMP) polishing machine. Among them, the grinding process performed at the product of the high turntable pressure and the speed of the turntable is performed on the first platform (pUten) of the CMP polishing machine, and it is performed at the product of the low turntable pressure and the speed of the turntable. The polishing procedure is performed on the second platform of the CMP polishing machine; the polishing step is performed on the third platform of the CMP polishing machine. The value of the product of the turntable pressure and the turntable speed for the south ranges from about 500 Psi-rpm to about 700 psi-rpm, preferably about 600 psi-rpm. At the product of high turntable pressure and turntable speed, the optimal turntable pressure is between about 7 p s i to 8 p s i. The value of the product of low turntable pressure and turntable speed is between about 2000 psi-rpm and about 400 psi-rpm, preferably about 300 psi-rpm. In the case of the product of the low turntable pressure and the turntable speed, the optimal turntable pressure is between about 3 p s i to 4 p s i. [Brief description of the drawings] In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier

525257

Understand that the following is a detailed description of a preferred embodiment and the accompanying drawings. Figure 1 is a schematic diagram of the polishing station of a chemical / mechanical planarization (CMP) polishing machine; port 2A Figures 2 and 2B are cross-sectional views of a semiconductor substrate, showing the formation of trench isolation regions, and the conventional planarization process of the semiconductor substrate = the problem; the third figure is that the planarization process of the present invention has shallow trenches. Flowchart of half-body base method for trench isolation area;

Figure 4 is a graph of the grinding rate of two kinds of dioxide gap fillers (〇3_TE〇s and §〇 (;) and the silicon nitride layer relative to the product of the pressure of the turntable and the speed of the turntable; and _ Figure 5 is Os -The graph of the relationship between the grinding selectivity of TEOS relative to SOG and silicon nitride layer, and the product of the rotary table pressure and rotary table speed. [Detailed description of the invention] Now refer to FIG. 4, for 〇3-TEOS CVD The silicon dioxide (SiOJ filling material 400, silicon nitride (SixNy) 42) formed by the procedure, and the SiO 2 filling material 41 formed by spin-on glass sheep (SOG) have a grinding rate or material removal rate. Let's discuss. As you can see, silicon nitride (SixNy) 42 is the one with the lowest abrasion rate (removal rate) among these materials. Of a given turntable pressure and rotation degree product, OfTEOS CVD sequence is formed SiO 2 (SiO 2) filler 40 0 has the fastest grinding rate, while spin-on glass (S 0 G)

Si02 filler 410 has a polishing rate similar to that of silicon nitride (SixNy) 42.

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V. Description of the invention (9) Therefore, the training layer 220 in Figure 2B can be selected at a relatively fast rate. When the flattening process of the SixNy material terminates the layer, it means that the pressure of the turntable and the turntable are two. The end of the processing of the velocity product value is achieved by the methods commonly used by this artist, such as visual inspection to the change in the material removal rate. 】 $ 疋 探知 Figure 5 shows the selection rate of materials during the chemical / mechanical planarization polishing process. The so-called selectivity is compared = rate: 03-the recommended dioxide formation by CVD process 2) fill 1 = the selectivity of the rat fossil evening (SlxNy) is shown in the curve 500. Cogan clearly observed that the silicon dioxide (SiO2) filler formed by the 0-TEOS CVD process was removed at a rate of about 3.0 to 3.5 times faster than that of a 3N nitride (SixNy). And, under the condition that the product of the pressure of the turntable and the speed of the turntable is low, the selection rate is still about 3.5. Therefore, when the silicon nitride is exposed to planarize the termination layer, reducing the product of the pressure of the turntable and the speed of the turntable will be more conducive to controlling the thickness of the Si02 layer 220 in the figure. In addition, the lower product of the pressure of the turntable and the speed of the turntable also helps to reduce the problem of dish sags and erosion shown in Figure 2B, and can completely remove the "〇2 层 22 ( ). Now referring to FIGS. 1 and 3, a method for planarizing a semiconductor substrate having a shallow trench isolation region is summarized. When the Si02 layer 220 of FIG. 2A is deposited on the semiconductor substrate 2 of FIG. 2A 〇〇 After the surface, the semiconductor substrate 20 shown in FIG. 1 is fixed on the wafer stage 15. The turntable 5 and the wafer stage 15 are rotated, and then the turntable 5 is brought into contact with the wafer stage 5 to start polishing. Semiconductor substrate 2 0. Grinding slurry 25 is injected to drown the grinding on the turntable 5

Page 12 525257 V. Description of the invention (10) 塾 1 〇 'The semiconductor substrate 20 is then ground under the condition of a high product of the turntable pressure and the speed of the turntable. According to the results of the inventor's experiments, the product of the so-called high turntable pressure and the speed of the turntable is between about 500 psi_rpm and 700 pSi-rpm ', preferably about 600 pS / rpm. At the product of high turntable pressure and turntable speed, the optimal turntable pressure is about 7

Psi to 8 psi. Thereby, a higher material removal rate can be obtained and more semiconductor substrates can be planarized in the same time, thereby achieving the effect of improving productivity. 2. Check the semiconductor substrate 20 to check whether the planarization stop layer 215 of the nitride nitride material shown in FIG. 2A is exposed. In step 31 of FIG. 3, if the planarization stop layer 215 of the silicon nitride material shown in FIG. 2A has not been exposed, then the process of step 300 is continued according to the instruction of No. 312, that is, in When the product of the high turntable pressure and the speed of the turntable continues to grind the semiconductor substrate 20 ° for one second to reach the end point of the si of Figure 2A, the grinding end of layer 2 2 0, that is, the nitride is not shown in Figure 2A When the flattening stop layer 215 of the evening material is exposed, the process of step 320 is performed according to the instruction of the arrow 315, which uses a low "product value of turntable pressure 2 and turntable speed" to perform a chemical / mechanical flattening polishing ^ Continue to planarize the semiconductor substrate. The product of the low turntable pressure and the speed of the turntable here ranges from about 200 psi-rpm to about 400 psirpm, preferably about 300 psi_rpm. At the product of low turntable pressure and turntable speed, the optimal turntable pressure is between about 3 psi to 4 P, si. As shown in FIG. 5, the product of the low turntable pressure and the turntable speed can increase the grinding selection rate, so the step 320 is performed at the low turntable pressure and

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The lapping procedure under the condition of 1 speed multiplication value can be controlled by slowing down the lapping rate. The thickness of the Si0 2 layer in Fig. 2B is 22 0, and the silicon nitride (SixNy) in section j of Fig. 2B is reduced. The flattening treatment termination layer 215 has an erroson phenomenon and a shallow trench and dish dishing in the ninth figure. ^ When step 32 0 is completed, the product of the low disk pressure and the disk speed is applied. After the polishing procedure under the optimal conditions, the dressing procedure of step 33 is performed. Deionized water is added to the polishing pad 10, and the surface of the semiconductor substrate 20 is gently buffed to remove the chemical / mechanical planarization polishing. Residues of the grinding slurry during the process. And, the polishing process can also remove micro scratches on the surface of the semiconductor substrate 20. The above method can be effectively applied to multiple grinding tables (mul tipie P ^ hsUng station). ) On the CMP grinding machine. Among them, the first platen of the cMp grinding machine can perform the grinding procedure under the condition of the high rotary table pressure $ /, and the speed of the multiplication value as described in step 30; First platform The polishing procedure under the condition of the product of the low rotary table pressure and the rotary table speed described in step 32 can be performed. The polishing and dressing procedure of step 33 can be performed in the third platform of the CMP polishing machine. There are many methods for testing The polishing end point of the Si 0 2 layer in FIG. 2A is, for example, the thickness of the Si 0 2 layer or the silicon nitride layer can be measured by using an ellipsometry technique. In addition, as described above, the polishing rate of silicon nitride is low. The friction is relatively large. In order to maintain a "stable turntable speed, the amount of current applied to the turntable is bound to increase. Therefore, the change in the amount of current applied to the turntable through the Phoenix Control can also measure the end point. Μ

Page 14 525257 Correction No. 881 (105 ^ V. Description of the invention (12) According to the preferred embodiment of the technology of the present invention, it is possible to use the automatic E-to-box handling arms (cassette_t〇_cassette handlers) and An automatic wafer loader moves the semiconductor substrate 20 from the first grinding table to the second grinding table, and then to the third grinding table. Although the present invention is disclosed above in a preferred embodiment, it is It is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the scope of the attached patent application. [Element symbol description] 5 ~ rotating disk; 15 ~ wafer stage; 25 ~ polishing slurry; 100 ~ polishing table; 205a, 205b, 20510 ~ polishing pad; 20 ~ semiconductor substrate; 3 0 ~ grinding slurry supplier; 205d ~ shallow groove pattern 2 1 0 ~ silicon dioxide layer; 2 1 5 ~ flattening treatment termination layer (for example, silicon nitride sound 220 ~ Si02 filler; day '400 ~ grinding OrTEOS Si02 Filler Rate curve; 4 10 ~ rate curve of Si SiO 2 filler for grinding SOG; 4 2 0 ~ rate curve for grinding silicon nitride layer; 50 0 ~ OfTEOS grinding selectivity curve for silicon nitride layer; 510 ~ 〇3- 丁 £ 03 grind selectivity curve with 80%; page 15503-3475-EF1; TSMC-1-97-509 »Jacky.ptc

Claims (1)

525257 Under the condition of "product of turntable pressure and turntable speed" in the south :: learning / mechanical flattening and grinding process, #this can remove higher material = and lower selectivity to flatten the semiconductor substrate, thereby improving Its production throughput; 1. A method for flattening half of the surface when forming a shallow trench isolation region "^ surface" to prevent shallow depression (d1Shlng) from occurring in a wide, shallow trench isolation region, and Avoiding erosion on the surface of the semiconductor substrate surface, including the following steps: the hole detection of j is used to mark the exposed end point of the silicon nitride region; and when the end point of the end point is reached, a low r dial is used. "Pressure and turntable speed = product value" to perform a chemical / mechanical planarization polishing process' to continue to planarize the semiconductor substrate, which slows down the polishing rate to control the thickness of the trench emulsion in the shallow trench isolation region and reduces Shallow dish depression and invasion. 2 · The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of patent application, further comprising a step of buffing the surface of the semiconductor substrate to remove the above chemical / Residues of the grinding process are mechanically planarized and microscratches on the surface of the semiconductor substrate are eliminated. 3. The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of the patent application, wherein the grinding process is performed at a high value of the product of the turntable pressure and the turntable speed, It is performed on a first platen of a chemical / mechanical planarization device. 4 · The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of the patent application, wherein the grinding process is performed at a low multiplication value of the disk pressure and the disk speed, Tied to one 0503-3475-EF1; TSMC-1-97-509; Jacky.pt page 16 525257 _ plug No. 88100509 _ year month day _ article Zheng _ — six, the scope of the patent application / mechanical flattening device on the second platform of. 5. The method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 2 of the scope of patent application, wherein the step of polishing the surface of the semiconductor substrate is performed by a chemical / mechanical planarization device. The third platform. 6. The method for flattening the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 1 of the scope of patent application, wherein the product of the high turntable pressure and the turntable speed is between about 500 psi_rpm Up to about 700ps i-rpm 〇7. A method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item i of the patent application scope, wherein a low turntable pressure and a turntable speed The product value ranges from about 2000 psi_rpm to about 400 psi-rpm ° 8. The method for planarizing the surface of a semiconductor substrate when forming a shallow trench isolation region as described in item 丨 of the patent application range, Among them, at the product of high turntable pressure and turntable speed, its turntable pressure is between about 7 psi and 8 ps i. ± 9. As described in item 1 of the scope of the patent application, the method of forming a semiconductor substrate surface in a shallow trench isolation region is described below. When the product of the low disk pressure and the disk speed is a medium value, the disk pressure is referred to (Approximately 31) "to 4 ps i 〇10.-A method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate, including the following steps: The main tomb of the main tomb has a nitrogen substrate A siliconized barrier layer is deposited on the surface of the semiconductor substrate; 525257 Correcting and broadcasting the shallow trenches inscribed on the surface of the edge semiconductor substrate to form a region for making the shallow trench isolation region; shape, a silicon dioxide layer covers the surface of the semiconductor substrate; Perform the & pre / mechanical planarization polishing procedure under the condition of "product value of turntable pressure and turntable speed" to flatten and remove high-speed and high-speed, dream-like, + on the surface of the semiconductor substrate to thereby increase k liters. Its production capacity (produc ti on throughput); detection is used to indicate the polishing end point of the silicon nitride barrier / layer has been exposed; when ^ field reaches the polishing end point, use a lower "turntable pressure and turntable speed ^ = product value" A chemical / mechanical planarization polishing process is performed to continue to planarize the holmium semiconductor substrate, which slows down the polishing rate to control the thickness of the trench oxide in the shallow trench isolation region and reduces shallow dishing and erosion. 1, 1 1 · The method for forming / substantially planarizing a shallow trench integrated circuit structure on a semiconductor substrate as described in item 1 of the scope of patent application, further including a step of buffing the surface of the semiconductor substrate To remove residues from the above-mentioned chemical / mechanical planarization polishing process and eliminate microscratches on the surface of the semiconductor substrate. 1 2 · A method for forming a shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the scope of patent application: a substantially planar shallow trench integrated circuit structure, which is performed when the product of the pressure of the turntable and the speed of the turntable is high The grinding process is performed on the first platen of a chemical / mechanical planarization device. 1 3 · The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item No. of the patent application scope, wherein the method is performed at the time of the product of the low turntable pressure and the turntable speed. mill 525257 __ Case No. 88100509 ___ Month _ _ Zheng Zheng 6. Scope of patent application ^ It is carried out on the second platform of a chemical / mechanical planarization device. 1 4 · The method for forming a substantially planar shallow trench integrated circuit structure on a semiconductor substrate as described in item 11 of the scope of the patent application, wherein the step of polishing the surface of the semiconductor substrate is a chemical / mechanical planarization The third platform of the device was carried out. 1 5 · The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the scope of the patent application, wherein the product value of the high turntable pressure and the turntable speed is between about 5 0 0 pSi-rpm to about 7 0 0 ps i-rpm 〇1 6. A method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate as described in item 10 of the patent application scope, wherein The product of the low turntable pressure and the turntable speed is between about 2000 psi-rpm and about 400 ps i-rpm. 〇1 7 · As described in item 10 of the scope of patent application, a rough A method of flattening a shallow trench integrated circuit structure, wherein at a product value of a high turntable pressure and a turntable speed, its turntable pressure is between about 7 ps i to 8 ps i 〇1 8 The method for forming a substantially flat shallow trench integrated circuit structure on a semiconductor substrate described in item i ′, where the product of the low turntable pressure and the speed of the turntable has a turntable pressure of about 3 ps i To 4 ps i 〇 0503-3475-EFl; TSMC-1-97-509; Jacky.ptc buy 19