TW200921773A - Method for producing a semiconductor wafer with a polished edge - Google Patents

Method for producing a semiconductor wafer with a polished edge Download PDF

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Publication number
TW200921773A
TW200921773A TW097143873A TW97143873A TW200921773A TW 200921773 A TW200921773 A TW 200921773A TW 097143873 A TW097143873 A TW 097143873A TW 97143873 A TW97143873 A TW 97143873A TW 200921773 A TW200921773 A TW 200921773A
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TW
Taiwan
Prior art keywords
polishing
edge
polished
semiconductor wafer
sided
Prior art date
Application number
TW097143873A
Other languages
Chinese (zh)
Inventor
Klaus Roettger
Werner Aigner
Makoto Tabata
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Siltronic Ag
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Publication of TW200921773A publication Critical patent/TW200921773A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering

Abstract

The invention relates to a method for producing a semiconductor wafer with a polished edge, said method comprising the following steps: a polishing of at least one side of the semiconductor wafer, and a polishing of the edge of the polished semiconductor wafer, wherein the edge is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive.

Description

200921773 六、發明說明： 【發明所屬之技術領域】 本專利申請係關於一種製造具有經拋光邊緣之半導體晶圓之方 法’該方法包含使用一含有固定研磨料之拋光布來拋光該邊緣。 在下文中，將利用此類拋光布進行之邊緣拋光縮寫為FA拋光 (fixed abrasive polishing) 〇 【先前技術】 半導體晶圓的邊緣加工受到越來越多的關注。具有預定邊緣形 狀（edge form)的平滑邊緣係所需者。通常可透過研磨一從晶體 切割出之半導體晶圓的粗糙邊緣而製造該邊緣形狀。為了平滑該 邊緣並去除研磨期間所留下的晶格損傷，需要對該邊緣進行拋 光。此可使用一不含固定研磨料之拋光布來完成。在此情況下， 係透過一含有自由研磨料之漿料來實現該拋光。與此邊緣拋光相 比（於下文中簡稱為布拋光）’ FA拋光所具有的優點是能避免較 複雜的漿料處理並能獲得更高的產量。相對於此優點’ FA拋光的 缺點是經拋光之邊緣較不平滑。美國專利第6,514,423 B1號中建 議在FA拋光之後蝕刻邊緣，從而減少其粗糙度。 如上所述，除了邊緣的低粗糙度之外，亦必須注意的是確保邊 緣的形狀能符合要求。對此，可以確定的是，對半導體晶圓之一 面或兩面進行拋光會對邊緣的形狀產生不利的改變。另外，此問 題亦無法透過改變流程鏈（pn)eessehain)而解決，舉例古之如 美國專利第6，162,73G號中所述，其僅在第—次拋光半導體晶圓的 兩面之後提供邊緣的布拋光。 200921773 【發明内容】 因此，本發明之目的是提出一種方法，該方法可製造一具有完 全符合粗链度和形狀要求之經抛光邊緣之半導體晶圓。 該目的係透過一製造具有經拋光邊緣之半導體晶圓之方法而實 現，該方法包含：拋光該半導體晶圓之至少一面；以及拋光該經 拋光之半導體晶圓的邊緣；其中，係在一拋光劑的存在下、利用 一含有固定研磨料之拋光布抛光該邊緣。 【實施方式】 本發明係利用以下見解：可使用FA拋光來修正經拋光之半導體 晶圓的邊緣形狀，而非使用布抛光。 該方法係用於一邊緣已經實施過一成形加工步驟（較佳為研磨 步驟）但仍未進行拋光之半導體晶圓。本方法係以半導體晶圓之 至少一面之拋光作為開始。此涉及一單面拋光或雙面拋光。較佳 係同時實施一雙面拋光。一適用於雙面拋光之機器係如德國專利 第100 07 390 A1號中所述。在拋光期間，半導體晶圓係位於一供 作引導盒之載體的切口中，且係位於上拋光板與下拋光板之間。 至v 抛光板及载體係•轉的，並且於提供一抛光劑的情況下、 半導體晶圓係相對於覆蓋有拋光布之拋光板在一由滾線所預定的 路徑上移動。拋光板施加於半導體晶圓上之拋光壓力以及拋光持 續時間’係關鍵地共同決定透過拋光所引起之材料去除的參數。 半導體晶圓之至少一面的拋光較佳以去除拋光來執行，換言 之，其目的係從半導體晶圓將要被拋光之面去除厚度至少為5微 米的材料。 4 200921773 半導體晶圓之一面或雙面的拋光所造成之邊緣形狀的改變係透 過邊緣的FA抛光來修正。 在FA拋光過程中，係使用含有諸如礙化矽顆粒、二氧化矽顆粒 或鑽石顆粒之固定研磨料的拋光布。根據一實施態樣，FA拋光係 在一液體拋光劑的存在下，例如在水的存在下而實現。為了平滑 邊緣，即為了減少其粗糙度，在此情況下較佳係使用一具有目數 (mesh)較佳不小於4000之特別細之研磨料的拋光布，即，平均 顆粒直徑不大於5微米，尤佳係不大於4微米。在使用儘量細的 研磨料來實現拋光並以細研磨料結束的過程中，多階段FA拋光亦 係特別適合的。此類拋光步驟順序和適合的拋光設備係如美國專 利第2006/0252355 A1號中所述。 根據本方法之第二實施態樣，FA拋光係在一含有例如膠狀二氧 化矽或氧化鈽的自由研磨料之漿料的存在下進行。 第三實施態樣係涉及首先在一液體拋光劑的存在下進行FA拋 光，然後在一含有例如膠狀二氧化矽或氧化鈽的自由研磨料之漿 料的存在下進行布拋光。在此情況下，拋光布之固定研磨料的平 均顆粒直徑可以大於後續布拋光中所分佈的顆粒直徑。在進行後 續布拋光時，較佳係使用具有目數為1000至2000之固定研磨料 的拋光布，即平均顆粒直徑為7至25微米。布拋光的持續時間可 以為非常短的15至30秒。 根據本發明之方法較佳亦包含一以單面拋光進行之半導體晶圓 正面的拋光。半導體晶圓之正面係被視為半導體晶圓準備製作電 子元件的那一面。該單面拋光，下文稱為CMP (化學-機械拋光）， 5 200921773 較佳係以光澤拋光（luster polishing )來實施，其係以提供盡可能 最光滑之側表面為目的而進行。CMP的材料去除，厚度最多為1 微米，其係明顯小於去除拋光之情況下的厚度。正面的CMP較佳 係在雙面拋光之後且在FA拋光之前或之後進行。 根據本發明之方法亦可視情況包含在半導體晶圓的正面上沉積 一蟲晶層。200921773 VI. Description of the Invention: [Technical Field of the Invention] This patent application relates to a method of fabricating a semiconductor wafer having a polished edge. The method comprises polishing the edge using a polishing cloth containing a fixed abrasive. In the following, edge polishing using such a polishing cloth is abbreviated as FA (fixed abrasive polishing) 先前 [Prior Art] Edge processing of semiconductor wafers is receiving more and more attention. A smooth edge with a predetermined edge form is required. The edge shape can typically be made by grinding a rough edge of a semiconductor wafer that is cut from the crystal. In order to smooth the edge and remove the lattice damage left during grinding, the edge needs to be polished. This can be done using a polishing cloth that does not contain a fixed abrasive. In this case, the polishing is achieved by a slurry containing a free abrasive. Compared with this edge polishing (hereinafter referred to as cloth polishing), FA polishing has the advantage of avoiding more complicated slurry processing and achieving higher yield. Relative to this advantage, the disadvantage of FA polishing is that the polished edges are less smooth. It is proposed in U.S. Patent No. 6,514,423 B1 to etch the edges after FA polishing to reduce the roughness thereof. As mentioned above, in addition to the low roughness of the edges, care must be taken to ensure that the shape of the edges meets the requirements. In this regard, it can be ascertained that polishing one or both sides of the semiconductor wafer adversely affects the shape of the edge. In addition, this problem cannot be solved by changing the process chain (pn) eessehain. For example, as described in U.S. Patent No. 6,162,73G, it provides an edge only after polishing the two sides of the semiconductor wafer. The cloth is polished. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor wafer having a polished edge that is fully compliant with coarse chain and shape requirements. The object is achieved by a method of fabricating a semiconductor wafer having a polished edge, the method comprising: polishing at least one side of the semiconductor wafer; and polishing an edge of the polished semiconductor wafer; wherein The edge is polished using a polishing cloth containing a fixed abrasive in the presence of the agent. [Embodiment] The present invention utilizes the insight that FA polishing can be used to correct the edge shape of a polished semiconductor wafer instead of using cloth polishing. The method is applied to a semiconductor wafer having an edge having been subjected to a forming process step (preferably a grinding step) but still not polished. The method begins with polishing of at least one side of a semiconductor wafer. This involves a single side polishing or double side polishing. It is preferred to carry out a double-sided polishing at the same time. A machine suitable for double-sided polishing is as described in German Patent No. 100 07 390 A1. During polishing, the semiconductor wafer is placed in a slit for the carrier of the guide cassette and is located between the upper and lower polishing plates. To v the polishing plate and the carrier are rotated, and in the case where a polishing agent is provided, the semiconductor wafer is moved relative to the polishing plate covered with the polishing cloth in a path predetermined by the rolling line. The polishing pressure applied to the semiconductor wafer by the polishing pad and the polishing duration' critically determine the parameters of the material removal caused by the polishing. Polishing of at least one side of the semiconductor wafer is preferably performed by removing the polishing, in other words, the purpose is to remove material having a thickness of at least 5 microns from the side of the semiconductor wafer to be polished. 4 200921773 The change in the shape of the edge caused by the polishing of one or both sides of the semiconductor wafer is corrected by the FA polishing of the edge. In the FA polishing process, a polishing cloth containing a fixed abrasive such as smear particles, cerium oxide particles or diamond particles is used. According to one embodiment, the FA polishing is effected in the presence of a liquid polishing agent, such as in the presence of water. In order to smooth the edges, that is, to reduce the roughness thereof, it is preferred to use a polishing cloth having a particularly fine abrasive having a mesh number of preferably not less than 4000, that is, an average particle diameter of not more than 5 μm. , especially good is no more than 4 microns. Multi-stage FA polishing is also particularly suitable during polishing with finest abrasives and finishing with fine abrasives. Such a sequence of polishing steps and a suitable polishing apparatus are as described in U.S. Patent No. 2006/0252355 A1. According to a second embodiment of the method, the FA polishing is carried out in the presence of a slurry containing a free abrasive such as colloidal cerium oxide or cerium oxide. The third embodiment relates to first performing FA polishing in the presence of a liquid polishing agent and then performing cloth polishing in the presence of a slurry containing a free abrasive such as colloidal cerium oxide or cerium oxide. In this case, the fixed abrasive of the polishing cloth may have an average particle diameter larger than the diameter of the particles distributed in the subsequent cloth polishing. In the case of the subsequent polishing, it is preferred to use a polishing cloth having a fixed abrasive having a mesh number of from 1,000 to 2,000, i.e., an average particle diameter of from 7 to 25 μm. The duration of the cloth polishing can be as short as 15 to 30 seconds. The method according to the invention preferably also comprises a polishing of the front side of the semiconductor wafer by single-sided polishing. The front side of the semiconductor wafer is considered to be the side on which the semiconductor wafer is to be fabricated. This single-sided polishing, hereinafter referred to as CMP (Chemical-Mechanical Polishing), 5 200921773 is preferably carried out by luster polishing, which is carried out for the purpose of providing the smoothest side surface possible. The CMP material is removed to a thickness of up to 1 micron, which is significantly less than the thickness of the polished finish. The front side CMP is preferably performed after double side polishing and before or after FA polishing. The method according to the invention may also optionally comprise depositing a layer of insect crystal on the front side of the semiconductor wafer.

以下四個步驟順序a )到d )為尤佳的順序： a)雙面拋光->FA拋光— CMP b )雙面抛光-> FA抛光-布抛光—CMP c) 雙面拋光— CMP—FA拋光 d) 雙面抛光—CMP->FA抛光-^布抛光 【圖式簡單說明】 (無） 【主要元件符號說明】 (無） 6The following four sequence steps a) through d) are preferred: a) double side polishing - > FA polishing - CMP b) double side polishing - > FA polishing - cloth polishing - CMP c) double side polishing - CMP -FA polishing d) double-sided polishing - CMP -> FA polishing - ^ cloth polishing [schematic description] (none) [Main component symbol description] (none) 6

Claims (1)

200921773 ' 七、申請專利範圍： 1. 一種用於製造具有經拋光邊緣之半導體晶圓之方法，包含： 拋光一半導體晶圓之至少一面；以及 拋光該經拋光之半導體晶圓的邊緣； 其中，係在一拋光劑的存在下、利用一含有固定研磨料之拋光 布拋光該邊緣。 2. 如晴求項1所述之方法，其中該拋光劑含有自由研磨料。 3. 如請求項1或2所述之方法’其中該半導體晶圓之至少一面的 拋光係包含進行一雙面拋光。 4. 如請求項3所述之方法，其中該半導體晶圓之至少一面的拋光 係包含進行該雙面拋光及於其後進行一單面拋光。 5. 如請求項4所述之方法，包含進一步拋光該邊緣，其中係在一 含有自由研磨料之漿料的存在下、利用一不含固定研磨料之拋 光布以拋光該經拋光之半導體晶圓之經拋光邊緣。 6. 如請求項5所述之方法’其中於根據請求項1所述之拋光布之 固定研磨料之目數（mesh )為1 〇〇〇至2000。 7. 如請求項1所述之方法’其中該拋光布之固定研磨料之目數係 不小於4000。 8. 如請求項4所述之方法，包含在拋光該邊緣之後進行該單面拋 光。 9. 如請求項5所述之方法’包含在進一步拋光該邊緣之後進行該 單面椒光。 10. 如請求項6所述之方法，包含在進一步拋光該邊緣之後進行該 單面抛光。 200921773 11. 12. 13. 14. 15. 如請求項4所述之方法，包含在拋光該邊緣之前進行該單面拋 光。 如請求項5所述之方法，包含在拋光該邊緣之前進行該單面拋 光，並且在拋光該邊緣之後進一步拋光該邊緣。 如請求項6所述之方法，包含在拋光該邊緣之前進行該單面拋 光’並且在拋光該邊緣之後進一步抛光該邊緣。 如請求項1、2及7中任-項所述之方法，包含在該具有經抛 光邊緣之半導體晶圓之經拋光面上沉積一磊晶層。 如請求項3所述之方法，包含在該具有經拋光邊緣之半導體晶 圓之經拋光面上沉積一蟲晶層。 200921773 四、指定代表圖： (一) 本案指定代表圖為：（無） (二) 本代表圖之元件符號簡單說明： (無） 五、本案若有化學式時，請揭示最能顯示發明特徵的化學式： (無）200921773 ' VII. Patent Application Range: 1. A method for manufacturing a semiconductor wafer having a polished edge, comprising: polishing at least one side of a semiconductor wafer; and polishing an edge of the polished semiconductor wafer; The edge is polished using a polishing cloth containing a fixed abrasive in the presence of a polishing agent. 2. The method of claim 1, wherein the polishing agent comprises a free abrasive. 3. The method of claim 1 or 2 wherein the polishing of at least one side of the semiconductor wafer comprises performing a double side polishing. 4. The method of claim 3, wherein the polishing of at least one side of the semiconductor wafer comprises performing the double side polishing followed by a single side polishing. 5. The method of claim 4, comprising further polishing the edge, wherein the polished semiconductor crystal is polished using a polishing cloth containing no fixed abrasive in the presence of a slurry containing free abrasive. The polished edge of the circle. 6. The method of claim 5, wherein the fixed abrasive of the polishing cloth according to claim 1 has a mesh of 1 〇〇〇 to 2000. 7. The method of claim 1, wherein the fixed abrasive of the polishing cloth has a mesh size of not less than 4,000. 8. The method of claim 4, comprising performing the one-sided polishing after polishing the edge. 9. The method of claim 5, comprising performing the single-sided pepper light after further polishing the edge. 10. The method of claim 6 comprising performing the one-sided polishing after further polishing the edge. 200921773 11. 12. 13. 14. 15. The method of claim 4, comprising performing the one-sided polishing prior to polishing the edge. The method of claim 5, comprising performing the one-sided polishing before polishing the edge, and further polishing the edge after polishing the edge. The method of claim 6 comprising performing the one-sided polishing before polishing the edge and further polishing the edge after polishing the edge. The method of any of claims 1, 2, and 7, comprising depositing an epitaxial layer on the polished surface of the semiconductor wafer having the polished edge. The method of claim 3, comprising depositing a worm layer on the polished surface of the semiconductor wafer having the polished edge. 200921773 IV. Designated representative map: (1) The representative representative of the case is: (none) (2) The symbol of the symbol of the representative figure is simple: (none) 5. If there is a chemical formula in this case, please reveal the best indication of the characteristics of the invention. Chemical formula: (none)
TW097143873A 2007-11-15 2008-11-13 Method for producing a semiconductor wafer with a polished edge TW200921773A (en)

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JP (1) JP2009124153A (en)
KR (1) KR20090050939A (en)
CN (1) CN101434047A (en)
DE (1) DE102007056122A1 (en)
SG (1) SG152978A1 (en)
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