JP2009124153A - Method for producing semiconductor wafer with polished edge part - Google Patents

Method for producing semiconductor wafer with polished edge part Download PDF

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Publication number
JP2009124153A
JP2009124153A JP2008291653A JP2008291653A JP2009124153A JP 2009124153 A JP2009124153 A JP 2009124153A JP 2008291653 A JP2008291653 A JP 2008291653A JP 2008291653 A JP2008291653 A JP 2008291653A JP 2009124153 A JP2009124153 A JP 2009124153A
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Prior art keywords
polishing
semiconductor wafer
edge
polished
abrasive grains
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Klaus Roettger
レットガー クラウス
Werner Aigner
アイグナー ヴェルナー
Makoto Tabata
誠 田畑
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Siltronic AG
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Siltronic AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/042—Lapping machines or devices; Accessories designed for working plane surfaces operating processes therefor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method capable of producing a semiconductor wafer having a polished edge part perfectly conforming to requirements relating to roughness and shape. <P>SOLUTION: This method for producing a semiconductor wafer having a polished edge includes the steps of polishing at least one side of the semiconductor wafer, and polishing the edge part of the polished semiconductor wafer, wherein the edge part is polished in the presence of a polishing agent by means of a polishing cloth containing fixed abrasive. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本特許出願はポリシングされたエッジ部を有する半導体ウェハの製造方法に関し、前記方法はエッジ部をポリシングするために固定砥粒を有する研磨布を使用することを含む。このような研磨布を用いたエッジ部のポリシングは、以後、ＦＡポリシングと省略する。   The present patent application relates to a method of manufacturing a semiconductor wafer having a polished edge portion, the method including using a polishing cloth having fixed abrasive grains to polish the edge portion. The polishing of the edge portion using such a polishing cloth is hereinafter abbreviated as FA polishing.

半導体ウェハのエッジ部の加工は次第に注目されている。所定のエッジ形状を有する平坦なエッジ部が要求される。このエッジ形状は、通常では、結晶をスライシングした半導体ウェハの粗面のエッジの研削により生じる。前記エッジ部を平坦化しかつ研削の際に残った結晶格子ダメージを除去するために、前記エッジ部はポリシングしなければならない。これは、固定砥粒を含有しない研磨布を用いて行うことができる。この場合、前記ポリシングは遊離砥粒を有するスラリーの存在で行われる。以後研磨布ポリシングと省略されるエッジ部のポリシングに対して、ＦＡポリシングは、「スラリー」の比較的手間のかかる取り扱いを不必要とし、より高い処理量を可能にするという利点を有する。この利点に対して、ポリシングされたエッジ部があまり平坦ではないという欠点が生じる。US 6,514,423 B1には、エッジ部の粗面性を低減するためにＦＡポリシングに引き続き前記エッジ部をエッチングすることが提案されている。   The processing of the edge portion of a semiconductor wafer is gradually attracting attention. A flat edge portion having a predetermined edge shape is required. This edge shape is usually generated by grinding the edge of a rough surface of a semiconductor wafer slicing a crystal. In order to flatten the edge and remove crystal lattice damage left during grinding, the edge must be polished. This can be done using a polishing cloth that does not contain fixed abrasive. In this case, the polishing is performed in the presence of a slurry having loose abrasive grains. In contrast to edge polishing, which is hereinafter abbreviated as polishing cloth polishing, FA polishing has the advantage that it does not require relatively laborious handling of the “slurry” and allows a higher throughput. The disadvantage is that the polished edge is not very flat. US Pat. No. 6,514,423 B1 proposes etching the edge portion subsequent to FA polishing in order to reduce the roughness of the edge portion.

既に述べたように、エッジ部の僅かな粗面性の他に、前記エッジ部の形状が要求を満たすことも考慮しなければならない。このことを考慮して、半導体ウェハの片面及び両面のポリシングがエッジの形状を不利に変化させないことが確認することができる。さらに、この問題は、例えばエッジ部の研磨布ポリシングが半導体ウェハの側の最初のポリシングの後に初めて予定されているUS 6,162,730に記載されているようなプロセス連鎖を選択することによっても解消できない。   As already stated, in addition to the slight roughness of the edge, it must be taken into account that the shape of the edge meets the requirements. In view of this, it can be confirmed that polishing on one and both sides of the semiconductor wafer does not adversely change the shape of the edge. Furthermore, this problem cannot be solved by selecting a process chain as described, for example, in US 6,162,730, where the edge polishing cloth polishing is scheduled for the first time after the first polishing on the side of the semiconductor wafer.

US 6,514,423 B1US 6,514,423 B1 US 6,162,730US 6,162,730

本発明の課題は、従って、ラフネス及び形状に関する要求に完全に適合する、ポリシングされたエッジ部を有する半導体ウェハの製造を可能にする方法を提供することである。   The object of the present invention is therefore to provide a method enabling the production of semiconductor wafers with polished edges, which perfectly meet the requirements regarding roughness and shape.

前記課題は、半導体ウェハの少なくとも一方の側のポリシングと、ポリシングされた半導体ウェハのエッジ部のポリシングとを有し、その際、前記エッジ部はポリシング剤の存在で、固定砥粒を有する研磨布でポリシングされる、ポリシングされたエッジ部を有する半導体ウェハの製造方法により解決される。   The object includes polishing of at least one side of a semiconductor wafer and polishing of an edge portion of the polished semiconductor wafer. At this time, the edge portion is a polishing cloth having fixed abrasive grains in the presence of a polishing agent. This is solved by a method of manufacturing a semiconductor wafer having a polished edge.

本発明は、ＦＡポリシングを用いてポリシングされた半導体ウェハのエッジ部の形状を修正することができるが、研磨布ポリシングを用いてはできないという認識を利用する。   The present invention utilizes the recognition that the shape of the edge of a semiconductor wafer polished using FA polishing can be corrected, but not polishing cloth polishing.

前記方法は、エッジ部は既に付形する加工工程、有利に研削工程にかけられているが、前記エッジ部は未だにポリシングされていない半導体ウェハに適用される。前記方法は、半導体ウェハの少なくとも一方の側のポリシングで始まる。これは片面ポリシングであるか又は両面ポリシングである。同時に実施される両面ポリシングが有利である。両面ポリシングのための適当な機械は、例えばDE100 07 390 A1に記載されている。前記ポリシングの間に、前記半導体ウェハは、ガイドケージとして機能するキャリアのこのために設けられたカットアウト部内でかつ上側のポリシングプレートと下側のポリシングプレートとの間に存在する。少なくとも一方のポリシングプレート及び前記キャリアは回転され、かつ前記半導体ウェハは供給されるポリシング剤と共に、転曲線が優勢の軌道上を研磨布で覆われたポリシングプレートに対して相対的に運動する。ポリシングプレートを半導体ウェハに押しつけるポリシング圧及びポリシング時間は、ポリシングにより生じる材料除去に決定的に関与するパラメータである。   The method is applied to a semiconductor wafer which has already been subjected to a processing step, preferably a grinding step, in which the edge portion is shaped, but the edge portion has not yet been polished. The method begins with polishing on at least one side of a semiconductor wafer. This is single-sided polishing or double-sided polishing. A double-sided polishing performed simultaneously is advantageous. A suitable machine for double-side polishing is described, for example, in DE 100 07 390 A1. During the polishing, the semiconductor wafer is present in a cutout provided for this purpose in the carrier functioning as a guide cage and between the upper polishing plate and the lower polishing plate. At least one polishing plate and the carrier are rotated, and the semiconductor wafer moves together with the supplied polishing agent relative to a polishing plate covered with a polishing cloth on a trajectory in which a rolling curve is dominant. Polishing pressure and polishing time for pressing the polishing plate against the semiconductor wafer are parameters that are critically involved in material removal caused by polishing.

この半導体ウェハの少なくとも一方の側のポリシングは、有利に除去ポリシングとして実施され、つまり前記半導体ウェハのポリシングされるべき側から少なくとも５μｍの厚さを有する材料を除去することを目的として実施される。   This polishing of at least one side of the semiconductor wafer is preferably carried out as removal polishing, i.e. for the purpose of removing material having a thickness of at least 5 μm from the side of the semiconductor wafer to be polished.

前記半導体ウェハの片面又は両面のポリシングが原因のエッジ形状の変更は、前記エッジ部のＦＡポリシングにより修正される。   The change in the edge shape caused by polishing on one or both sides of the semiconductor wafer is corrected by FA polishing of the edge portion.

ＦＡポリシングの場合に、固定砥粒、例えば炭化ケイ素、二酸化ケイ素又はダイアモンドからなる粒子を有する研磨布が使用される。一実施態様の場合に、このＦＡポリシングは液状ポリシング剤の存在で、例えば水の存在で行われる。このエッジ部の平坦化のため、つまり前記エッジ部のラフネスの低減のために、この場合、有利に４０００よりも低くないメッシュを有する、つまり５μｍより大きくない、特に有利に４μｍより大きくない平均粒径を有する特に微細な砥粒を有する研磨布が使用される。特に、その進行において次第に微細になる砥粒を用いてポリシングされ、かつ前記ポリシングは前記微細な砥粒によって終わる多段階のＦＡポリシングも適している。このようなポリシング工程順序及び適当なポリシング装置は、例えばUS2006/0252355 A1に記載されている。   In the case of FA polishing, a polishing cloth having fixed abrasive grains, for example particles made of silicon carbide, silicon dioxide or diamond, is used. In one embodiment, this FA polishing is performed in the presence of a liquid polishing agent, for example, in the presence of water. For this flattening of the edges, i.e. to reduce the roughness of the edges, in this case the average grain preferably has a mesh not lower than 4000, i.e. not larger than 5 μm, particularly preferably not larger than 4 μm. A polishing cloth having particularly fine abrasive grains having a diameter is used. In particular, multi-stage FA polishing that is polished using abrasive grains that become progressively finer and that ends with the fine abrasive grains is also suitable. Such a polishing process sequence and a suitable polishing apparatus are described, for example, in US 2006/0252355 A1.

この方法の第２の実施態様の場合に、このＦＡポリシングは遊離砥粒、例えばコロイド状の二酸化ケイ素又は酸化セリウムを有するスラリーの存在で行われる。   In the second embodiment of the method, the FA polishing is performed in the presence of a slurry having loose abrasive grains such as colloidal silicon dioxide or cerium oxide.

第３の実施態様は、まずＦＡポリシングを水性ポリシング剤の存在で実施し、引き続き遊離砥粒、例えばコロイド状の二酸化ケイ素又は酸化セリウムを有するスラリーの存在で研磨布ポリシングを実施することを有する。この場合、研磨布中の固定砥粒の平均粒径は、引き続く研磨布ポリシングを行わない場合よりも大きくすることができる。引き続き研磨布ポリシングを実施する場合に、１０００〜２０００のメッシュを有する、つまり７〜２５μｍの平均粒径を有する固定砥粒を有する研磨布の使用が、有利である。この研磨布ポリシングの時間は、１５〜３０ｓで極めて短くすることができる。   A third embodiment comprises first performing FA polishing in the presence of an aqueous polishing agent followed by polishing cloth polishing in the presence of a slurry having free abrasive grains such as colloidal silicon dioxide or cerium oxide. In this case, the average particle diameter of the fixed abrasive grains in the polishing pad can be made larger than when the subsequent polishing cloth polishing is not performed. In the subsequent polishing of the polishing cloth, it is advantageous to use a polishing cloth having a mesh of 1000 to 2000, ie having fixed abrasive grains having an average particle diameter of 7 to 25 μm. The polishing cloth polishing time can be extremely shortened to 15 to 30 seconds.

本発明による方法は、有利に片面ポリシングとして実施される半導体ウェハの前面のポリシングを有することもできる。この半導体ウェハの前面とは、半導体ウェハの、電子部材の構築のために提供される面である。引き続くＣＭＰ（化学機械研磨）といわれる片面ポリシングは、有利にできる限り平坦な端面を作成する目的を有する光沢研磨として実施される。最大で１μｍの厚さのＣＭＰの材料除去は、除去ポリシングの場合よりも明らかに少ない。前面のＣＭＰは、有利に両面ポリシングの後でかつＦＡポリシングの前又は後で実施される。   The method according to the invention can also have a polishing of the front side of the semiconductor wafer, which is advantageously performed as a single-side polishing. The front surface of the semiconductor wafer is a surface provided for the construction of the electronic member of the semiconductor wafer. Subsequent single-side polishing, referred to as CMP (Chemical Mechanical Polishing), is preferably carried out as a glossy polishing with the purpose of creating as flat an end face as possible. The material removal of CMP up to 1 μm thick is clearly less than with removal polishing. Front CMP is preferably performed after double-side polishing and before or after FA polishing.

本発明による方法は、場合により半導体ウェハの前面のエピタキシャル層の堆積も含む。   The method according to the invention optionally also includes the deposition of an epitaxial layer on the front side of the semiconductor wafer.

次の４つの工程順序ａ）〜ｄ）が特に有利である：
ａ） 両面ポリシング → ＦＡポリシング → ＣＭＰ
ｂ） 両面ポリシング → ＦＡポリシング → 研磨布ポリシング → ＣＭＰ
ｃ） 両面ポリシング → ＣＭＰ → ＦＡポリシング
ｄ） 両面ポリシング → ＣＭＰ → ＦＡポリシング → 研磨布ポリシング The following four process sequences a) to d) are particularly advantageous:
a) Double-side polishing → FA polishing → CMP
b) Double-side polishing → FA polishing → Polishing cloth polishing → CMP
c) Double-side polishing → CMP → FA polishing d) Double-side polishing → CMP → FA polishing → Polishing cloth polishing

Claims (12)

半導体ウェハの少なくとも一方の側のポリシング；
及びポリシングされた半導体ウェハのエッジ部のポリシングを有し、
その際、前記エッジ部はポリシング剤の存在で、固定砥粒を有する研磨布でポリシングされる、ポリシングされたエッジ部を有する半導体ウェハの製造方法。 Polishing at least one side of the semiconductor wafer;
And polishing the edge of the polished semiconductor wafer,
In this case, the edge portion is polished with a polishing cloth having fixed abrasive grains in the presence of a polishing agent, and a method for manufacturing a semiconductor wafer having a polished edge portion. ポリシング剤が遊離砥粒を有する、請求項１記載の方法。   The method of claim 1, wherein the polishing agent has free abrasive grains. 半導体ウェハの少なくとも一方の側のポリシングが両面ポリシングを有する、請求項１又は請求項２記載の方法。   3. A method according to claim 1 or claim 2, wherein the polishing on at least one side of the semiconductor wafer comprises double-side polishing. 半導体ウェハの少なくとも一方の側のポリシングが、両面ポリシング及びその後に実施される片面ポリシングを有する、請求項３記載の方法。   4. The method of claim 3, wherein the polishing on at least one side of the semiconductor wafer comprises double-side polishing followed by single-side polishing performed. エッジ部の更なるポリシングを有し、その際、ポリシングされた半導体ウェハのポリシングされたエッジ部は、遊離砥粒を有するスラリーの存在で、固定砥粒を有していない研磨布を用いてポリシングされる、請求項４記載の方法。   With further polishing of the edge part, the polished edge part of the polished semiconductor wafer is polished with a polishing cloth that does not have fixed abrasive grains in the presence of slurry with loose abrasive grains 5. The method of claim 4, wherein: 請求項１記載の研磨布中の固定砥粒は１０００〜２０００のメッシュを有する、請求項５記載の方法。   The method according to claim 5, wherein the fixed abrasive grains in the polishing cloth according to claim 1 have a mesh of 1000 to 2000. 研磨布中の固定砥粒は４０００よりも低くないメッシュを有する、請求項１記載の方法。   The method of claim 1, wherein the fixed abrasive grains in the polishing cloth have a mesh not lower than 4000. エッジ部のポリシングの後に実施される片面ポリシングを有する、請求項４記載の方法。   5. The method of claim 4, comprising single-side polishing performed after edge polishing. エッジ部の更なるポリシングの後に実施される片面ポリシングを有する、請求項５又は請求項６記載の方法。   7. A method according to claim 5 or claim 6, comprising single-side polishing performed after further polishing of the edge. エッジ部のポリシングの前に実施される片面ポリシングを有する、請求項４記載の方法。   5. The method according to claim 4, comprising a single-side polishing performed before the edge polishing. エッジ部のポリシングの前に実施される片面ポリシングと、前記エッジ部のポリシングの後に実施される前記エッジ部の更なるポリシングとを有する、請求項５又は請求項６記載の方法。   7. The method according to claim 5 or 6, comprising single-side polishing performed before edge polishing and further polishing of the edge performed after polishing of the edge. ポリシングされたエッジ部を有する半導体ウェハのポリシングされた側のエピタキシャル層の堆積を有する、請求項１から１１までのいずれか１項記載の方法。   The method according to claim 1, comprising depositing an epitaxial layer on the polished side of a semiconductor wafer having a polished edge.
JP2008291653A 2007-11-15 2008-11-14 Method for producing semiconductor wafer with polished edge part Withdrawn JP2009124153A (en)

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JP2011009736A (en) * 2009-06-24 2011-01-13 Siltronic Ag Method of polishing edge of semiconductor wafer
JP2011009746A (en) * 2009-06-24 2011-01-13 Siltronic Ag Method of manufacturing epitaxially coated semiconductor wafer
JP2012009550A (en) * 2010-06-23 2012-01-12 Disco Abrasive Syst Ltd Wafer processing method
JP2012019126A (en) * 2010-07-09 2012-01-26 Disco Abrasive Syst Ltd Wafer processing method

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JP2010162624A (en) * 2009-01-13 2010-07-29 Ebara Corp Polishing device and method
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