CN104526493A - Monocrystalline silicon wafer edge polishing technology - Google Patents

Monocrystalline silicon wafer edge polishing technology Download PDF

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Publication number
CN104526493A
CN104526493A CN201410660052.1A CN201410660052A CN104526493A CN 104526493 A CN104526493 A CN 104526493A CN 201410660052 A CN201410660052 A CN 201410660052A CN 104526493 A CN104526493 A CN 104526493A
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Prior art keywords
silicon wafer
polishing
plane
cleaning
edge
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CN201410660052.1A
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Chinese (zh)
Inventor
孙晨光
魏艳军
罗翀
武卫
吕莹
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Tianjin Zhonghuan Semiconductor Joint Stock Co Ltd
Tianjin Zhonghuan Advanced Material Technology Co Ltd
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Tianjin Zhonghuan Semiconductor Joint Stock Co Ltd
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Priority to CN201410660052.1A priority Critical patent/CN104526493A/en
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B9/00—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor
    • B24B9/02—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground
    • B24B9/06—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain
    • B24B9/065—Machines or devices designed for grinding edges or bevels on work or for removing burrs; Accessories therefor characterised by a special design with respect to properties of materials specific to articles to be ground of non-metallic inorganic material, e.g. stone, ceramics, porcelain of thin, brittle parts, e.g. semiconductors, wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/02—Lapping machines or devices; Accessories designed for working surfaces of revolution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02021—Edge treatment, chamfering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02082—Cleaning product to be cleaned
    • H01L21/02087—Cleaning of wafer edges

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)

Abstract

The invention provides a monocrystalline silicon wafer edge polishing technology, which is a silicon wafer edge polishing technology obtained by combing a chemical-mechanical polishing process and the characteristics of a silicon wafer edge. During the process of the technology, different polishing processes need to be conducted according to different chamfer angles, different reference surface and other parameters of a silicon wafer; and mechanical action strength and chemical action strength are matched well during the polishing processes so as to achieve the purpose of a smooth edge.

Description

A kind of monocrystalline silicon wafer crystal sheet edge polishing process
Technical field
The invention relates to the edge polishing process technology of single crystal silicon semiconductor polishing wafer sheet, especially a kind of monocrystalline silicon wafer crystal sheet edge polishing process.
Background technology
Chemically mechanical polishing (CMP) is acquisition semiconductor material surface planarizing technique the most general at present.It is the technique that mechanical friction and chemical attack combine, and has taken into account both advantages, can obtain more perfect polishing crystal surface.In recent years, semiconductor technology is towards the silicon polished future development of large scale, and also the roughness on effects on surface granularity, geometric parameter, edge and surface proposes stricter requirement simultaneously.Edge polishing is also chemically mechanical polishing, after edge polishing, the damage layer of silicon chip edge can equally be removed in image surface polishing, obtain smooth silicon chip edge, the following aspects of silicon chip can be made to be significantly improved: defect (3) that (1) prevents edge break (2) from preventing thermal stress from causing increases epitaxial layer and the photoresist flatness at silicon chip edge.
Summary of the invention
What the invention will solve is that after conventional chemical-mechanical polishing, sample edge roughness is high, the problem serious to sample damage itself.
For solving the problems of the technologies described above, the technical scheme that the invention adopts is: a kind of monocrystalline silicon wafer crystal sheet edge polishing process, and its processing step is:
(1) select angle after chamfering to be the silicon wafer of 11 ° ~ 22 °, the silicon wafer chosen is uploaded to the centering unit on edge polishing equipment by manipulator, described centering unit utilizes optical signal to scan determination and the centering of carrying out the plane of reference;
(2) plane of reference polishing is carried out according to the silicon wafer determining reference plane position in step (1), carry out between silicon wafer and polishing cloth in polishing process rubbing and impose the pressure of 15-50N, polishing time is t1 (0<t1≤8s);
(3) silicon wafer completing plane of reference polishing in step (2) is carried out end face polishing, in process, silicon wafer is fixed on sucker, and rotate under the rotating speed of 500-2500r/min with sucker, the frock of carrying out polishing corresponding with sucker moves up and down simultaneously, carry out between silicon wafer and polishing cloth in process rubbing and impose the pressure of 5-30N, polishing time is t2 (0<t2≤25s), chamfer angle is that the silicon wafer of 11 ° is than the long processing time 3-8s of the silicon wafer of chamfer angle 22 °, the little 5-10N of tonnage,
(4) use flowing pure water tentatively to clean to the silicon wafer completing end face polishing in step (3), scavenging period is 15-25s, and after cleaning, manipulator is automatically collected silicon wafer and put into download basket;
(5) complete the silicon wafer of preliminary cleaning in download step (4), use transmission waterwheel that it is passed to cleaning machine in time, use alkaline cleaning fluid to clean.
Described reference plane position is divided into OF (the flat limit plane of reference), NOTCH (the V-type groove plane of reference) and edge without the plane of reference according to shape.
Preferably, when arranging the plane of reference polishing process of step (2), making the anglec of rotation of silicon wafer reduce along with the increase of silicon wafer self chamfer angle, often reducing the anglec of rotation that 1 ° of chamfer angle then increases 2-3 °.
Cleaning method in described step (5) in cleaning agent carries out 1-3 cleaning for using SC-1 cleaning fluid to silicon wafer, each rinse bath scavenging period is 3-10min, cleaning temperature is 30-70 DEG C, afterwards silicon wafer is carried out rinsing in pure water groove, finally obtain the silicon wafer that polishing completes.
Described SC-1 cleaning fluid be by ammoniacal liquor, hydrogen peroxide and water according to ammoniacal liquor: hydrogen peroxide: water=(1-2): (1-2): the concentration ratio of (4-6) mixes.
The advantage that the invention has and good effect are: the present invention is the edge polishing process of the silicon wafer drawn in conjunction with the process of chemically mechanical polishing and the characteristic of silicon chip edge, process need carries out different polishing process according to parameters such as the different chamfer angles of silicon wafer, the different plane of references, in polishing process, mechanism strength chemical action intensity should carry out matched well, thus obtains the object at smooth edge.
Accompanying drawing explanation
Fig. 1 is the edge contour schematic diagram of silicon wafer;
Fig. 2 is the V-type groove location profile schematic diagram of silicon wafer;
Fig. 3 be silicon wafer partially polished after microscope under contrast photo;
Fig. 4 is the microphotograph of the edge roughness of silicon wafer;
Fig. 5 is the microphotograph of the edge roughness details of silicon wafer.
In figure: 1, end face polishing module 1,2, end face polishing module 2,3, end face lower surface polishing module, 4, end face upper surface polishing module, 5, silicon wafer.
Detailed description of the invention
Experiment material: 8 inches of zone melting and refining silicon wafers, resistivity is 320 ± 8% Ω cm, and thickness is 740 ± 5um, and chamfer angle is 22 °, plane of reference type be OF (the flat limit plane of reference), NOTCH (the V-type groove plane of reference) or edge without the plane of reference, quantity is 100.
Process equipment: edge polishing system, JAC cleaning machine one, transmits waterwheel, Keyemce laser microscope, Silicon Wafer polished silicon wafer edge contour instrument.
Auxiliary material: polishing pad, edge polishing liquid, pure water, PFA sheet basket.
Concrete implementation step is as follows:
(1) locate: select chamfer angle to be the silicon wafer of θ, the silicon wafer chosen is uploaded to the centering unit on edge polishing equipment by manipulator, described centering unit utilizes optical signal to scan determination and the centering of carrying out the plane of reference;
(2) plane of reference polishing: carry out plane of reference polishing to the silicon wafer determining reference plane position in step (1), carries out between silicon wafer and polishing cloth in polishing process rubbing and imposing F 1pressure, polishing time is t 1, the anglec of rotation of silicon wafer is set to P;
(3) end face polishing: the silicon wafer completing plane of reference polishing in step (2) is carried out end face polishing, in process, silicon wafer is fixed on sucker, and rotate under rotating speed S with sucker, simultaneously the frock of carrying out polishing corresponding with sucker moves up and down, and carries out rubbing and press that (wherein end face polishing module 1 exerts a force F in process between silicon wafer and polishing cloth 21, end face polishing module 2 exerts a force F 22, end face lower surface polishing module force F 23, end face upper surface polishing module force F 24), polishing time is t 2;
(4) tentatively clean: use flowing pure water tentatively to clean to the silicon wafer completing end face polishing in step (3), scavenging period is t 3, after cleaning, manipulator is automatically collected silicon wafer and is put into download basket;
(5) recovery is cleaned again: the silicon wafer completing preliminary cleaning in download step (4), and use transmission waterwheel that it is passed to cleaning machine in time, be placed in rinse bath, serviceability temperature is T 1, concentration proportioning is that the SC-1 cleaning fluid of Q cleans silicon wafer, and each rinse bath scavenging period is t 4, afterwards silicon wafer is carried out rinsing in pure water groove, finally obtains the silicon wafer that polishing completes.
Embodiment
Adopt above-mentioned experiment material to carry out embodiment analysis, parameter is as shown in the table:
Embodiment 1 2 3 4
θ(°) 11 16 22 22
The plane of reference OF Nothing NOTCH NOTCH
F 1(N) 20 25 27 12
t 1(s) 3 5 7 3
P(°) 15 20 35 35
S(r/min) 700 1200 2500 700
F 21(N) 9 15 27 27
F 22(N) 9 15 27 27
F 23(N) 3 9 12 12
F 24(N) 3 9 12 12
t 2(s) 26 22 20 0.5
t 3(s) 17 20 23 23
T 1(℃) 45 65 50 50
Q 1:1:5 1:1:4 1:2:5 1:1:5
t 4(min) 7 6 5 5
Results and analysis:
In embodiment 1, before and after polishing, the contrast of silicon wafer edge parameters is as shown in the table:
Parameter A1 A2 B1 B2 R T1 T2
Before polishing 459.9 447 470.5 464.1 440 21.214 21.382
After polishing 460.2 450.1 471.5 465.7 439.7 21.196 21.264
In embodiment 1, before and after polishing, V-type groove location parameter comparison sees the following form:
Parameter D W P1 P2 LR RR BR Th
Before polishing 1.047 3.136 1.904 3.051 0.984 0.659 1.066 88.987
After polishing 1.041 3.137 1.901 3.041 0.949 0.646 1.064 88.944
In embodiment 2, before and after polishing, silicon wafer edge parameters contrasts as following table:
Parameter A1 A2 B1 B2 R T1 T2
Before polishing 470.9 449 472.5 466.1 442 23.214 23.382
After polishing 471.2 452.1 473.5 467.7 442.7 23.196 23.264
In embodiment 2, before and after polishing, V-type groove location parameter comparison sees the following form:
Parameter D W P1 P2 LR RR BR Th
Before polishing 1.147 3.236 2.004 3.151 1.084 0.759 1.166 89.987
After polishing 1.141 3.237 2.001 3.141 1.049 0.746 1.164 89.944
In embodiment 3, before and after polishing, silicon wafer edge parameters contrasts as following table:
Parameter A1 A2 B1 B2 R T1 T2
Before polishing 469.9 448 471.5 465.1 441 22.214 22.382
After polishing 470.2 451.1 472.5 466.7 440.7 22.196 22.264
In embodiment 3, before and after polishing, V-type groove location parameter comparison sees the following form:
Parameter D W P1 P2 LR RR BR Th
Before polishing 1.147 3.236 2.004 3.151 1.084 0.759 1.166 89.987
After polishing 1.141 3.237 2.001 3.141 1.049 0.746 1.164 89.944
In embodiment 4, before and after polishing, silicon wafer edge parameters contrasts as following table:
Parameter A1 A2 B1 B2 R T1 T2
Before polishing 469.9 448 471.5 465.1 441 22.214 22.382
After polishing 470.2 451.1 472.5 466.7 440.7 22.196 22.264
In embodiment 4, before and after polishing, V-type groove location parameter comparison sees the following form:
Parameter D W P1 P2 LR RR BR Th
Before polishing 1.147 3.236 2.004 3.151 1.084 0.759 1.166 89.987
After polishing 1.141 3.237 2.001 3.141 1.049 0.746 1.164 89.944
Meaning of parameters in above-mentioned list is as follows: A1, A2 are that silicon wafer edge width is long, and R is minimum profile curvature radius, the thickness of the suitable silicon wafer of B1 and B2, and T1, T2 are silicon wafer edge chamfer angle; D is the Notch degree of depth, and W is Notch width, and P1+D=P2, LR, RR are shoulder arcs half, and BR is end arc radius, and Th is Notch angle.
As can be seen from Figure 4, before and after polishing, the roughness of silicon wafer obtains obvious improvement, the edge roughness of silicon wafer is less as can be seen from Figure 5, as can be seen from the result of 4 groups of embodiments, undertaken before and after polishing by this method, the numerical value of each parameter is basically identical, and do not occur large change, effect is better.This illustrates and utilizes this method polishing silicon wafer out meeting under the prerequisite that semiconductor material surface planarization is greatly improved, also ensure that the integrality at silicon wafer edge, is a kind of finishing method being directed to the higher silicon wafer of production surface smoothness preferably.
Above the embodiment of the invention has been described in detail, but described content being only the preferred embodiment of the invention, can not being considered to for limiting practical range of the present invention.All equalizations done according to the invention scope change and improve, and all should still belong within this patent covering scope.

Claims (5)

1. a monocrystalline silicon wafer crystal sheet edge polishing process, is characterized in that, processing step is:
(1) select the silicon wafer after chamfering, the silicon wafer chosen is uploaded to the centering unit on edge polishing equipment by manipulator, described centering unit utilizes optical signal to scan determination and the centering of carrying out the plane of reference;
(2) carry out plane of reference polishing according to the silicon wafer determining reference plane position in step (1), carry out between silicon wafer and polishing cloth in polishing process rubbing and impose the pressure of 15-50N, polishing time is t 1(0<t 1≤ 8s);
(3) silicon wafer completing plane of reference polishing in step (2) is carried out end face polishing, in process, silicon wafer is fixed on sucker, and rotate under the rotating speed of 500-2500r/min with sucker, the frock of carrying out polishing corresponding with sucker moves up and down simultaneously, carry out between silicon wafer and polishing cloth in process rubbing and impose the pressure of 5-30N, polishing time is t 2(0<t 2≤ 25s);
(4) use flowing pure water tentatively to clean to the silicon wafer completing end face polishing in step (3), scavenging period is 15-25s, and after cleaning, manipulator is automatically collected silicon wafer and put into download basket;
(5) complete the silicon wafer of preliminary cleaning in download step (4), use transmission waterwheel that it is passed to cleaning machine in time, use alkaline cleaning fluid to clean.
2. a kind of monocrystalline silicon wafer crystal sheet edge polishing process according to claim 1, is characterized in that: described reference plane position is divided into the flat limit plane of reference, the V-type groove plane of reference and edge without the plane of reference according to shape.
3. a kind of monocrystalline silicon wafer crystal sheet edge polishing process according to claim 1, it is characterized in that: in the plane of reference polishing process in step (2), the anglec of rotation of silicon wafer reduces along with the increase of silicon wafer self chamfer angle, often reduces the anglec of rotation that 1 ° of chamfer angle then increases 2-3 °.
4. a kind of monocrystalline silicon wafer crystal sheet edge polishing process according to claim 1, it is characterized in that: the cleaning method in described step (5) in cleaning agent carries out 1-3 cleaning for using SC-1 cleaning fluid to silicon wafer, each rinse bath scavenging period is 3-10min, cleaning temperature is 30-70 DEG C, afterwards silicon wafer is carried out rinsing in pure water groove, finally obtain the silicon wafer that polishing completes.
5. a kind of monocrystalline silicon wafer crystal sheet edge polishing process according to claim 4, is characterized in that: described SC-1 cleaning fluid be by ammoniacal liquor, hydrogen peroxide and water according to ammoniacal liquor: hydrogen peroxide: water=(1-2): (1-2): the concentration ratio of (4-6) mixes.
CN201410660052.1A 2014-11-18 2014-11-18 Monocrystalline silicon wafer edge polishing technology Pending CN104526493A (en)

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Cited By (11)

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Publication number Priority date Publication date Assignee Title
CN105345605A (en) * 2015-09-25 2016-02-24 广东先导半导体材料有限公司 Wafer edge polishing method and edge polishing machine suction cup
CN109623554A (en) * 2019-01-08 2019-04-16 天津中环领先材料技术有限公司 A kind of side throwing technique reducing silicon chip edge roughness
CN109822419A (en) * 2019-03-04 2019-05-31 天通日进精密技术有限公司 Wafer transfer device and wafer transfer method
CN109894962A (en) * 2017-12-07 2019-06-18 有研半导体材料有限公司 A kind of silicon chip edge polishing process
CN110587428A (en) * 2019-10-09 2019-12-20 青岛高测科技股份有限公司 Device and method for calibrating center of Notch groove formed in semiconductor crystal bar
CN110802502A (en) * 2019-11-12 2020-02-18 西安奕斯伟硅片技术有限公司 Edge grinding equipment
CN111761419A (en) * 2020-06-11 2020-10-13 上海新欣晶圆半导体科技有限公司 Adhesive tape grinding process for repairing edge damage of wafer
CN112872921A (en) * 2021-03-17 2021-06-01 天津中环领先材料技术有限公司 Polishing method for improving flatness of wafer edge
CN112967922A (en) * 2019-12-12 2021-06-15 有研半导体材料有限公司 Process method for processing 12-inch silicon polished wafer
CN114300339A (en) * 2021-12-09 2022-04-08 山东有研艾斯半导体材料有限公司 Edge polishing process for improving R-shaped profile of silicon wafer
TWI798716B (en) * 2021-06-09 2023-04-11 合晶科技股份有限公司 Method for processing a substrate and the transistor structure formed on the substrate

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Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105345605A (en) * 2015-09-25 2016-02-24 广东先导半导体材料有限公司 Wafer edge polishing method and edge polishing machine suction cup
CN109894962B (en) * 2017-12-07 2020-04-17 有研半导体材料有限公司 Silicon wafer edge polishing process
CN109894962A (en) * 2017-12-07 2019-06-18 有研半导体材料有限公司 A kind of silicon chip edge polishing process
CN109623554A (en) * 2019-01-08 2019-04-16 天津中环领先材料技术有限公司 A kind of side throwing technique reducing silicon chip edge roughness
CN109822419A (en) * 2019-03-04 2019-05-31 天通日进精密技术有限公司 Wafer transfer device and wafer transfer method
CN110587428A (en) * 2019-10-09 2019-12-20 青岛高测科技股份有限公司 Device and method for calibrating center of Notch groove formed in semiconductor crystal bar
CN110802502A (en) * 2019-11-12 2020-02-18 西安奕斯伟硅片技术有限公司 Edge grinding equipment
CN112967922A (en) * 2019-12-12 2021-06-15 有研半导体材料有限公司 Process method for processing 12-inch silicon polished wafer
CN111761419A (en) * 2020-06-11 2020-10-13 上海新欣晶圆半导体科技有限公司 Adhesive tape grinding process for repairing edge damage of wafer
CN111761419B (en) * 2020-06-11 2021-10-15 上海中欣晶圆半导体科技有限公司 Adhesive tape grinding process for repairing edge damage of wafer
CN112872921A (en) * 2021-03-17 2021-06-01 天津中环领先材料技术有限公司 Polishing method for improving flatness of wafer edge
CN112872921B (en) * 2021-03-17 2022-08-23 天津中环领先材料技术有限公司 Polishing method for improving flatness of wafer edge
TWI798716B (en) * 2021-06-09 2023-04-11 合晶科技股份有限公司 Method for processing a substrate and the transistor structure formed on the substrate
CN114300339A (en) * 2021-12-09 2022-04-08 山东有研艾斯半导体材料有限公司 Edge polishing process for improving R-shaped profile of silicon wafer

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