TWI596668B - Method for polishing semiconductor wafer - Google Patents
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- TWI596668B TWI596668B TW106114155A TW106114155A TWI596668B TW I596668 B TWI596668 B TW I596668B TW 106114155 A TW106114155 A TW 106114155A TW 106114155 A TW106114155 A TW 106114155A TW I596668 B TWI596668 B TW I596668B
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- 239000004065 semiconductor Substances 0.000 title claims description 81
- 238000005498 polishing Methods 0.000 title claims description 64
- 238000000034 method Methods 0.000 title claims description 26
- 238000004140 cleaning Methods 0.000 claims description 67
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 20
- 239000008367 deionised water Substances 0.000 claims description 15
- 229910021641 deionized water Inorganic materials 0.000 claims description 15
- 239000000126 substance Substances 0.000 claims description 12
- 238000007517 polishing process Methods 0.000 claims description 11
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 8
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 7
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- 238000005406 washing Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 95
- 230000007547 defect Effects 0.000 description 7
- 239000012535 impurity Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Cleaning Or Drying Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
本發明係關於半導體製造技術領域，尤其係關於一種半導體晶圓的拋光方法。 The present invention relates to the field of semiconductor manufacturing technology, and more particularly to a method of polishing a semiconductor wafer.
半導體製造方法中，晶圓的拋光通常需要經過如下幾個步驟： In semiconductor manufacturing methods, wafer polishing usually requires the following steps:
1、雙面拋光，即同時對晶圓的正反兩面進行拋光。 1. Double-sided polishing, that is, polishing both sides of the wafer at the same time.
2、邊緣拋光，即對晶圓的邊緣部分進行局部的鏡面拋光。 2. Edge polishing, that is, partial mirror polishing of the edge portion of the wafer.
3、最終拋光，即對晶圓的正面或正反兩面進行鏡面拋光，直徑在300mm以上的晶圓通常只對正面進行最終的鏡面拋光。 3. Final polishing, that is, mirror polishing of the front side or the front and back sides of the wafer, and the wafer having a diameter of 300 mm or more usually only performs final mirror polishing on the front side.
步驟2通常是在步驟1之後進行，用於去除步驟1可能造成的晶圓邊緣損傷。在步驟2中，拋光墊不僅與晶圓的邊緣接觸，常常還會與晶圓表面靠近邊緣的區域接觸，從而造成對晶圓表面靠近邊緣的部分“過度拋光”。這種過度拋光會影響在晶圓上進行IC製造的產品良率，在被過度拋光的晶圓邊緣附近會出現更多的失效裸芯。 Step 2 is typically performed after step 1 to remove wafer edge damage that may result from step 1. In step 2, the polishing pad not only contacts the edge of the wafer, but often also contacts the area of the wafer surface near the edge, causing "over-polished" portions of the wafer surface near the edge. This over-polishing can affect the yield of the IC on the wafer, and more failed die near the edge of the over-polished wafer.
專利文獻JP2006237055A提供了一種解決方法：在雙面拋光後，利用一種樹脂保護膜覆蓋晶圓正反兩面，從而可避免在邊緣拋光時對晶圓表面靠近邊緣的部分過度拋光。然而，這種方法成本較高，技術上的 實現也比較困難。 The patent document JP2006237055A provides a solution for covering the front and back sides of the wafer with a resin protective film after double-sided polishing, thereby avoiding over-polishing of the portion of the wafer surface near the edge during edge polishing. However, this method is costly and technically Implementation is also more difficult.
因此，實有必要提供一種經濟實用、易於實現的半導體晶圓拋光方法，以解決上述晶圓邊緣區域“過度拋光”的問題。 Therefore, it is necessary to provide an economical and practical, easy to implement semiconductor wafer polishing method to solve the problem of "over-polishing" of the wafer edge region.
鑒於以上所述現有技術，本發明的目的在於提供一種半導體晶圓的拋光方法，用於解決現有技術中晶圓拋光時邊緣區域容易被過度拋光的問題。 In view of the above prior art, it is an object of the present invention to provide a method for polishing a semiconductor wafer for solving the problem that the edge region is easily over-polished in wafer polishing in the prior art.
為實現上述目的及其他相關目的，本發明提供一種半導體晶圓的拋光方法，依次包括如下步驟：S1同時對半導體晶圓的正反兩面進行初步拋光；S2對所述半導體晶圓進行第一濕法清洗，同時在所述半導體晶圓的正反兩面形成氧化層；S3對所述半導體晶圓的邊緣部分進行鏡面拋光；S4對所述半導體晶圓進行第二濕法清洗，同時去除覆蓋在所述半導體晶圓上的氧化層；S5對所述半導體晶圓的正面或正反兩面進行鏡面拋光。 To achieve the above and other related objects, the present invention provides a method for polishing a semiconductor wafer, which in turn includes the steps of: S1 simultaneously performing preliminary polishing on both sides of the semiconductor wafer; S2 performing first wet on the semiconductor wafer Cleaning, while forming an oxide layer on both sides of the semiconductor wafer; S3 mirror polishing the edge portion of the semiconductor wafer; S4 performing a second wet cleaning on the semiconductor wafer while removing the An oxide layer on the semiconductor wafer; S5 mirror-polished the front side or the front and back sides of the semiconductor wafer.
較佳地，步驟S1採用化學機械反應的方法進行初步拋光。 Preferably, step S1 is subjected to preliminary polishing by a chemical mechanical reaction method.
較佳地，步驟S2中，所述第一濕法清洗採用氨水和雙氧水的混合液進行。 Preferably, in the step S2, the first wet cleaning is performed by using a mixed solution of ammonia water and hydrogen peroxide.
較佳地，步驟S2中，在所述第一濕法清洗之前和之後，採用去離子水對所述半導體晶圓進行清洗。 Preferably, in step S2, the semiconductor wafer is cleaned with deionized water before and after the first wet cleaning.
較佳地，步驟S2後，對所述半導體晶圓進行乾燥。 Preferably, after the step S2, the semiconductor wafer is dried.
較佳地，步驟S2中，在所述第一濕法清洗之前，採用氫氟酸清洗所述半導體晶圓。 Preferably, in step S2, the semiconductor wafer is washed with hydrofluoric acid before the first wet cleaning.
較佳地，步驟S2中，在所述第一濕法清洗之後，採用臭氧水清洗所述半導體晶圓。 Preferably, in step S2, after the first wet cleaning, the semiconductor wafer is washed with ozone water.
較佳地，步驟S2中形成的氧化層的厚度為0.3~3奈米(nm)。 Preferably, the thickness of the oxide layer formed in step S2 is 0.3 to 3 nanometers (nm).
較佳地，步驟S3中，採用化學機械反應的方法進行鏡面拋光。 Preferably, in step S3, mirror polishing is performed by a chemical mechanical reaction method.
較佳地，步驟S4中，所述第二濕法清洗依次包括步驟：採用氨水和雙氧水的混合液進行清洗、採用鹽酸和雙氧水的混合液進行清洗、以及採用稀釋的氫氟酸進行清洗。 Preferably, in the step S4, the second wet cleaning comprises the steps of: washing with a mixture of ammonia water and hydrogen peroxide, washing with a mixture of hydrochloric acid and hydrogen peroxide, and washing with diluted hydrofluoric acid.
更佳地，步驟S4中，在所述第二濕法清洗的每個步驟之前和之後，採用去離子水對所述半導體晶圓進行清洗。 More preferably, in step S4, the semiconductor wafer is cleaned with deionized water before and after each step of the second wet cleaning.
較佳地，步驟S4後，對所述半導體晶圓進行乾燥。 Preferably, after the step S4, the semiconductor wafer is dried.
較佳地，步驟S5中，採用化學機械反應的方法分多步進行鏡面拋光。 Preferably, in step S5, the mirror polishing is performed in multiple steps by a chemical mechanical reaction method.
如上所述，本發明的半導體晶圓的拋光方法，具有以下有益效果：本發明在半導體晶圓進行邊緣拋光之前進行清洗並形成氧化層，保護了晶圓表面靠近邊緣的部分，避免了該部分在晶圓邊緣拋光步驟中被過度拋光；在晶圓邊緣拋光之後、最終鏡面拋光之前對晶圓進行清洗並去除氧化層，由於邊緣拋光後留在晶圓表面的金屬雜質可以隨著氧化層一併被去除，因此可以實現晶圓表面更為有效的金屬清潔，清洗後晶圓 表面沒有額外的材料、雜質和缺陷，有利於提高後續鏡面拋光的效率和平整度。此外，本發明還具有方法簡單、經濟實用等優點。 As described above, the polishing method of the semiconductor wafer of the present invention has the following advantageous effects: the present invention cleans and forms an oxide layer before the edge polishing of the semiconductor wafer, and protects the portion of the wafer surface near the edge, thereby avoiding the portion. Over-polishing in the wafer edge polishing step; cleaning the wafer and removing the oxide layer after polishing the edge of the wafer, before final mirror polishing, metal impurities remaining on the surface of the wafer after edge polishing may follow the oxide layer And removed, so that more efficient metal cleaning of the wafer surface can be achieved. There are no additional materials, impurities and defects on the surface, which is beneficial to improve the efficiency and flatness of subsequent mirror polishing. In addition, the invention has the advantages of simple method, economical utility and the like.
S1-S5、S401-S403‧‧‧步驟 S1-S5, S401-S403‧‧‧ steps
第1圖係表示本發明的半導體晶圓的拋光方法的流程示意圖。 Fig. 1 is a flow chart showing a polishing method of a semiconductor wafer of the present invention.
第2圖係表示，依據本發明之一實施例，第二濕法清洗的流程示意圖。 Figure 2 is a schematic view showing the flow of the second wet cleaning according to an embodiment of the present invention.
以下結合圖式和具體實施例對本發明進一步詳細說明。根據本案說明書及申請專利範圍，本發明的優點及特徵將更清楚。需說明的是，圖式均採用非常簡化的形式，且均使用非精準的比例，僅用以方便、明晰地輔助說明本發明實施例的目的。 The invention is further described in detail below in conjunction with the drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the description and claims. It should be noted that the drawings are all in a very simplified form, and both use non-precise proportions, and are only for convenience and clarity to assist the purpose of the embodiments of the present invention.
實施例 Example
請參閱第1圖，本發明提供一種半導體晶圓的拋光方法，依次包括如下步驟：S1同時對半導體晶圓的正反兩面進行初步拋光；S2對所述半導體晶圓進行第一濕法清洗，並在所述半導體晶圓的正反兩面形成氧化層；S3對所述半導體晶圓的邊緣部分進行鏡面拋光；S4對所述半導體晶圓進行第二濕法清洗，同時去除覆蓋在所述半導體晶圓上的氧化層；S5對所述半導體晶圓的正面或正反兩面進行鏡面拋光。 Referring to FIG. 1 , the present invention provides a method for polishing a semiconductor wafer, which in turn includes the steps of: S1 simultaneously performing preliminary polishing on both front and back sides of the semiconductor wafer; and S2 performing first wet cleaning on the semiconductor wafer. And forming an oxide layer on the front and back sides of the semiconductor wafer; S3 mirror-finishing the edge portion of the semiconductor wafer; S4 performing a second wet cleaning on the semiconductor wafer while removing the semiconductor overlying the semiconductor wafer An oxide layer on the wafer; S5 mirror-polished the front side or the front and back sides of the semiconductor wafer.
本發明在半導體晶圓進行邊緣拋光之前進行清洗並形成氧化層，可以保護晶圓表面靠近邊緣的區域，避免了該區域在晶圓邊緣拋光步驟中被過度拋光。其中，所述半導體晶圓可以是6英寸、8英寸、12英寸、18英寸或更大尺寸的晶圓。 The present invention cleans and forms an oxide layer prior to edge polishing of the semiconductor wafer, which protects the area of the wafer surface near the edge, preventing the area from being over-polished during the wafer edge polishing step. Wherein, the semiconductor wafer may be a 6 inch, 8 inch, 12 inch, 18 inch or larger wafer.
具體地，步驟S1較佳係採用化學機械反應的方法同時對半導體晶圓的正反兩面進行初步拋光。採用化學機械反應的方法進行初步拋光，可以保證晶圓的平整度，改善晶圓背面的粗糙度，去除晶圓表面由於前序方法產生的缺陷。該步驟可以同時對多片晶圓進行，例如，可同時對2-50片晶圓進行初步拋光。 Specifically, step S1 preferably uses a chemical mechanical reaction method to simultaneously perform preliminary polishing on both sides of the semiconductor wafer. Preliminary polishing using a chemical mechanical reaction method can ensure the flatness of the wafer, improve the roughness of the back side of the wafer, and remove the defects of the wafer surface due to the pre-order method. This step can be performed on multiple wafers at the same time, for example, preliminary polishing of 2-50 wafers simultaneously.
具體地，步驟S2用於去除前序初步拋光產生的殘留在晶圓上的研磨漿和缺陷，並在晶圓的整個表面，包括正面和反面，形成氧化層。其中，所述第一濕法清洗較佳係採用氨水和雙氧水的混合液進行，即第一步標準清洗(standard clean 1，SC1)。SC1清洗可清潔晶圓表面，並可在晶圓表面形成氧化層。 Specifically, step S2 is for removing the slurry and defects remaining on the wafer generated by the preliminary polishing, and forming an oxide layer on the entire surface of the wafer, including the front side and the back side. Wherein, the first wet cleaning is preferably carried out by using a mixture of ammonia water and hydrogen peroxide, that is, the first standard cleaning (standard clean 1, SC1). SC1 cleaning cleans the surface of the wafer and forms an oxide layer on the surface of the wafer.
在本發明的一些實施例中，可以採用濕法檯在SC1清洗槽中進行所述第一濕法清洗。所述濕法檯可以包括一個或多個SC1清洗槽，例如，可採用具有兩個SC1清洗槽的濕法檯。 In some embodiments of the invention, the first wet cleaning may be performed in an SC1 wash tank using a wet bench. The wet station can include one or more SC1 wash tanks, for example, a wet station having two SC1 wash tanks can be employed.
在所述第一濕法清洗之前和之後，較佳地，可以採用去離子水對所述半導體晶圓進行清洗。步驟S2之後，可以對清洗的所述半導體晶圓進行乾燥。在本發明的一些實施例中，採用濕法檯的去離子水(deionized water，DIW)清洗槽進行去離子水清洗，例如可以在濕法檯的SC1清洗槽 之前和之後都設置DIW清洗槽，在將半導體晶圓從濕法檯上卸載之前，可以採用旋轉乾燥法對清洗後的半導體晶圓進行乾燥。 Preferably, the semiconductor wafer may be cleaned with deionized water before and after the first wet cleaning. After step S2, the cleaned semiconductor wafer can be dried. In some embodiments of the present invention, a deionized water (DIW) cleaning tank of a wet stage is used for deionized water cleaning, for example, an SC1 cleaning tank that can be used in a wet table. The DIW cleaning bath is provided both before and after, and the cleaned semiconductor wafer can be dried by spin drying before the semiconductor wafer is unloaded from the wet stage.
作為本發明的較佳實施例，步驟S2中，可以在所述第一濕法清洗之前，採用氫氟酸清洗所述半導體晶圓。在氫氟酸清洗和SC1清洗之間採用去離子水清洗半導體晶圓。 As a preferred embodiment of the present invention, in step S2, the semiconductor wafer may be washed with hydrofluoric acid before the first wet cleaning. The semiconductor wafer is cleaned with deionized water between hydrofluoric acid cleaning and SC1 cleaning.
作為本發明的較佳實施例，步驟S2中，在所述第一濕法清洗之後，可以採用臭氧水清洗所述半導體晶圓。臭氧水清洗用於在晶圓表面形成氧化層。SC1清洗和臭氧水清洗之間採用去離子水清洗半導體晶圓。 As a preferred embodiment of the present invention, in step S2, after the first wet cleaning, the semiconductor wafer may be cleaned with ozone water. Ozone water cleaning is used to form an oxide layer on the surface of the wafer. The semiconductor wafer is cleaned with deionized water between SC1 cleaning and ozone water cleaning.
具體地，步驟S2中形成的氧化層的厚度較佳為0.3~3nm。氧化層厚度的設計既要保證在邊緣拋光中對晶圓表面的保護效果，也要便於其在後續步驟中能被去除。 Specifically, the thickness of the oxide layer formed in step S2 is preferably 0.3 to 3 nm. The thickness of the oxide layer is designed to ensure the protection of the wafer surface during edge polishing and to be removed in subsequent steps.
具體地，步驟S3中，採用化學機械反應的方法進行邊緣拋光。該步驟用於改善邊緣粗糙度以及去除邊緣缺陷。邊緣鏡面拋光的方法在現有技術中較為成熟，故在此不作贅述。 Specifically, in step S3, edge polishing is performed by a chemical mechanical reaction method. This step is used to improve edge roughness and remove edge defects. The method of edge mirror polishing is mature in the prior art, so it will not be described here.
具體地，步驟S4用於去除邊緣拋光殘留的氧化層、研磨漿和晶圓表面的缺陷。其中，所述第二濕法清洗，如第2圖所示，較佳地，依次包括步驟：S401採用氨水和雙氧水的混合液進行清洗、S402採用鹽酸和雙氧水的混合液進行清洗、以及S403採用稀釋的氫氟酸進行清洗。 Specifically, step S4 is for removing defects of the oxide layer, the slurry, and the wafer surface remaining in the edge polishing. Wherein, the second wet cleaning, as shown in FIG. 2, preferably comprises the steps of: S401 is washed with a mixture of ammonia water and hydrogen peroxide, S402 is washed with a mixture of hydrochloric acid and hydrogen peroxide, and S403 is used. Dilute hydrofluoric acid for cleaning.
在本發明的一些實施例中，可以採用濕法檯進行所述第二濕法清洗。所述濕法檯可以包括：SC1清洗槽、SC2清洗槽和稀釋氫氟酸DHF(Diluted HF)清洗槽。其中，SC1清洗槽用於通入氨水和雙氧水的混合液進行半導體晶圓的清洗，SC1清洗槽可以有一個或多個，較佳為兩個；SC2 清洗槽設置在SC1清洗槽之後，用於通入鹽酸和雙氧水的混合液進行半導體晶圓的清洗；DHF清洗槽用於通入稀釋的氫氟酸進行清洗；DHF清洗可以在SC2清洗之後用DHF清洗槽進行，也可以在SC2清洗槽中通入稀釋的氫氟酸進行。DHF清洗用於去除氧化層，從而確保從濕法檯卸載的半導體晶圓上沒有化學氧化層，同時也有利於金屬雜質的去除。 In some embodiments of the invention, the second wet cleaning may be performed using a wet table. The wet stage may include: an SC1 cleaning tank, an SC2 cleaning tank, and a diluted hydrofluoric acid DHF (Diluted HF) cleaning tank. Wherein, the SC1 cleaning tank is used for cleaning the semiconductor wafer by introducing a mixture of ammonia water and hydrogen peroxide, and the SC1 cleaning tank may have one or more, preferably two; SC2 The cleaning tank is disposed after the SC1 cleaning tank for the cleaning of the semiconductor wafer by introducing a mixture of hydrochloric acid and hydrogen peroxide; the DHF cleaning tank is used for cleaning with diluted hydrofluoric acid; and the DHF cleaning is for DHF after SC2 cleaning. The cleaning tank can be carried out by introducing diluted hydrofluoric acid into the SC2 cleaning tank. DHF cleaning is used to remove the oxide layer, thereby ensuring that there is no chemical oxide layer on the semiconductor wafer unloaded from the wet stage, and also facilitates the removal of metal impurities.
在所述第二濕法清洗的每個步驟之前和之後，較佳地，可以採用去離子水對所述半導體晶圓進行清洗。在步驟S4之後，可以對清洗的所述半導體晶圓進行乾燥。在本發明的一些實施例中，採用濕法檯的DIW清洗槽進行去離子水清洗，例如可以在濕法檯的SC1清洗槽之前、SC1清洗槽與SC2清洗槽之間、以及SC2清洗槽之後設置多個DIW清洗槽，在將半導體晶圓從濕法檯上卸載之前，可以採用旋轉乾燥法對清洗後的半導體晶圓進行乾燥。 Preferably, the semiconductor wafer can be cleaned with deionized water before and after each step of the second wet cleaning. After the step S4, the cleaned semiconductor wafer may be dried. In some embodiments of the present invention, the DIW cleaning tank of the wet stage is used for deionized water cleaning, for example, before the SC1 cleaning tank of the wet table, between the SC1 cleaning tank and the SC2 cleaning tank, and after the SC2 cleaning tank. A plurality of DIW cleaning tanks are provided, and the cleaned semiconductor wafer can be dried by a spin drying method before the semiconductor wafer is unloaded from the wet stage.
具體地，步驟S5用於對半導體晶圓進行最終拋光，可採用化學機械反應的方法分多步進行鏡面拋光，以確保晶圓表面的平整度，改善表面粗糙度，以及去除表面缺陷。較佳地，可以分兩步進行鏡面拋光以達到方法標準。通常直徑在300mm以上的晶圓只對正面進行最終拋光。最終鏡面拋光的方法在現有技術中較為成熟，故在此不作贅述。 Specifically, step S5 is used for final polishing of the semiconductor wafer, and the mirror polishing may be performed in multiple steps by a chemical mechanical reaction method to ensure the flatness of the wafer surface, improve the surface roughness, and remove surface defects. Preferably, mirror polishing can be performed in two steps to achieve the method standard. Generally, wafers with a diameter of 300 mm or more are only final polished on the front side. The final method of mirror polishing is mature in the prior art, so it will not be described here.
由於在進行最終鏡面拋光的半導體晶圓表面沒有額外的化學氧化層，半導體材料的研磨去除率較高，並且由於在第二濕法清洗的步驟中金屬雜質連同氧化層一起被去除，最終拋光得到的半導體晶圓在表面純淨度方面的品質更高。 Since there is no additional chemical oxide layer on the surface of the final mirror polished semiconductor wafer, the polishing removal rate of the semiconductor material is high, and since the metal impurities are removed together with the oxide layer in the second wet cleaning step, the final polishing is obtained. Semiconductor wafers are of higher quality in terms of surface purity.
綜上所述，本發明在半導體晶圓進行邊緣拋光之前進行清洗並形成氧化層，保護了晶圓表面靠近邊緣的部分，避免了該部分在晶圓邊緣拋光步驟中被過度拋光；在晶圓邊緣拋光之後、最終鏡面拋光之前對晶圓進行清洗並去除氧化層，由於邊緣拋光後留在晶圓表面的金屬雜質可以隨著氧化層一併被去除，因此可以實現晶圓表面更為有效的金屬清潔，清洗後晶圓表面沒有額外的材料、雜質和缺陷，有利於提高後續鏡面拋光的效率和平整度。此外，本發明還具有方法簡單、經濟實用等優點。所以，本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。 In summary, the present invention cleans and forms an oxide layer before edge polishing of the semiconductor wafer, protecting the portion of the wafer surface near the edge, and avoiding excessive polishing of the portion during the wafer edge polishing step; After the edge is polished and before the final mirror polishing, the wafer is cleaned and the oxide layer is removed. Since the metal impurities remaining on the surface of the wafer after the edge polishing can be removed together with the oxide layer, the wafer surface can be more effectively realized. The metal is cleaned and there is no additional material, impurities and defects on the surface of the wafer after cleaning, which is beneficial to improve the efficiency and flatness of the subsequent mirror polishing. In addition, the invention has the advantages of simple method, economical utility and the like. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述特定實施例之內容係為了詳細說明本發明，然而，該等實施例係僅用於說明，並非意欲限制本發明。熟習本領域之技藝者可理解，在不悖離後附申請專利範圍所界定之範疇下針對本發明所進行之各種變化或修改係落入本發明之一部分。 The above description of the specific embodiments is intended to be illustrative of the invention, and is not intended to limit the invention. It will be understood by those skilled in the art that various changes or modifications may be made to the present invention without departing from the scope of the appended claims.
S1-S5‧‧‧步驟 S1-S5‧‧‧ steps
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| CN112635302A (en) * | 2020-12-21 | 2021-04-09 | 中环领先半导体材料有限公司 | Process for reducing polishing fragment rate of silicon wafer edge |
| CN113084598B (en) * | 2021-04-02 | 2022-04-05 | 杭州中欣晶圆半导体股份有限公司 | Cost-reducing and efficiency-improving silicon wafer edge polishing process |
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