TWI811425B - Method for manufacturing semiconductor structure - Google Patents

Abstract

A method for manufacturing a semiconductor structure includes the following steps. A gate structure is formed on a semiconductor substrate. A nitride layer is formed to cover the gate structure and the semiconductor substrate. An oxide layer is formed to cover the nitride layer. A first chemical mechanical polishing step is performed from an upper surface of the oxide layer down until the nitride layer is exposed. The first chemical mechanical polishing step has an etching rate to the oxide layer faster than an etching rate to the nitride layer. An etching step is performed, which uses an etchant applied onto the nitride layer treated with the first chemical mechanical polishing step on the gate structure. The etchant comprise phosphoric acid. A second chemical mechanical polishing step is performed from a portion of the oxide layer exposed from the etching step. The second chemical mechanical polishing step has an etching rate to the oxide layer faster than an etching rate to the nitride layer.

Description

Methods of fabricating semiconductor structures

The present invention relates to a manufacturing method of a semiconductor structure, and in particular to a manufacturing method including a chemical mechanical polishing step.

In recent years, due to the continuous changes in semiconductor structures, the number of process steps for semiconductor structures has increased accordingly, which can easily reduce the process yield of semiconductor structures. Especially when there are defects on the component surface, it is easy to cause a decrease in the yield of subsequent processes. Therefore, designers are committed to reducing defects in the semiconductor manufacturing process to improve product yield.

The present invention relates to a method for manufacturing a semiconductor structure.

According to one concept of the present disclosure, a method for manufacturing a semiconductor structure is proposed, which includes the following steps. A gate structure is formed on a semiconductor substrate. A nitride layer is formed to cover the gate structure and the semiconductor substrate. An oxide layer is formed covering the nitride layer. A first chemical mechanical polishing step, using a first polishing slurry to polish downward from an upper surface of the oxide layer until the nitride layer is exposed. The polishing rate of the first polishing slurry on the oxide layer is greater than that on the nitride layer. Grind rate. In a cleaning step, a cleaning solution is applied to the exposed portions of the nitride layer and the oxide layer after the first chemical mechanical polishing. The cleaning solution includes sulfuric acid, ammonia, hydrogen peroxide, or a combination of the above. In a second chemical mechanical polishing step, a second polishing slurry is used to polish the exposed portion of the nitride layer after the cleaning step. The polishing rate of the nitride layer by the second polishing slurry is greater than the polishing rate of the oxide layer.

According to another concept of the present disclosure, a method for manufacturing a semiconductor structure is provided, which includes the following steps. A gate structure is formed on a semiconductor substrate. A nitride layer is formed to cover the gate structure and the semiconductor substrate. An oxide layer is formed covering the nitride layer. A first chemical mechanical polishing step, grinding downward from an upper surface of the oxide layer until the nitride layer is exposed. The polishing rate of the oxide layer in the first chemical mechanical polishing step is greater than the polishing rate of the nitride layer. An etching step uses an etchant to apply to the nitride layer above the gate structure after the first chemical mechanical polishing. The etchant includes phosphoric acid. A second chemical mechanical polishing step is to polish the exposed portion of the oxide layer after the etching step. The polishing rate of the oxide layer in the second chemical mechanical polishing step is greater than the polishing rate of the nitride layer.

In order to have a better understanding of the above and other aspects of the present invention, examples are given below and are described in detail with reference to the accompanying drawings:

Below are some examples for illustration. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not proposed in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn to the same proportions as the actual product. Therefore, the description and illustrations are only used to describe the embodiments and are not used to limit the scope of the present disclosure. In addition, descriptions in the embodiments, such as detailed structures, process steps, material applications, etc., are only for illustration and do not limit the scope of the present disclosure. The details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. The following description uses the same/similar symbols to indicate the same/similar components.

First embodiment

The manufacturing method of the semiconductor structure of the first embodiment will be described with reference to FIGS. 1 to 5 .

Referring to Figure 1, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may include a silicon substrate, a silicon-on-insulator (SOI) structure, or other suitable semiconductor substrate structure. Isolation structures 104 such as shallow trench isolation devices may be formed in the semiconductor substrate 102 to define active regions such as P-type wells and N-type wells of devices (eg, N-type transistors or P-type transistors, etc.). The method of forming a transistor on the semiconductor substrate 102 includes the following steps. A gate structure G is formed on the semiconductor substrate 102 . The gate structure G may include a gate dielectric layer 106, a first material layer 108, a second material layer 110, a gate electrode 112, a hard mask layer 114, a first spacer 116 and a second spacer 118. Gate dielectric layer 106 is formed on semiconductor substrate 102 . Gate dielectric layer 106 may include an oxide such as silicon oxide, or other suitable dielectric material. A first material layer 108 may be formed on the gate dielectric layer 106 . In one embodiment, the first material layer 108 may include hafnium oxide (HfO), but is not limited thereto. The second material layer 110 may be formed on the first material layer 108 . In one embodiment, the second material layer 110 may include titanium nitride, but is not limited thereto. Gate electrode 112 may be formed on second material layer 110 . Gate electrode 112 may include polysilicon or other suitable materials. A hard mask layer 114 may be formed on the gate electrode 112 . The hard mask layer 114 may include nitride, such as silicon nitride, which may be formed by deposition, but is not limited thereto, and other suitable materials or formation methods may also be used. The first spacers 116 may be formed on side surfaces of the gate dielectric layer 106 , the first material layer 108 , the second material layer 110 , the gate electrode 112 , and the hard mask layer 114 . The first spacer 116 may include, but is not limited to, silicon carbonitride or the like. The second spacer 118 may be formed on the side surface of the first spacer 116 and may extend to the upper surface of the semiconductor substrate 102 . The second spacers 118 may include an oxide such as silicon oxide. Source/drain 120 may be formed in semiconductor substrate 102 on an opposite side of gate structure G. The source/drain 120 may include a doped region formed by doping, such as a lightly doped (LDD) or a heavily doped source/drain region, or may include a metal silicide layer formed on the surface of the doped region. For example, nickel silicide (NiSi), etc.

A nitride layer 222 is formed to cover the gate structure G, the semiconductor substrate 102 and the isolation structure 104 . Nitride layer 222 includes silicon nitride. The nitride layer 222 may be a tensile stress contact hole etch stop layer (Tensile CESL). An oxide layer 324 is formed to cover the nitride layer 222 . The oxide layer 324 may include silicon oxide, such as undoped silicone glass (USG). The oxide layer 324 is formed by, but not limited to, high density plasma chemical vapor deposition (HDP). Oxide layer 324 may include an interlayer dielectric layer. The oxide layer 324 may be a single layer or a multi-layer composite film.

Referring to FIG. 2 , a first chemical mechanical polishing step 651 is performed to polish downward from the upper surface of the oxide layer 324 until the nitride layer 222 is exposed. The first chemical mechanical polishing step 651 uses a first polishing slurry to perform polishing, and the polishing rate of the oxide layer 324 is greater than the polishing rate of the nitride layer 222 . The nitride layer 222 serves as a polish stop layer for the first chemical mechanical polishing step 651 . The first grinding slurry may include first powder particles, such as cerium dioxide powder. After the first chemical mechanical polishing step 651 is completed, the upper surface of the oxide layer 324 may be slightly concave and lower than the top surface of the nitride layer 222 .

After the first chemical mechanical polishing step 651 is completed, the material of the first polishing slurry may remain on the exposed structural surface (such as the upper surface of the nitride layer 222 and the oxide layer 324). In one embodiment, a cleaning step is performed after the first chemical mechanical polishing step 651 is completed, and the remaining substances of the first polishing slurry on the surface of the structure are removed through the cleaning step. The cleaning step can be carried out using the wet cleaning method, using a cleaning solution.

Referring to Figure 3, a second chemical mechanical polishing step 753 is then performed from the cleaned structural surface. The second chemical mechanical polishing step 753 of the first embodiment uses a second polishing slurry that is different from the first polishing slurry, and the polishing rate of the nitride layer 222 is greater than the polishing rate of the oxide layer 324 . The second chemical mechanical polishing step 753 mainly polishes the nitride layer 222 and uses the oxide layer 324 as a polishing stop layer. The second grinding slurry may include second powder particles, such as silica powder particles. The second chemical mechanical polishing step 753 can reduce the thickness of the nitride layer 222, thereby causing a smaller change in the total exposed surface of the nitride layer 222 and the oxide layer 324, which will facilitate subsequent non-selective etching ( For example, the surface flatness results of etching step 855) described in Figure 4. Since the second chemical mechanical polishing step 753 uses the oxide layer 324 as a polishing stop layer, the top surface position of the polished nitride layer 222 may be substantially equal to or slightly higher than the portion of the oxide layer 324 adjacent to the nitride layer 222 upper surface position.

In the first embodiment, a cleaning step is performed between the first chemical mechanical polishing step 651 and the second chemical mechanical polishing step 753 which are selective for grinding oxides (such as silicon oxide) and nitrides (such as silicon nitride) respectively. , wherein the cleaning step can remove the first polishing slurry material (including the first powder particles, such as cerium dioxide powder) remaining in the first chemical mechanical polishing step 651. Therefore, the second chemical mechanical polishing step 753 is performed later. The second powder particles (such as silica powder) used will not aggregate with the first powder particles (such as cerium dioxide particles) to form larger-sized particles. In this way, the particles can be prevented from scratching the device components during grinding. problem. The cleaning solution used in the cleaning step to clean the residual matter of the first polishing slurry includes sulfuric acid (H ₂ SO ₄ ), ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), or a combination of the above. For example, cleaning solutions include SPM (containing sulfuric acid, hydrogen peroxide), SC1 (containing deionized water, ammonium hydroxide, hydrogen peroxide), and water. In one embodiment, the cleaning step includes pre-wetting with water containing carbon dioxide for 30 seconds, then performing SPM cleaning for 60 seconds, then performing SC1 cleaning for 60 seconds, and then blowing dry with a nitrogen flow rate of 35L/min. In another embodiment, the cleaning step includes SPM (H ₂ SO ₄ : H ₂ O ₂ =1:1) cleaning for 15 seconds (temperature: 180°C), followed by SC1 (NH ₄ OH : H ₂ O ₂ : H ₂ 0 = 1:4:100) Clean for 20 seconds (room temperature). In yet another embodiment, the cleaning step includes SC1 (NH ₄ OH: H ₂ O ₂ :H ₂ 0 = 1:1:120) for 39 seconds (room temperature), then SPM (H ₂ SO ₄ : H ₂ O ₂ =2:1) for 49 seconds (125°C), followed by SC1 (NH ₄ OH: H ₂ O ₂ : H ₂ 0 = 1:1:120) for 10 seconds (room temperature). However, this disclosure is not limited to this. After the second chemical mechanical polishing step 753 is completed, another cleaning step may be performed on the semiconductor structure using deionized water.

Referring to FIG. 4 , an etching step 855 may be performed to remove portions of the first spacer 116 and the second spacer 118 above the gate electrode 112 from the nitride layer 222 and the oxide layer 324 . And remove the hard mask layer 114 to expose the gate electrode 112 . The etching step 855 may include chemical mechanical polishing, dry etching, or wet etching. The etching step 855 may be a non-selective etching to planarize the surface of the structure. In another embodiment, the etch step 855 may use the hard mask layer 114 as an etch stop layer and stop on the hard mask layer 114 , and then may be moved using another etch step that is selective for the hard mask layer 114 . The hard mask layer 114 is removed to expose the underlying gate electrode 112 .

Referring to FIG. 5 , the gate electrode 112 (i.e., the dummy gate electrode or the sacrificial gate electrode) can be removed using an etching step that is selective to the gate electrode 112 . This etching step can include dry etching, wet etching. , or a combination of the above. In one embodiment, a portion of the gate electrode 112 may be removed by dry etching first, and then the remaining portion may be removed by wet etching.

Second embodiment

The first steps of the manufacturing method of the semiconductor structure of the second embodiment are the same as those of FIGS. 1 to 2 of the first embodiment, and will not be described again here. In the second embodiment, after the first chemical mechanical polishing step 651 (refer to the relevant description of Figure 2) is completed, the etching step 957 shown in Figure 6 is performed to reduce the thickness of the nitride layer 222, thereby making The upper surface of the nitride layer 222 is lower than the upper surface of the oxide layer 324 . In an embodiment, the etching step 957 includes a wet etching method or a dry etching method, the etching rate of the nitride layer 222 is greater than the etching rate of the oxide layer 324, or the oxide layer 324 is not etched substantially. Oxide layer 324 may serve as an etch mask for etch step 957 . The etchant used in the wet etching method includes phosphoric acid (H ₃ PO ₄ ), such as hot phosphoric acid, and its etching rate for the nitride layer 222 may be, for example, 30 Å/min. However, the present disclosure is not limited thereto. The etching step 957 may also use other suitable etching methods or etchant types.

Please refer back to Figure 3. Then, a second chemical mechanical polishing step 753 is performed from the surface of the structure processed by the etching step 957. The second chemical mechanical polishing step 753 of the second embodiment uses the same first polishing slurry as the first chemical mechanical polishing step 651, and the polishing rate of the oxide layer 324 is greater than the polishing rate of the nitride layer 222. The second chemical mechanical polishing step 753 of the second embodiment may use the nitride layer 222 left after the etching step 957 as a polishing stop layer.

In the second embodiment, the first chemical mechanical polishing step 651 and the second chemical mechanical polishing step 753 are both polishing steps with etching selectivity for oxides (such as silicon oxide), so polishing slurry materials with similar properties can be used. That is, the first polishing slurry (including first powder particles, such as ceria powder) of the first chemical mechanical polishing step 651 may be similar or identical to the second polishing slurry (including first powder particles) of the second chemical mechanical polishing step 753 second powder particles, such as cerium dioxide powder). The first powder particles and the second powder particles (for example, both ceria powder particles) with similar or identical properties are less likely to accumulate with each other into larger-sized particles. Therefore, even during the second chemical mechanical polishing step 753, the structure Even if there is the first polishing slurry substance remaining from the first chemical mechanical polishing step 651 on the surface, the problem of scratching the device components due to the generation of particles will not occur.

After the second chemical mechanical polishing step 753 is completed, a cleaning step may be performed on the semiconductor structure using deionized water. You can then proceed to the next steps. The subsequent steps of the manufacturing method of the semiconductor structure of the second embodiment are the same as those of Figures 4 to 5 of the first embodiment, and will not be described again here.

Based on the above, in the first embodiment of the present disclosure, a cleaning step is performed between the first chemical mechanical polishing step and the second chemical mechanical polishing step that are selective for grinding oxides and nitrides respectively, wherein the cleaning step can remove Remove the first polishing slurry material remaining in the first chemical mechanical polishing step. In the second embodiment of the present disclosure, after the first chemical mechanical polishing step that is selective for polishing the oxide layer, an etching step that is selective for the nitride layer is used to reduce the thickness of the nitride layer, thereby reducing the thickness of the nitride layer. The upper surface of the nitride layer is positioned lower than the upper surface of the oxide layer, and then a second chemical mechanical polishing step with selectivity to the oxide layer is performed. In this way, both embodiments can avoid the problem of abrasive particles used in different abrasive slurries from accumulating with each other (for example, due to positive and negative electric attraction forces) into larger-sized particles, causing the particles to scratch device components.

In summary, although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

102:Semiconductor substrate 104:Isolation structure 106: Gate dielectric layer 108: First material layer 110: Second material layer 112: Gate electrode 114: Hard mask layer 116: First gap wall 118:Second gap wall 120: Source/Drain 222:Nitride layer 324:Oxide layer 651: First chemical mechanical grinding step 753: Second chemical mechanical grinding step 855: Etching step 957: Etching step G: Gate structure

FIG. 1 illustrates one step of a method of manufacturing a semiconductor structure according to an embodiment. FIG. 2 illustrates one step of a method of manufacturing a semiconductor structure according to an embodiment. FIG. 3 illustrates one step of the manufacturing method of the semiconductor structure according to the embodiment. FIG. 4 illustrates one step of the manufacturing method of the semiconductor structure according to the embodiment. FIG. 5 illustrates one step of the manufacturing method of the semiconductor structure according to the embodiment. FIG. 6 illustrates one step of the manufacturing method of the semiconductor structure according to the embodiment.

102:Semiconductor substrate

104:Isolation structure

106: Gate dielectric layer

108: First material layer

110: Second material layer

112: Gate electrode

114: Hard mask layer

116: First gap wall

118:Second gap wall

120: Source/Drain

222:Nitride layer

324:Oxide layer

957: Etching step

G: Gate structure

Claims (17)

A method of manufacturing a semiconductor structure, including: forming a gate structure on a semiconductor substrate; forming a nitride layer to cover the gate structure and the semiconductor substrate; forming an oxide layer to cover the nitride layer; A first chemical mechanical polishing step, using a first polishing slurry to polish downward from an upper surface of the oxide layer until the nitride layer is exposed, the polishing rate of the first polishing slurry to the oxide layer is greater than that of the oxide layer. The polishing rate of the nitride layer; A cleaning step, using a cleaning solution to apply to the exposed portions of the nitride layer and the oxide layer after the first chemical mechanical polishing, the cleaning solution including sulfuric acid, ammonia, hydrogen peroxide, or a combination of the above; and A second chemical mechanical polishing step, using a second polishing slurry to polish the exposed portion of the nitride layer after the cleaning step, the polishing rate of the second polishing slurry for the nitride layer is greater than that of the oxide layer The polishing rate of the layer. The method for manufacturing a semiconductor structure as described in claim 1, wherein the first polishing slurry includes ceria, and the second polishing slurry includes silicon dioxide. The manufacturing method of a semiconductor structure as described in item 1 of the patent application, wherein the nitride layer is used as a polishing stop layer in the first chemical mechanical polishing step, and the oxide layer is used as a polishing layer in the second chemical mechanical polishing step. Stop layer. The manufacturing method of a semiconductor structure as described in claim 1 of the patent application further includes performing another cleaning step using deionized water after the second chemical mechanical polishing step. The manufacturing method of a semiconductor structure as described in item 1 of the patent application further includes an etching step after the second chemical mechanical polishing step to remove the nitride layer and oxide layer above the gate electrode of the gate structure. The layer is etched down to expose the gate electrode. The manufacturing method of the semiconductor structure described in claim 5 of the patent application further includes removing the gate electrode after the etching step. A method of manufacturing a semiconductor structure, including: forming a gate structure on a semiconductor substrate; forming a nitride layer to cover the gate structure and the semiconductor substrate; forming an oxide layer to cover the nitride layer; A first chemical mechanical polishing step, grinding downward from an upper surface of the oxide layer until the nitride layer is exposed. The polishing rate of the first chemical mechanical polishing step of the oxide layer is greater than that of the nitride layer. Rate; An etching step using an etchant to apply to the nitride layer above the gate structure after the first chemical mechanical polishing, the etchant including phosphoric acid; and A second chemical mechanical polishing step is to polish the exposed portion of the oxide layer after the etching step. The polishing rate of the oxide layer in the second chemical mechanical polishing step is greater than the polishing rate of the nitride layer. As claimed in claim 7, the method for manufacturing a semiconductor structure, wherein the etching rate of the nitride layer by the etchant is greater than the etching rate of the oxide layer. As described in claim 8 of the patent application, the method for manufacturing a semiconductor structure, wherein the etchant does not substantially etch the oxide layer. As claimed in claim 7, the method for manufacturing a semiconductor structure, wherein the first chemical mechanical polishing step uses a first polishing slurry, and the first polishing slurry includes ceria. As claimed in claim 7, the method for manufacturing a semiconductor structure, wherein a residual portion of the nitride remaining above the gate structure after the etching step is used as a polishing stop layer for the second chemical mechanical polishing step. As claimed in claim 7, the method for manufacturing a semiconductor structure, wherein the nitride layer is used as a polishing stop layer for the first chemical mechanical polishing step. The method for manufacturing a semiconductor structure as described in Item 7 of the patent application further includes a cleaning step using deionized water after the second chemical mechanical polishing step. The manufacturing method of a semiconductor structure as described in item 7 of the patent application further includes another etching step after the second chemical mechanical polishing step to remove the nitride layer above the gate electrode of the gate structure from the oxide layer. The material layer is etched downward to expose the gate electrode. The method of manufacturing a semiconductor structure as described in claim 14 further includes removing the gate electrode after the other etching step. The manufacturing method of a semiconductor structure as described in item 7 of the patent application, wherein an upper surface position of the nitride layer is changed from being higher than the upper surface of the oxide layer to being lower than the oxide layer through the etching step. of the upper surface. As described in claim 7 of the patent application, the method for manufacturing a semiconductor structure is characterized in that both the first chemical mechanical polishing step and the second chemical mechanical polishing step use cerium dioxide powder.

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