CN113084598B - Cost-reducing and efficiency-improving silicon wafer edge polishing process - Google Patents

Cost-reducing and efficiency-improving silicon wafer edge polishing process Download PDF

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Publication number
CN113084598B
CN113084598B CN202110361875.4A CN202110361875A CN113084598B CN 113084598 B CN113084598 B CN 113084598B CN 202110361875 A CN202110361875 A CN 202110361875A CN 113084598 B CN113084598 B CN 113084598B
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silicon wafer
polishing
section
polishing process
face
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CN113084598A (en
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王鸣
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Hangzhou Semiconductor Wafer Co Ltd
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Hangzhou Semiconductor Wafer Co Ltd
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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B24GRINDING; POLISHING
    • B24BMACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B21/00Machines or devices using grinding or polishing belts; Accessories therefor
    • B24B21/002Machines or devices using grinding or polishing belts; Accessories therefor for grinding edges or bevels

Abstract

The invention relates to a cost-reducing and efficiency-improving silicon wafer edge polishing process, which belongs to the technical field of silicon wafer manufacturing. And turning over the silicon wafer, polishing the end face of the front face, and performing spray cleaning. In the peripheral edge polishing process, feeding is started from the section A2 on the side edge of the back surface, the section A1 on the side edge of the front surface is processed after the section BC passes through, then the section A3526 is folded back from the tail end of the section A1 to continue polishing, and the section BC is retreated from the upper end of the section BC, so that spraying cleaning is carried out after the peripheral edge polishing process of the silicon wafer is completed. The two ends of the silicon wafer pass through the fine polishing belt which circularly runs in a single direction, and the rotating shaft drives the silicon wafer fixed by the magnetic disk to rotate at the moment. And taking the silicon wafer after the polishing process by a mechanical arm, and placing the silicon wafer in an overflow groove for storage. Has the characteristics of high efficiency, short processing period and good quality stability. The problem of guarantee the side throwing quality and shorten the side throwing time is solved. The production capacity is improved and the cost is reduced.

Description

Cost-reducing and efficiency-improving silicon wafer edge polishing process
Technical Field
The invention relates to the technical field of silicon wafer manufacturing, in particular to a cost-reducing and efficiency-improving silicon wafer edge polishing process.
Background
Edge polishing is a necessary process for 8 inch and 12 inch silicon polishing wafers for the purposes of: (1) removing a possible damage layer at the edge of the silicon wafer, and (2) obtaining a smooth chamfer surface to reduce the risk of adsorbing particles at the edge of the silicon wafer.
Currently, the edge polishing machine of BBS KINMEI company is commonly adopted in the 8-inch and 12-inch silicon wafer processing industry to perform edge polishing processing on silicon wafers. The BBS edge polishing machine is characterized in that a part adhered with edge polishing cloth is tightly attached to the silicon wafer chamfer surface under the action of centrifugal force, and the silicon wafer chamfer surface is polished in the high-speed rotation of the edge polishing drum and the change of the relative position of the edge polishing drum and the silicon wafer.
As published by BBS kimmie corporation, application No.: JP 2008155539. Taking an 8-inch silicon wafer as an example, the factory process parameter values of the BBS KINMEI E-200 type edge polishing machine are as follows: the stroke of the grinding table is 15mm, the up-and-down traveling speed of the grinding table is 0.33mm/min, and the side polishing process time is 45 seconds. If the processing is carried out according to the default process of leaving factories, the speed of E-200 piece production is 75 seconds per piece, and the daily yield is about 900 pieces. If the monthly capacity is 10 thousands, 4 side polishing machines are required. If daily production can be increased to 1111, the equipment investment cost is reduced by 25%. The productivity is improved under the existing equipment quantity, and the normal method is to shorten the side polishing process time, but the side polishing quality can be influenced, and even the risk of epitaxial slip lines exists.
Disclosure of Invention
The invention mainly solves the defects of low efficiency, long processing period and poor quality stability in the prior art, and provides the cost-reducing and efficiency-improving silicon wafer edge polishing process which has the characteristics of high efficiency, short processing period and good quality stability. The problem of guarantee the side throwing quality and shorten the side throwing time is solved. The production capacity is improved and the cost is reduced.
The technical problem of the invention is mainly solved by the following technical scheme:
a cost-reducing and efficiency-improving silicon wafer edge polishing process comprises the following operation steps:
the first step is as follows: taking the silicon wafer by a manipulator, sending the silicon wafer into an end face mill for positioning, polishing the end face of the back, and spraying and cleaning the polished back.
The second step is that: and turning over the silicon wafer, polishing the end face of the front face, and performing spray cleaning after polishing the front face.
The third step: and after finishing polishing two end surfaces of the silicon wafer, carrying out an outer periphery polishing process, wherein the back surface is on the top, the front surface is on the bottom, feeding is carried out from the section A2 on the side edge of the back surface, the section A1 on the side edge of the front surface is processed after the section BC passes through, then the section A3526 is folded back from the tail end of the section A1 to continue polishing, and the section B is withdrawn from the upper end of the section BC, so that spray cleaning is carried out after the outer periphery polishing process of the silicon wafer is finished.
The fourth step: two ends of the silicon wafer pass through the fine polishing belt which circularly runs in a single direction, at the moment, the rotating shaft drives the silicon wafer fixed by the magnetic disc to rotate, and meanwhile, the silicon wafer is sprayed in the fine polishing process.
The fifth step: and taking the silicon wafer after the polishing process by a mechanical arm, and placing the silicon wafer in an overflow groove for storage.
Preferably, the processing time in the A2 stage is 8 seconds, the processing time in the BC stage and the A1 stage are both 16 seconds, the silicon wafer traveling speed on the grinding table is set to 0.63mm/s, and the grinding table traveling width is 15 mm.
Preferably, the fine polishing belt is in fit type insertion connection with the outer periphery of the silicon wafer through the fine polishing annular groove, and the water belt grinding process of the fine polishing belt on the silicon wafer is realized by adopting the fine polishing annular groove and synchronous spraying.
Preferably, the polishing solution in the polishing process is prepared by mixing and proportioning stock solution and deionized water, and the proportioning is 1: 8-1: 30.
Preferably, the stock solution is a water-soluble polishing agent without any sulfur, phosphorus or chlorine additive, and the stock solution can be silicon oxide polishing solution or cerium oxide polishing solution.
The invention can achieve the following effects:
compared with the prior art, the silicon wafer edge polishing process has the characteristics of high efficiency, short processing period and good quality stability. The problem of guarantee the side throwing quality and shorten the side throwing time is solved. The production capacity is improved and the cost is reduced.
Drawings
Fig. 1 is a schematic structural view of the present invention.
Fig. 2 is a schematic diagram of the fine polishing structure of the present invention.
Fig. 3 is a structural sectional view of the fine polishing belt of the present invention.
In the figure: the device comprises a silicon wafer 1, a back surface 2, a front surface 3, a fine polishing belt 4, a magnetic disk 5, a rotating shaft 6 and a fine polishing annular groove 7.
Detailed Description
The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings.
Example (b): as shown in fig. 1, fig. 2 and fig. 3, a cost-reducing and efficiency-increasing silicon wafer edge polishing process includes the following operation steps:
the first step is as follows: taking the silicon wafer 1 by a manipulator, sending the silicon wafer into an end face mill for positioning, polishing the end face of the back face 2, and performing spray cleaning after polishing the back face 2.
The second step is that: and turning over the silicon wafer 1, polishing the end face of the front face 3, and performing spray cleaning after polishing the front face 3.
The third step: and after finishing polishing two end surfaces of the silicon wafer 1, performing an outer periphery polishing process, wherein the back surface 2 is arranged above, the front surface 3 is arranged below, feeding is started from the section A2 on the side edge of the back surface 2, the section A1 on the side edge of the front surface 3 is processed after the section BC passes through, then the section A3526 is folded back from the tail end of the section A1 to continue polishing and retreat from the upper end of the section BC, and performing spray cleaning after finishing the outer periphery polishing process of the silicon wafer 1.
The processing time in the A2 stage was 8 seconds, the processing time in the BC and A1 stages was 16 seconds, the wafer 1 was set at a traveling speed of 0.63mm/s on the grinding table, and the traveling width of the grinding table was 15 mm.
The fourth step: two ends of the silicon chip 1 pass through the fine polishing belt 4 which circularly runs in a single direction, at the moment, the rotating shaft 6 drives the silicon chip 1 fixed by the magnetic disc 5 to rotate, and meanwhile, the silicon chip 1 is sprayed in the fine polishing process. The fine polishing belt 4 is in fit insertion connection with the outer periphery of the silicon wafer 1 through the fine polishing annular groove 7, and the water belt grinding process of the fine polishing belt 4 on the silicon wafer 1 is realized by adopting the fine polishing annular groove 7 and synchronous spraying.
The fifth step: and taking the silicon wafer 1 after finishing the polishing process by a mechanical arm, and placing the silicon wafer into an overflow groove for storage.
The polishing solution in the polishing process is prepared by mixing and proportioning stock solution and deionized water, and the proportioning is 1: 15. The stock solution is a water-soluble polishing agent without any sulfur, phosphorus and chlorine additives, and can be silicon oxide polishing solution or cerium oxide polishing solution.
In conclusion, the cost-reducing and efficiency-improving silicon wafer edge polishing process has the characteristics of high efficiency, short processing period and good quality stability. The problem of guarantee the side throwing quality and shorten the side throwing time is solved. The production capacity is improved and the cost is reduced.
The above description is only an embodiment of the present invention, but the structural features of the present invention are not limited thereto, and any changes or modifications within the scope of the present invention by those skilled in the art are covered by the present invention.

Claims (1)

1. A cost-reducing and efficiency-improving silicon wafer edge polishing process is characterized by comprising the following steps: the method comprises the following operation steps:
the first step is as follows: taking a silicon wafer (1) by a manipulator, sending the silicon wafer into an end face mill for positioning, polishing the end face of the back face (2), and performing spray cleaning after polishing the back face (2);
the second step is that: turning over the silicon wafer (1), polishing the end face of the front face (3), and performing spray cleaning after polishing the front face (3);
the third step: after finishing polishing two end surfaces of the silicon wafer (1), carrying out an outer periphery polishing process, wherein the back surface (2) is arranged on the upper side, the front surface (3) is arranged on the lower side, feeding is carried out from the section A2 on the side edge of the back surface (2), the section A1 on the side edge of the front surface (3) is processed through the section BC, then the rear end of the section A1 is folded back to continue polishing, and the cutter is withdrawn from the upper end of the section BC, and carrying out spray cleaning after the outer periphery polishing process of the silicon wafer (1) is finished; the fine polishing belt (4) is in fit insertion connection with the outer periphery of the silicon wafer (1) through a fine polishing annular groove (7), and the water belt grinding process of the fine polishing belt (4) on the silicon wafer (1) is realized by adopting the fine polishing annular groove (7) and synchronous spraying;
the processing time of the section A2 is 8 seconds, the processing time of the section BC and the processing time of the section A1 are both 16 seconds, the advancing speed of the silicon wafer (1) on the grinding table is set to be 0.63mm/s, and the advancing amplitude of the grinding table is 15 mm;
the polishing solution in the polishing process is prepared by mixing and proportioning stock solution and deionized water, and the proportioning is 1: 8-1: 30; the stock solution is a water-soluble polishing agent without any sulfur, phosphorus and chlorine additives, and can be silicon oxide polishing solution or cerium oxide polishing solution;
the fourth step: two ends of the silicon wafer (1) pass through a fine polishing belt (4) which circularly runs in a single direction, at the moment, the rotating shaft (6) drives the silicon wafer (1) fixed by the magnetic disc (5) to rotate, and meanwhile, the silicon wafer (1) is sprayed in the fine polishing process;
the fifth step: and taking the silicon wafer (1) which is subjected to the polishing process by a mechanical arm, and placing the silicon wafer into an overflow groove for storage.
CN202110361875.4A 2021-04-02 2021-04-02 Cost-reducing and efficiency-improving silicon wafer edge polishing process Active CN113084598B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086277A (en) * 2004-09-15 2006-03-30 Lapmaster Sft Corp Method of polishing semiconductor wafer
JP2015208782A (en) * 2014-04-23 2015-11-24 富士紡ホールディングス株式会社 Abrasive pad
CN107958835A (en) * 2016-10-14 2018-04-24 上海新昇半导体科技有限公司 A kind of polishing method of semiconductor crystal wafer
CN111761419A (en) * 2020-06-11 2020-10-13 上海新欣晶圆半导体科技有限公司 Adhesive tape grinding process for repairing edge damage of wafer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5274993B2 (en) * 2007-12-03 2013-08-28 株式会社荏原製作所 Polishing equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006086277A (en) * 2004-09-15 2006-03-30 Lapmaster Sft Corp Method of polishing semiconductor wafer
JP2015208782A (en) * 2014-04-23 2015-11-24 富士紡ホールディングス株式会社 Abrasive pad
CN106232296A (en) * 2014-04-23 2016-12-14 富士纺控股株式会社 Grinding pad
CN107958835A (en) * 2016-10-14 2018-04-24 上海新昇半导体科技有限公司 A kind of polishing method of semiconductor crystal wafer
CN111761419A (en) * 2020-06-11 2020-10-13 上海新欣晶圆半导体科技有限公司 Adhesive tape grinding process for repairing edge damage of wafer

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