CN109894962A - A kind of silicon chip edge polishing process - Google Patents
A kind of silicon chip edge polishing process Download PDFInfo
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- CN109894962A CN109894962A CN201711290241.4A CN201711290241A CN109894962A CN 109894962 A CN109894962 A CN 109894962A CN 201711290241 A CN201711290241 A CN 201711290241A CN 109894962 A CN109894962 A CN 109894962A
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Abstract
The invention discloses a kind of silicon chip edge polishing process, the technique is the following steps are included: (1) starts the cleaning processing silicon wafer using cleaning machine；(2) silicon wafer after cleaning is subjected to board centering processing；(3) the round edge edge of silicon wafer is processed by shot blasting；(4) silicon wafer for completing round edge edge polishing is subjected to plane of reference localization process；(5) silicon wafer determined to completion reference plane position carries out the processing of plane of reference edge polishing.The present invention is by increasing the preceding cleaning treatment of side throwing and changing edge polishing process sequence, effective solution side throw during caused by plane of reference edge corrosion the problem of damaging, smooth undamaged plane of reference edge is obtained, extension processing and device process yield are improved.
Description
Technical field
The present invention relates to a kind of silicon chip edge polishing processes, belong to silicon chip process technology field.
Background technique
As semi-conductor industry is along the rapidly development of Moore's Law, microelectronic component characteristic size constantly reduces, to silicon
Integrality, uniformity, surface quality, edge quality, performance detection evaluation of material etc. propose increasingly harsher requirement.For
The productivity for improving epitaxial wafer or device producer, to silicon chip edge quality proposes more strict requirements.For 8 inches or
It is generally to cross Cheng Qian for larger sized silicon wafer in surface polishing and need to carry out edge polishing.Edge polishing is using chemical machine
Tool polishing, there are one layer of polishing fluid thin layer between silicon chip edge surface and polishing cloth, corrodes silicon chip edge surface, generates
One layer of chemicals transition zone, in the collective effect of polishing cloth and polishing fluid, chamfering damaging layer is constantly corroded and removes, finally
Smooth undamaged edge surface is obtained, to prevent the easy chipping in edge, extension back edge defect etc..
In traditional edge polishing process process, plane of reference edge polishing is usually first carried out, then carry out round edge edge
Polishing.The process features are before edge polishing without cleaning, and plane of reference edge polishing is prior to round edge edge polishing.Due to edge table
The hydrophobicity in face makes the SiO in polishing fluid2The alkaline solution of soliquid composition is gathered in edge surface, makes chemical attack
Effect is greater than mechanical removal and acts on, and increases surface micro-roughness.It is thrown simultaneously when the silicon wafer for having thrown the plane of reference is using round edge
When board, since the plane of reference is not by mechanism, polishing fluid chemical attack damaging layer caused by the plane of reference can be left behind,
It is observed under metallographic microscope (Nikon-L200N), as shown in Figure 2.Edge there are the silicon wafer of damaging layer extension process when be easy
Extension stacking fault defects are generated in injury region, epitaxial wafer or device yield is reduced, influences product quality.As shown in figure 3, in gold
The outer edge defect delayed observed under phase microscope (Nikon-L200N).
Summary of the invention
The purpose of the present invention is to provide a kind of silicon chip edge polishing processes, to solve round edge edge polishing in the prior art
The technical issues of causing corrosion damage to the silicon wafer plane of reference in the process improves extension processing and device process yield.
To achieve the above object, the invention adopts the following technical scheme:
A kind of silicon chip edge polishing process, comprising the following steps:
(1) silicon wafer is started the cleaning processing using cleaning machine；
(2) silicon wafer after cleaning is subjected to board centering processing；
(3) the round edge edge of silicon wafer is processed by shot blasting；
(4) silicon wafer for completing round edge edge polishing is subjected to plane of reference localization process；
(5) silicon wafer determined to completion reference plane position carries out the processing of plane of reference edge polishing.
In the step (1), 1 cleaning is carried out to silicon wafer using SC-1 cleaning solution, the time is 6-10 minutes, cleaning temperature
Degree is 50-80 DEG C, carries out QDR in pure water slot later and rinses 3 times, finally makes silicon chip edge surface in hydrophily.Wherein, described
SC-1 cleaning solution is by ammonium hydroxide, hydrogen peroxide and pure water by (1-2): (1-2): the mass ratio of (10-20) mixes.
Preferably, in the step (2), centering, the silicon wafer center of circle and board circle are carried out to silicon wafer using edge polisher
The heart deviates range within 0.2mm.
Preferably, in the step (3), used polishing cloth hardness is 60Aske-C, edge polishing pressure 80-
120N, revolving speed 500-900r/min, time 50-90s.
Preferably, in the step (4), the silicon wafer plane of reference and the board depth of parallelism are within 0.1mm.
Preferably, in the step (5), used polishing cloth hardness is 60Aske-C, edge polishing pressure 10-
30N, revolving speed 1000-1300r/min, time 50-90s.
The present invention has the advantages that
Cleaning treatment and change edge polishing process sequence before the present invention is thrown by increasing side, effective solution side was thrown
The problem of plane of reference edge corrosion caused by journey damages, obtains smooth undamaged plane of reference edge, improves extension processing
And device process yield.
Detailed description of the invention
Fig. 1 is process flow chart of the invention.
Fig. 2 is that the silicon chip edge corrosion damage after process flow processing is thrown using traditional side.
Fig. 3 is to have the defects that the silicon wafer of corrosion damage by delaying generation outside.
Fig. 4 is the pattern delayed outside the silicon wafer processed using technique of the invention.
Specific embodiment
Below by drawings and examples, the present invention will be further described, but is not meant to the scope of the present invention
Limitation.
As shown in Figure 1, being process flow chart of the invention, included process is successively are as follows: at SC-1 cleaning-silicon wafer centering
Reason-round edge edge polishing-plane of reference positioning-plane of reference edge polishing.
Embodiment
Process 8 cun of heavily doped As, the pingbian plane of reference silicon wafer that chamfering degree is 22 degree
(1) using cleaning machine treat side throw silicon wafer cleaned, first pass through SC-1 cleaning, SC-1 cleaning solution be by ammonium hydroxide,
Hydrogen peroxide and pure water are mixed in 1: 1: 15 ratio to be formed.Scavenging period is 7 minutes, and cleaning temperature is 70 DEG C, later in pure water slot
Middle progress QDR is rinsed 3 times.Finally it is dried using drying mode.
(2) by step (1) complete cleaning silicon wafer be put into side throw machine feeding platform, by Manipulator Transportation to centering board into
Row centering positioning, it is ensured that range is deviateed within 0.2mm in the silicon wafer center of circle and the board center of circle.
(3) silicon wafer that step (2) complete centering is subjected to the processing of round edge edge polishing, used polishing cloth hardness is
60Aske-C, side throwing liquid is mixed with pure water in 1: 15 ratio by polishing fluid (Cabot-EP4000C) to be formed, and pH value control exists
Within the scope of 10.5-11, edge polishing pressure 100N, revolving speed 800r/min, time 60s.
(4) silicon wafer that step (3) complete round edge edge polishing is subjected to plane of reference localization process, the silicon wafer plane of reference and board
The depth of parallelism is within 0.1mm.
(5) step (4) are completed into the silicon wafer that reference plane position determines and carries out the processing of plane of reference edge polishing, used throwing
Light cloth hardness is 60Aske-C, edge polishing pressure 20N, revolving speed 1100r/min, time 60s.
As shown in figure 4, the silicon wafer that the present embodiment is processed is observed at metallographic microscope (Nikon-L200N), edge
The corrosion-free damage of the plane of reference, delays not damaged defect outside.
Claims (7)
1. a kind of silicon chip edge polishing process, which comprises the following steps:
(1) silicon wafer is started the cleaning processing using cleaning machine；
(2) silicon wafer after cleaning is subjected to board centering processing；
(3) the round edge edge of silicon wafer is processed by shot blasting；
(4) silicon wafer for completing round edge edge polishing is subjected to plane of reference localization process；
(5) silicon wafer determined to completion reference plane position carries out the processing of plane of reference edge polishing.
2. silicon chip edge polishing process according to claim 1, which is characterized in that in the step (1), use SC-1
Cleaning solution carries out 1 cleaning to silicon wafer, and the time is 6-10 minutes, and cleaning temperature is 50-80 DEG C, carries out in pure water slot later
QDR is rinsed 3 times, finally makes silicon chip edge surface in hydrophily.
3. silicon chip edge polishing process according to claim 2, which is characterized in that the SC-1 cleaning solution be by ammonium hydroxide,
Hydrogen peroxide and pure water press (1-2): (1-2): the mass ratio of (10-20) mixes.
4. silicon chip edge polishing process according to claim 1, which is characterized in that in the step (2), use edge
Polishing machine carries out centering to silicon wafer, and range is deviateed within 0.2mm in the silicon wafer center of circle and the board center of circle.
5. silicon chip edge polishing process according to claim 1, which is characterized in that used in the step (3)
Polishing cloth hardness is 60Aske-C, edge polishing pressure 80-120N, revolving speed 500-900r/min, time 50-90s.
6. silicon chip edge polishing process according to claim 1, which is characterized in that in the step (4), silicon wafer reference
Face and the board depth of parallelism are within 0.1mm.
7. silicon chip edge polishing process according to claim 1, which is characterized in that used in the step (5)
Polishing cloth hardness is 60Aske-C, edge polishing pressure 10-30N, revolving speed 1000-1300r/min, time 50-90s.
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| CN201711290241.4A CN109894962B (en) | 2017-12-07 | 2017-12-07 | Silicon wafer edge polishing process |
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| CN201711290241.4A CN109894962B (en) | 2017-12-07 | 2017-12-07 | Silicon wafer edge polishing process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111540676A (en) * | 2020-05-11 | 2020-08-14 | 西安奕斯伟硅片技术有限公司 | Silicon wafer edge stripping method and silicon wafer |
| CN113858020A (en) * | 2021-09-15 | 2021-12-31 | 杭州中欣晶圆半导体股份有限公司 | Device and process method for controlling micro scratches on polished surface of silicon wafer |
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|---|---|---|---|---|
| CN111540676A (en) * | 2020-05-11 | 2020-08-14 | 西安奕斯伟硅片技术有限公司 | Silicon wafer edge stripping method and silicon wafer |
| CN111540676B (en) * | 2020-05-11 | 2024-02-23 | 西安奕斯伟材料科技股份有限公司 | Silicon wafer edge stripping method and silicon wafer |
| CN113858020A (en) * | 2021-09-15 | 2021-12-31 | 杭州中欣晶圆半导体股份有限公司 | Device and process method for controlling micro scratches on polished surface of silicon wafer |
| CN113858020B (en) * | 2021-09-15 | 2023-10-13 | 杭州中欣晶圆半导体股份有限公司 | Device and process method for controlling micro scratch on polished surface of silicon wafer |
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| CN109894962B (en) | 2020-04-17 |
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Address after: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Patentee after: Youyan semiconductor silicon materials Co.,Ltd. Address before: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Patentee before: GRINM SEMICONDUCTOR MATERIALS Co.,Ltd. |
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Effective date of registration: 20210629 Address after: 253012 room 921, block a, No. 6596, Dongfanghong East Road, Yuanqiao Town, Dezhou Economic and Technological Development Zone, Shandong Province Patentee after: Shandong Youyan semiconductor materials Co.,Ltd. Address before: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Patentee before: Youyan semiconductor silicon materials Co.,Ltd. |