JP2008004913A - 不揮発性メモリ素子の動作方法 - Google Patents
不揮発性メモリ素子の動作方法 Download PDFInfo
- Publication number
- JP2008004913A JP2008004913A JP2007011879A JP2007011879A JP2008004913A JP 2008004913 A JP2008004913 A JP 2008004913A JP 2007011879 A JP2007011879 A JP 2007011879A JP 2007011879 A JP2007011879 A JP 2007011879A JP 2008004913 A JP2008004913 A JP 2008004913A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- memory cell
- gate
- charge storage
- dielectric structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000011017 operating method Methods 0.000 title claims abstract 5
- 230000005641 tunneling Effects 0.000 claims abstract description 131
- 238000003860 storage Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 238000000034 method Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 19
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 9
- 229910004140 HfO Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 238000002955 isolation Methods 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 241000293849 Cordylanthus Species 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 14
- 238000009792 diffusion process Methods 0.000 description 14
- 230000005684 electric field Effects 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000008859 change Effects 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
【解決手段】不揮発性メモリ素子の動作方法を提供する。素子は、半導体基板、スタック層、および基板の表面下に配置し、チャネル領域によって分離されたソース領域とドレイン領域を備えたメモリセルを有する。スタック層は、チャネル領域上に配置した絶縁層、絶縁層上に配置した電荷蓄積層、電荷蓄積層上の多層トンネリング誘電体構造、および多層トンネリング誘電体構造上に配置したゲートを有する。ゲートに負のバイアスを供給し、−FNトンネリングによって、多層トンネリング誘電体構造を介して電荷蓄積層に電子を注入し、素子の閾値電圧を増大させる。ゲートに正のバイアスを供給し、+FNトンネリングによって、多層トンネリング誘電体構造を介して電荷蓄積層に正孔を注入し、素子の閾値電圧を減少させる。
【選択図】図1
Description
101 半導体基板
102 ソース領域
104 ドレイン領域
106 チャネル領域
140 絶縁層
150 電荷蓄積層
160 多層トンネリング誘電体構造
162 第一トンネリング誘電体層
164 小正孔トンネリング障壁高さ層
166 第二トンネリング誘電体層
170 ゲート
180 スタック層
401 基板
402 拡散領域
406 チャネル領域
440 絶縁層
450 電荷蓄積層
460 多層トンネリング誘電体構造
462 第一トンネリング誘電体層
464 小正孔トンネリング障壁高さ層
466 第二トンネリング誘電体層
470 ゲート
480 スタック層
490 溝分離部
Claims (18)
- メモリセルの動作方法であって、
表面下に配置したチャネル領域によって分離されている二つのソース/ドレイン領域を備えた基板と、
チャネル領域上に配置した絶縁層と、
絶縁層上に配置した電荷蓄積層と、
電荷蓄積層上に配置した多層トンネリング誘電体構造と、及び
多層トンネリング誘電体構造上に配置したゲートと、
を有するメモリセルを提供し、
第一動作を行い、ゲートに負のバイアスを供給し、ソース/ドレイン領域を浮遊、接地、または0Vに設定し、−FNトンネリングによってメモリセルのゲートから、多層トンネリング誘電体構造を介して電荷蓄積層に電子を注入し、メモリセルの閾値電圧を増大させ、
第二動作を行い、ゲートに正のバイアスを供給し、ソース/ドレイン領域を浮遊、接地、または0Vに設定し、+FNトンネリングによってメモリセルのゲートから、多層トンネリング誘電体構造を介して電荷蓄積層に正孔を注入し、メモリセルの閾値電圧を減少させる動作方法。 - 負のバイアスが、−約16Vと−約20Vの間である請求項1記載の動作方法。
- 正のバイアスが、約14Vと約16Vの間である請求項1記載の動作方法。
- ソース/ドレイン領域がp型の導電性であり、第一動作がプログラム動作であり、第二動作が消去動作である請求項1記載の動作方法。
- ソース/ドレイン領域がn型の導電性であり、第一動作が消去動作であり、第二動作がプログラム動作である請求項1記載の動作方法。
- 多層トンネリング誘電体構造が、酸化物/窒化物/酸化物層を有する請求項1記載の動作方法。
- 多層トンネリング誘電体構造が、酸化シリコン/窒化シリコン/酸化シリコン層または酸化シリコン/酸化アルミニウム/酸化シリコン層を有する請求項1記載の動作方法。
- 絶縁層の材料が、酸化シリコンまたは酸化アルミニウムを有する請求項1記載の動作方法。
- 電荷蓄積層の材料が、窒化シリコン、SiON、HfO2、HfSixOy、またはAl2O3を有する請求項1記載の動作方法。
- メモリ素子の動作方法であって、前記メモリ素子がゲート、ソース領域、ドレイン領域、ソース領域とドレイン領域の間のチャネル領域、チャネル領域上に配置した電荷蓄積層、電荷蓄積層とゲートの間の多層トンネリング誘電体構造、および電荷蓄積層とチャネル領域の間の絶縁層を有し、前記ゲートがワードラインに対応し、ソース領域が第一ビットラインに対応し、ドレイン領域が第二ビットラインに対応し、
所定のメモリセルに対して第一動作を行い、ワードラインに負のバイアスを供給し、第一および第二ビットラインを浮遊、接地、または0Vに設定し、−FNトンネリングによってメモリセルのゲートから、多層トンネリング誘電体構造を介して電荷蓄積層に電子を注入し、メモリセルの閾値電圧を増大させ、
所定のメモリセルに対して第二動作を行い、ワードラインに正のバイアスを供給し、第一および第二ビットラインを浮遊、接地、または0Vに設定し、+FNトンネリングによってメモリセルのゲートから、多層トンネリング誘電体構造を介して電荷蓄積層に正孔を注入し、メモリセルの閾値電圧を減少させる動作方法。 - 負のバイアスが、−約16Vと−約20Vの間である請求項1記載の動作方法。
- 正のバイアスが、約14と16Vの間である請求項1記載の動作方法。
- ソース/ドレイン領域がp型の導電性であり、第一動作がプログラム動作であり、第二動作が消去動作である請求項10記載の動作方法。
- ソース/ドレイン領域がn型の導電性であり、第一動作が消去動作であり、第二動作がプログラム動作である請求項10記載の動作方法。
- 多層トンネリング誘電体構造が、酸化物/窒化物/酸化物層を有する請求項10記載の動作方法。
- 多層トンネリング誘電体構造が、酸化シリコン/窒化シリコン/酸化シリコン層または酸化シリコン/酸化アルミニウム/酸化シリコン層を有する請求項10記載の動作方法。
- 絶縁層の材料が、酸化シリコンまたは酸化アルミニウムを有する請求項10記載の動作方法。
- 電荷蓄積層の材料が、窒化シリコン、SiON、HfO2、HfSixOy、またはAl2O3を有する請求項10記載の動作方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095122001 | 2006-06-20 | ||
TW095122001A TWI300931B (en) | 2006-06-20 | 2006-06-20 | Method of operating non-volatile memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008004913A true JP2008004913A (ja) | 2008-01-10 |
JP5367222B2 JP5367222B2 (ja) | 2013-12-11 |
Family
ID=38860698
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007011879A Active JP5367222B2 (ja) | 2006-06-20 | 2007-01-22 | 不揮発性メモリ素子の動作方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7463530B2 (ja) |
JP (1) | JP5367222B2 (ja) |
KR (1) | KR100919891B1 (ja) |
TW (1) | TWI300931B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008211162A (ja) * | 2007-02-01 | 2008-09-11 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2009021508A (ja) * | 2007-07-13 | 2009-01-29 | Renesas Technology Corp | 不揮発性半導体記憶装置およびその動作方法 |
US9478670B2 (en) | 2012-09-05 | 2016-10-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4965948B2 (ja) * | 2006-09-21 | 2012-07-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8101989B2 (en) * | 2006-11-20 | 2012-01-24 | Macronix International Co., Ltd. | Charge trapping devices with field distribution layer over tunneling barrier |
US7450423B2 (en) * | 2007-01-03 | 2008-11-11 | Macronix International Co., Ltd. | Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure |
US9299568B2 (en) | 2007-05-25 | 2016-03-29 | Cypress Semiconductor Corporation | SONOS ONO stack scaling |
US8633537B2 (en) | 2007-05-25 | 2014-01-21 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US20090179253A1 (en) | 2007-05-25 | 2009-07-16 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8063434B1 (en) | 2007-05-25 | 2011-11-22 | Cypress Semiconductor Corporation | Memory transistor with multiple charge storing layers and a high work function gate electrode |
US9449831B2 (en) | 2007-05-25 | 2016-09-20 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8643124B2 (en) | 2007-05-25 | 2014-02-04 | Cypress Semiconductor Corporation | Oxide-nitride-oxide stack having multiple oxynitride layers |
US8940645B2 (en) | 2007-05-25 | 2015-01-27 | Cypress Semiconductor Corporation | Radical oxidation process for fabricating a nonvolatile charge trap memory device |
US7643349B2 (en) * | 2007-10-18 | 2010-01-05 | Macronix International Co., Ltd. | Efficient erase algorithm for SONOS-type NAND flash |
US7848148B2 (en) * | 2007-10-18 | 2010-12-07 | Macronix International Co., Ltd. | One-transistor cell semiconductor on insulator random access memory |
KR20090041764A (ko) * | 2007-10-24 | 2009-04-29 | 삼성전자주식회사 | 비휘발성 메모리 소자의 동작 방법 |
US8089114B2 (en) * | 2007-11-08 | 2012-01-03 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including blocking and interface patterns between charge storage patterns and control electrodes and related methods |
US9431549B2 (en) | 2007-12-12 | 2016-08-30 | Cypress Semiconductor Corporation | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
US20090152621A1 (en) * | 2007-12-12 | 2009-06-18 | Igor Polishchuk | Nonvolatile charge trap memory device having a high dielectric constant blocking region |
JP5534748B2 (ja) | 2009-08-25 | 2014-07-02 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
US8685813B2 (en) | 2012-02-15 | 2014-04-01 | Cypress Semiconductor Corporation | Method of integrating a charge-trapping gate stack into a CMOS flow |
TWI498908B (zh) * | 2012-03-29 | 2015-09-01 | Ememory Technology Inc | 記憶體單元的操作方法 |
US9230977B2 (en) * | 2013-06-21 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded flash memory device with floating gate embedded in a substrate |
US9018061B2 (en) * | 2013-08-30 | 2015-04-28 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
KR20160055463A (ko) | 2014-11-10 | 2016-05-18 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 동작 방법 |
US9368510B1 (en) * | 2015-05-26 | 2016-06-14 | Sandisk Technologies Inc. | Method of forming memory cell with high-k charge trapping layer |
KR20210015148A (ko) * | 2019-07-31 | 2021-02-10 | 에스케이하이닉스 주식회사 | 음의 캐패시턴스를 구비하는 강유전층을 포함하는 비휘발성 메모리 장치 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55111175A (en) * | 1979-02-15 | 1980-08-27 | Ibm | Device for collecting charge |
Family Cites Families (73)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0582795A (ja) | 1991-08-22 | 1993-04-02 | Rohm Co Ltd | 半導体記憶装置 |
JPH0555596A (ja) | 1991-08-22 | 1993-03-05 | Rohm Co Ltd | 半導体不揮発性記憶装置 |
CA2184724A1 (en) * | 1994-03-03 | 1995-09-08 | Shang-De Chang | Low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase |
US5408115A (en) * | 1994-04-04 | 1995-04-18 | Motorola Inc. | Self-aligned, split-gate EEPROM device |
EP0843360A1 (en) | 1996-11-15 | 1998-05-20 | Hitachi Europe Limited | Memory device |
KR100473159B1 (ko) * | 1997-06-23 | 2005-06-23 | 주식회사 하이닉스반도체 | 낸드플래쉬메모리셀의프로그램및소거방법 |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
FR2770328B1 (fr) | 1997-10-29 | 2001-11-23 | Sgs Thomson Microelectronics | Point memoire remanent |
US6026026A (en) | 1997-12-05 | 2000-02-15 | Hyundai Electronics America, Inc. | Self-convergence of post-erase threshold voltages in a flash memory cell using transient response |
US6074917A (en) | 1998-06-16 | 2000-06-13 | Advanced Micro Devices, Inc. | LPCVD oxide and RTA for top oxide of ONO film to improve reliability for flash memory devices |
JP4923321B2 (ja) * | 2000-09-12 | 2012-04-25 | ソニー株式会社 | 不揮発性半導体記憶装置の動作方法 |
JP4696383B2 (ja) * | 2001-03-28 | 2011-06-08 | ソニー株式会社 | 不揮発性半導体記憶装置の製造方法 |
US6720630B2 (en) | 2001-05-30 | 2004-04-13 | International Business Machines Corporation | Structure and method for MOSFET with metallic gate electrode |
KR20020092114A (ko) * | 2001-06-02 | 2002-12-11 | 김대만 | 드레인 턴온 현상과 과잉 소거 현상을 제거한 sonos셀, 이를 포함하는 불휘발성 메모리 장치 및 그 제조방법 |
US7253467B2 (en) * | 2001-06-28 | 2007-08-07 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory devices |
US6858906B2 (en) * | 2001-06-28 | 2005-02-22 | Samsung Electronics Co., Ltd. | Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers |
TW546840B (en) | 2001-07-27 | 2003-08-11 | Hitachi Ltd | Non-volatile semiconductor memory device |
KR100395762B1 (ko) | 2001-07-31 | 2003-08-21 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
US6709928B1 (en) | 2001-07-31 | 2004-03-23 | Cypress Semiconductor Corporation | Semiconductor device having silicon-rich layer and method of manufacturing such a device |
KR100407573B1 (ko) | 2001-08-09 | 2003-11-28 | 삼성전자주식회사 | 부유 트랩형 비휘발성 메모리 장치 형성 방법 |
US7012297B2 (en) | 2001-08-30 | 2006-03-14 | Micron Technology, Inc. | Scalable flash/NV structures and devices with extended endurance |
US7476925B2 (en) | 2001-08-30 | 2009-01-13 | Micron Technology, Inc. | Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interploy insulators |
US6512696B1 (en) | 2001-11-13 | 2003-01-28 | Macronix International Co., Ltd. | Method of programming and erasing a SNNNS type non-volatile memory cell |
US7115469B1 (en) | 2001-12-17 | 2006-10-03 | Spansion, Llc | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process |
US6605840B1 (en) | 2002-02-07 | 2003-08-12 | Ching-Yuan Wu | Scalable multi-bit flash memory cell and its memory array |
US6784480B2 (en) | 2002-02-12 | 2004-08-31 | Micron Technology, Inc. | Asymmetric band-gap engineered nonvolatile memory device |
US7042045B2 (en) | 2002-06-04 | 2006-05-09 | Samsung Electronics Co., Ltd. | Non-volatile memory cell having a silicon-oxide nitride-oxide-silicon gate structure |
US6617639B1 (en) * | 2002-06-21 | 2003-09-09 | Advanced Micro Devices, Inc. | Use of high-K dielectric material for ONO and tunnel oxide to improve floating gate flash memory coupling |
US6897533B1 (en) | 2002-09-18 | 2005-05-24 | Advanced Micro Devices, Inc. | Multi-bit silicon nitride charge-trapping non-volatile memory cell |
KR100446632B1 (ko) | 2002-10-14 | 2004-09-04 | 삼성전자주식회사 | 비휘발성 sonsnos 메모리 |
US6900098B1 (en) * | 2002-10-15 | 2005-05-31 | Halo Lsi, Inc. | Twin insulator charge storage device operation and its fabrication method |
US6744675B1 (en) * | 2002-11-26 | 2004-06-01 | Advanced Micro Devices, Inc. | Program algorithm including soft erase for SONOS memory device |
KR100475119B1 (ko) * | 2002-11-26 | 2005-03-10 | 삼성전자주식회사 | Sonos 셀이 채용된 nor 형 플래시 메모리 소자의동작 방법 |
US6912163B2 (en) | 2003-01-14 | 2005-06-28 | Fasl, Llc | Memory device having high work function gate and method of erasing same |
KR100501457B1 (ko) | 2003-02-04 | 2005-07-18 | 동부아남반도체 주식회사 | 양자 트랩 디바이스를 위한 에스오엔오엔오에스 구조를 갖는 반도체 소자 |
US6815764B2 (en) | 2003-03-17 | 2004-11-09 | Samsung Electronics Co., Ltd. | Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same |
JP4040534B2 (ja) | 2003-06-04 | 2008-01-30 | 株式会社東芝 | 半導体記憶装置 |
US7115942B2 (en) | 2004-07-01 | 2006-10-03 | Chih-Hsin Wang | Method and apparatus for nonvolatile memory |
KR100973281B1 (ko) * | 2003-06-10 | 2010-07-30 | 삼성전자주식회사 | 소노스 메모리 소자 및 그 제조 방법 |
EP1487013A3 (en) * | 2003-06-10 | 2006-07-19 | Samsung Electronics Co., Ltd. | SONOS memory device and method of manufacturing the same |
KR20040106074A (ko) * | 2003-06-10 | 2004-12-17 | 삼성전자주식회사 | 소노스 메모리 소자 및 그 제조 방법 |
KR100562743B1 (ko) | 2003-10-06 | 2006-03-21 | 동부아남반도체 주식회사 | 플래시 메모리 소자의 제조방법 |
KR100579844B1 (ko) | 2003-11-05 | 2006-05-12 | 동부일렉트로닉스 주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
US7151692B2 (en) | 2004-01-27 | 2006-12-19 | Macronix International Co., Ltd. | Operation scheme for programming charge trapping non-volatile memory |
US7164603B2 (en) | 2004-04-26 | 2007-01-16 | Yen-Hao Shih | Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory |
US7075828B2 (en) | 2004-04-26 | 2006-07-11 | Macronix International Co., Intl. | Operation scheme with charge balancing erase for charge trapping non-volatile memory |
US7133313B2 (en) | 2004-04-26 | 2006-11-07 | Macronix International Co., Ltd. | Operation scheme with charge balancing for charge trapping non-volatile memory |
US7209390B2 (en) | 2004-04-26 | 2007-04-24 | Macronix International Co., Ltd. | Operation scheme for spectrum shift in charge trapping non-volatile memory |
US7187590B2 (en) | 2004-04-26 | 2007-03-06 | Macronix International Co., Ltd. | Method and system for self-convergent erase in charge trapping memory cells |
US7133316B2 (en) | 2004-06-02 | 2006-11-07 | Macronix International Co., Ltd. | Program/erase method for P-channel charge trapping memory device |
US7190614B2 (en) | 2004-06-17 | 2007-03-13 | Macronix International Co., Ltd. | Operation scheme for programming charge trapping non-volatile memory |
KR100597642B1 (ko) * | 2004-07-30 | 2006-07-05 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
US20060023258A1 (en) * | 2004-08-02 | 2006-02-02 | Xerox Corporation. | Method for minimizing boundary defects using halftone classes with matched harmonics |
KR100688575B1 (ko) * | 2004-10-08 | 2007-03-02 | 삼성전자주식회사 | 비휘발성 반도체 메모리 소자 |
US8264028B2 (en) | 2005-01-03 | 2012-09-11 | Macronix International Co., Ltd. | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
US20060198189A1 (en) | 2005-01-03 | 2006-09-07 | Macronix International Co., Ltd. | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
US7642585B2 (en) | 2005-01-03 | 2010-01-05 | Macronix International Co., Ltd. | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
EP2320426B1 (en) | 2005-01-03 | 2012-05-23 | Macronix International Co., Ltd. | Non-volatile memory memory arrays and methods of operating thereof |
US7315474B2 (en) | 2005-01-03 | 2008-01-01 | Macronix International Co., Ltd | Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays |
US7473589B2 (en) * | 2005-12-09 | 2009-01-06 | Macronix International Co., Ltd. | Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same |
US20090039417A1 (en) * | 2005-02-17 | 2009-02-12 | National University Of Singapore | Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide |
KR100644405B1 (ko) * | 2005-03-31 | 2006-11-10 | 삼성전자주식회사 | 불휘발성 메모리 장치의 게이트 구조물 및 이의 제조 방법 |
US7279740B2 (en) | 2005-05-12 | 2007-10-09 | Micron Technology, Inc. | Band-engineered multi-gated non-volatile memory device with enhanced attributes |
US7612403B2 (en) | 2005-05-17 | 2009-11-03 | Micron Technology, Inc. | Low power non-volatile memory and gate stack |
US7636257B2 (en) | 2005-06-10 | 2009-12-22 | Macronix International Co., Ltd. | Methods of operating p-channel non-volatile memory devices |
US7829938B2 (en) | 2005-07-14 | 2010-11-09 | Micron Technology, Inc. | High density NAND non-volatile memory device |
US7576386B2 (en) | 2005-08-04 | 2009-08-18 | Macronix International Co., Ltd. | Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer |
US7468299B2 (en) | 2005-08-04 | 2008-12-23 | Macronix International Co., Ltd. | Non-volatile memory cells and methods of manufacturing the same |
KR100628875B1 (ko) * | 2005-08-19 | 2006-09-26 | 삼성전자주식회사 | 소노스 타입의 비휘발성 메모리 장치 및 그 제조 방법 |
US7629641B2 (en) | 2005-08-31 | 2009-12-08 | Micron Technology, Inc. | Band engineered nano-crystal non-volatile memory device utilizing enhanced gate injection |
US8846549B2 (en) | 2005-09-27 | 2014-09-30 | Macronix International Co., Ltd. | Method of forming bottom oxide for nitride flash memory |
KR100682537B1 (ko) * | 2005-11-30 | 2007-02-15 | 삼성전자주식회사 | 반도체 소자 및 그 형성 방법 |
US7394702B2 (en) * | 2006-04-05 | 2008-07-01 | Spansion Llc | Methods for erasing and programming memory devices |
-
2006
- 2006-06-20 TW TW095122001A patent/TWI300931B/zh active
- 2006-10-30 US US11/554,455 patent/US7463530B2/en active Active
-
2007
- 2007-01-22 JP JP2007011879A patent/JP5367222B2/ja active Active
- 2007-06-15 KR KR1020070058643A patent/KR100919891B1/ko active IP Right Grant
-
2008
- 2008-11-10 US US12/267,740 patent/US8149628B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55111175A (en) * | 1979-02-15 | 1980-08-27 | Ibm | Device for collecting charge |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008211162A (ja) * | 2007-02-01 | 2008-09-11 | Renesas Technology Corp | 半導体記憶装置およびその製造方法 |
JP2009021508A (ja) * | 2007-07-13 | 2009-01-29 | Renesas Technology Corp | 不揮発性半導体記憶装置およびその動作方法 |
US9478670B2 (en) | 2012-09-05 | 2016-10-25 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor storage device |
Also Published As
Publication number | Publication date |
---|---|
US20090065851A1 (en) | 2009-03-12 |
TWI300931B (en) | 2008-09-11 |
US20070290273A1 (en) | 2007-12-20 |
US8149628B2 (en) | 2012-04-03 |
US7463530B2 (en) | 2008-12-09 |
TW200802380A (en) | 2008-01-01 |
KR20070120887A (ko) | 2007-12-26 |
JP5367222B2 (ja) | 2013-12-11 |
KR100919891B1 (ko) | 2009-09-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5367222B2 (ja) | 不揮発性メモリ素子の動作方法 | |
US8860124B2 (en) | Depletion-mode charge-trapping flash device | |
US7433243B2 (en) | Operation method of non-volatile memory | |
US20080001204A1 (en) | Non-volatile memory device and method for fabricating the same | |
KR100944649B1 (ko) | 비휘발성 메모리 및 그 형성 방법 | |
TWI413261B (zh) | 半導體裝置 | |
US8531885B2 (en) | NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers | |
JP2008270343A (ja) | 不揮発性半導体記憶装置 | |
US20100163965A1 (en) | Flash memory device and manufacturing method of the same | |
US8687424B2 (en) | NAND flash memory of using common P-well and method of operating the same | |
US6801456B1 (en) | Method for programming, erasing and reading a flash memory cell | |
US7652320B2 (en) | Non-volatile memory device having improved band-to-band tunneling induced hot electron injection efficiency and manufacturing method thereof | |
KR100706071B1 (ko) | 단일비트 비휘발성 메모리셀 및 그것의 프로그래밍 및삭제방법 | |
US20060268607A1 (en) | Operation method of non-volatile memory structure | |
JP2006222367A (ja) | 不揮発性半導体メモリ装置、駆動方法、及び製造方法 | |
US7772618B2 (en) | Semiconductor storage device comprising MIS transistor including charge storage layer | |
EP1870904B1 (en) | Operating method of non-volatile memory device | |
JP2004158614A (ja) | 不揮発性半導体メモリ装置およびそのデータ書き込み方法 | |
US20060226467A1 (en) | P-channel charge trapping memory device with sub-gate | |
US7859912B2 (en) | Mid-size NVM cell and array utilizing gated diode for low current programming | |
JP2006236424A (ja) | 不揮発性メモリデバイス、および、その電荷注入方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20091112 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20100119 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120808 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120816 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121107 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130628 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130809 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130826 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130911 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5367222 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |