JP2007508698A - 有機ケイ酸塩ガラスについての一酸化二窒素剥脱方法 - Google Patents

有機ケイ酸塩ガラスについての一酸化二窒素剥脱方法 Download PDF

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Publication number
JP2007508698A
JP2007508698A JP2006534260A JP2006534260A JP2007508698A JP 2007508698 A JP2007508698 A JP 2007508698A JP 2006534260 A JP2006534260 A JP 2006534260A JP 2006534260 A JP2006534260 A JP 2006534260A JP 2007508698 A JP2007508698 A JP 2007508698A
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Prior art keywords
layer
photoresist
osg
stripping
organic
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Pending
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JP2006534260A
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English (en)
Japanese (ja)
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JP2007508698A5 (enExample
Inventor
アナプラゲイダ，ラオ
ツー，ヘレン
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Lam Research Corp
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Lam Research Corp
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Application filed by Lam Research Corp filed Critical Lam Research Corp
Publication of JP2007508698A publication Critical patent/JP2007508698A/ja
Publication of JP2007508698A5 publication Critical patent/JP2007508698A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP2006534260A 2003-10-08 2004-10-05 有機ケイ酸塩ガラスについての一酸化二窒素剥脱方法 Pending JP2007508698A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/680,895 US7202177B2 (en) 2003-10-08 2003-10-08 Nitrous oxide stripping process for organosilicate glass
PCT/US2004/032793 WO2005038892A1 (en) 2003-10-08 2004-10-05 A nitrous oxide stripping process for organosilicate glass

Publications (2)

Publication Number Publication Date
JP2007508698A true JP2007508698A (ja) 2007-04-05
JP2007508698A5 JP2007508698A5 (enExample) 2007-10-18

Family

ID=34422202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006534260A Pending JP2007508698A (ja) 2003-10-08 2004-10-05 有機ケイ酸塩ガラスについての一酸化二窒素剥脱方法

Country Status (7)

Country Link
US (1) US7202177B2 (enExample)
EP (1) EP1671363A4 (enExample)
JP (1) JP2007508698A (enExample)
KR (1) KR101197070B1 (enExample)
CN (1) CN100426469C (enExample)
TW (1) TW200523689A (enExample)
WO (1) WO2005038892A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190070859A (ko) * 2017-12-13 2019-06-21 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법

Families Citing this family (9)

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Publication number Priority date Publication date Assignee Title
US20050136681A1 (en) * 2003-12-23 2005-06-23 Tokyo Electron Limited Method and apparatus for removing photoresist from a substrate
KR100666881B1 (ko) * 2005-06-10 2007-01-10 삼성전자주식회사 포토레지스트 제거 방법 및 이를 이용한 반도체 소자의제조 방법.
JP5005702B2 (ja) * 2005-11-17 2012-08-22 エヌエックスピー ビー ヴィ 湿度センサー
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
US8283255B2 (en) * 2007-05-24 2012-10-09 Lam Research Corporation In-situ photoresist strip during plasma etching of active hard mask
US20110226280A1 (en) * 2008-11-21 2011-09-22 Axcelis Technologies, Inc. Plasma mediated ashing processes
US20100130017A1 (en) * 2008-11-21 2010-05-27 Axcelis Technologies, Inc. Front end of line plasma mediated ashing processes and apparatus
CN101996934B (zh) * 2009-08-20 2012-07-18 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
CN115799028B (zh) * 2021-09-10 2025-12-05 长鑫存储技术有限公司 半导体结构的制备方法及半导体结构

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JP2000183040A (ja) * 1998-12-15 2000-06-30 Canon Inc 有機層間絶縁膜エッチング後のレジストアッシング方法
WO2002003426A2 (en) * 2000-06-30 2002-01-10 Lam Research Corporation Process for the post etch stripping of photoresist with hydrogen
JP2003045969A (ja) * 2001-07-12 2003-02-14 Samsung Electronics Co Ltd デュアルダマシン工程を利用した配線形成方法
JP2003092349A (ja) * 2001-09-18 2003-03-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6617257B2 (en) * 2001-03-30 2003-09-09 Lam Research Corporation Method of plasma etching organic antireflective coating
JP2003303880A (ja) * 2002-04-10 2003-10-24 Nec Corp 積層層間絶縁膜構造を利用した配線構造およびその製造方法

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US111041A (en) * 1871-01-17 Improvement in hay-tedders
US5126231A (en) * 1990-02-26 1992-06-30 Applied Materials, Inc. Process for multi-layer photoresist etching with minimal feature undercut and unchanging photoresist load during etch
US5910453A (en) * 1996-01-16 1999-06-08 Advanced Micro Devices, Inc. Deep UV anti-reflection coating etch
US5970376A (en) * 1997-12-29 1999-10-19 Taiwan Semiconductor Manufacturing Company, Ltd. Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer
JP4221847B2 (ja) * 1999-10-25 2009-02-12 パナソニック電工株式会社 プラズマ処理装置及びプラズマ点灯方法
US6323121B1 (en) * 2000-05-12 2001-11-27 Taiwan Semiconductor Manufacturing Company Fully dry post-via-etch cleaning method for a damascene process
JP2002118087A (ja) * 2000-06-29 2002-04-19 Dms Co Ltd 紫外線照査装置
US6413877B1 (en) * 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
US6514860B1 (en) * 2001-01-31 2003-02-04 Advanced Micro Devices, Inc. Integration of organic fill for dual damascene process
US6777344B2 (en) 2001-02-12 2004-08-17 Lam Research Corporation Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications
US6566283B1 (en) * 2001-02-15 2003-05-20 Advanced Micro Devices, Inc. Silane treatment of low dielectric constant materials in semiconductor device manufacturing
US20020139771A1 (en) * 2001-02-22 2002-10-03 Ping Jiang Gas switching during an etch process to modulate the characteristics of the etch
US6498112B1 (en) * 2001-07-13 2002-12-24 Advanced Micro Devices, Inc. Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films
US6696222B2 (en) * 2001-07-24 2004-02-24 Silicon Integrated Systems Corp. Dual damascene process using metal hard mask
US7253112B2 (en) * 2002-06-04 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene process
JP2004079901A (ja) * 2002-08-21 2004-03-11 Nec Electronics Corp 半導体装置及びその製造方法
US6720256B1 (en) * 2002-12-04 2004-04-13 Taiwan Semiconductor Manufacturing Company Method of dual damascene patterning
US6916697B2 (en) * 2003-10-08 2005-07-12 Lam Research Corporation Etch back process using nitrous oxide

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JP2000183040A (ja) * 1998-12-15 2000-06-30 Canon Inc 有機層間絶縁膜エッチング後のレジストアッシング方法
WO2002003426A2 (en) * 2000-06-30 2002-01-10 Lam Research Corporation Process for the post etch stripping of photoresist with hydrogen
US6617257B2 (en) * 2001-03-30 2003-09-09 Lam Research Corporation Method of plasma etching organic antireflective coating
JP2003045969A (ja) * 2001-07-12 2003-02-14 Samsung Electronics Co Ltd デュアルダマシン工程を利用した配線形成方法
JP2003092349A (ja) * 2001-09-18 2003-03-28 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003303880A (ja) * 2002-04-10 2003-10-24 Nec Corp 積層層間絶縁膜構造を利用した配線構造およびその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190070859A (ko) * 2017-12-13 2019-06-21 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법
JP2019106490A (ja) * 2017-12-13 2019-06-27 東京エレクトロン株式会社 半導体装置の製造方法
CN110034063A (zh) * 2017-12-13 2019-07-19 东京毅力科创株式会社 半导体装置的制造方法
US11495490B2 (en) 2017-12-13 2022-11-08 Tokyo Electron Limited Semiconductor device manufacturing method
CN110034063B (zh) * 2017-12-13 2023-10-20 东京毅力科创株式会社 半导体装置的制造方法
KR102642184B1 (ko) * 2017-12-13 2024-03-04 도쿄엘렉트론가부시키가이샤 반도체 장치의 제조 방법

Also Published As

Publication number Publication date
KR101197070B1 (ko) 2012-11-06
US20050079710A1 (en) 2005-04-14
WO2005038892A1 (en) 2005-04-28
EP1671363A1 (en) 2006-06-21
CN1864249A (zh) 2006-11-15
CN100426469C (zh) 2008-10-15
US7202177B2 (en) 2007-04-10
EP1671363A4 (en) 2010-01-13
TW200523689A (en) 2005-07-16
KR20060107758A (ko) 2006-10-16

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