CN110034063A - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- CN110034063A CN110034063A CN201811526091.7A CN201811526091A CN110034063A CN 110034063 A CN110034063 A CN 110034063A CN 201811526091 A CN201811526091 A CN 201811526091A CN 110034063 A CN110034063 A CN 110034063A
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- film
- hole
- dielectric constant
- low dielectric
- groove
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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Abstract
本发明提供一种半导体装置的制造方法。提供如下技术:在制造半导体装置时,在对作为层间绝缘膜的由SiOC膜形成的多孔质的低介电常数膜进行蚀刻时能够抑制低介电常数膜的损伤。对晶圆W进行以异氰酸酯和胺为原料、通过蒸镀聚合生成聚脲的成膜处理。由此在低介电常数膜(20)的孔部(21)内埋入聚脲。而且,先形成通孔的情况下,在低介电常数膜(20)形成通孔(201)后、且形成沟槽(202)前在通孔(201)内埋入保护用的填充物(100)。作为填充物(100)可列举出聚脲。先形成沟槽的情况下,形成沟槽(202),形成通孔(201)后,去除沟槽(202)内的掩模时,通过低介电常数膜(20)的孔部内的聚脲的存在来保护低介电常数膜。
Description
技术领域
本发明涉及可抑制对用于制造半导体装置的形成于基板上的多孔质的低介电常数膜进行形成用于埋入布线的通孔及沟槽的工序时的损伤的技术。
背景技术
经多层化的半导体装置的制造中,作为为了提高工作速度而减小层间绝缘膜的寄生电容的方法,使用了多孔质的低介电常数膜。作为这种膜,例如可列举出包含硅、碳、氧及氢、且具有Si-C键的SiOC膜。对于SiOC膜,为了埋入作为布线材料的例如铜,使用抗蚀剂掩模及下层掩模,利用作为CF系的气体的例如CF4气体的等离子体进行蚀刻,接着利用氧气的等离子体进行抗蚀剂掩模的灰化。
然而,对SiOC膜进行蚀刻、灰化等的等离子体处理的情况下,在暴露于等离子体中的SiOC膜的露出面、即凹部的侧壁及底面,例如Si-C键被等离子体切断从而C从膜中脱离。因C的脱离而生成了不饱和化学键的Si在该状态下不稳定,因此之后与例如大气中的水分等结合而形成Si-OH。
这样通过等离子体处理,蚀刻气体等扩散到多孔质的SiOC膜的孔隙部,SiOC膜因蚀刻气体而受到损伤。该损伤层的碳的含量降低,因此介电常数会降低。布线图案的线宽的微细化、及布线层、绝缘膜等的薄膜化正在进展,因此膜的表面部对晶圆整体带来的影响的比例变大,因此SiOC膜的介电常数的降低成为半导体装置的特性脱离设计值的要素之一。
专利文献1中记载了如下技术:在基板上的多孔质的低介电常数膜的孔部事先埋入PMMA(丙烯酸类树脂),对低介电常数膜进行蚀刻等处理后,对基板进行加热,供给溶剂,进而供给微波,从而将PMMA去除。但是为了去除PMMA,需要利用等离子体花费20分钟左右长的时间,另外必需将基板加热至400℃以上的温度,因此存在给已经形成于基板上的元件部分带来不良影响的担心大的问题。
另外,非专利文献1中,对于基于树脂的热分解的概念,公开了若树脂的去除温度降低,则该树脂的耐热温度也降低。其中,公开了PMMA唯一在布线工序中可容许的温度的400℃下能够热去除(Thermal unstuff),但PMMA的热稳定性降低到250℃。这意味着在利用PMMA的保护工序中对PMMA施加250℃以上的温度时,PMMA膜会变质,因此不能作为保护膜使用。
因此,非专利文献1中所记载的技术并不如本发明那样,即使进行超过了保护膜的去除温度的热工序,该保护膜也作为保护膜而具有功能。
现有技术文献
专利文献
专利文献1:美国专利第9,414、445(第2栏第23行~29行、第13栏第51行~53行、权利要求3)
非专利文献1:PESM2014,Grenoble(France)“Low damage integration ofultralow-k porousorganosilicate glasses by Pore-Stuffing approach”p-11http://search.yahoo.co.jp/r/FOR=lnHXYipV3iiHPJ8Ddulpn9J0AKPQKNPWEP9nzhy.AiW7ZSfYxo79p7jA3xOdeEcedQqGRKkEAYq90SDWeAT5IUsEfgiLpbHgxS8DD0kYKkIGqb8pnApsZ5xT8UlA4Ot.KLFnrDpecdEGg86FqBcBKfCEqY3PqzBYQ9KfooXg6Xo2Dt8m5oGdCpp7WKLDFTHa2Wz9s8jHjCqu5OmSbDaj4USJp6MbORAH65KsDgl9EH7ns610ZIvWgfumVXoh5_wErVR4FCMd3wt0zOsKjLp2_AwFsYkxMFmOJYRiMzULCQ15RFal6R4A5NMV7Q--/_ylt=A2RCnn0EZ9hYv3IANE2DTwx.;_ylu=X3oDMTEyY3ZldGU5BHBvcwMxBHNlYwNzcgRzbGsDdGl0bGUEdnRpZANqcDAwNDk-/SIG=15ks2kk9s/EXP=1490677956/**http%3A//pesm2014.insight-outside.fr/presentations/Sesssion6-2-PoreStuffing_PESM2014_Liping-Zhang_finalv.pdf%23search=%27PESM2014%252C%2BGrenoble%2BL.%2BZhanga%27
发明内容
发明要解决的问题
本发明是鉴于这样的实际情况而作出的,其目的在于,提供在制造半导体装置时,在作为多孔质的低介电常数膜的层间绝缘膜中形成布线用的凹部时能够抑制层间绝缘膜的损伤的技术。
用于解决问题的方案
本发明的半导体装置的制造方法在形成于基板上的作为层间绝缘膜的多孔质的低介电常数膜中通过蚀刻形成沟槽和通孔,其特征在于,所述制造方法包括如下工序:
埋入工序,对前述低介电常数膜供给聚合用的原料,在前述低介电常数膜内的孔部埋入具有脲键的聚合物;
对前述低介电常数膜进行蚀刻,形成通孔的工序;
接着,在前述通孔内埋入包含有机物的保护用的填充物的工序;
然后,对前述低介电常数膜进行蚀刻,形成沟槽的工序;
接着,去除前述填充物的工序;和,
形成前述沟槽后,对前述基板进行加热而将前述聚合物解聚,由此从前述低介电常数膜内的孔部将前述聚合物去除的工序,
在前述孔部埋入前述聚合物的工序在形成前述沟槽之前进行。
另一发明的半导体装置的制造方法在形成于基板上的作为层间绝缘膜的多孔质的低介电常数膜中通过蚀刻形成沟槽和通孔,其特征在于,所述制造方法包括如下工序:
埋入工序,对前述低介电常数膜供给聚合用的原料,在前述低介电常数膜内的孔部埋入具有脲键的聚合物;
在前述低介电常数膜的表面形成沟槽用的掩模的工序;
使用前述沟槽用的掩模,对前述低介电常数膜进行蚀刻,形成沟槽的工序;
接着,在前述沟槽内形成通孔用的掩模的工序;
然后,使用前述通孔用的掩模,对前述沟槽的底部进行蚀刻,形成通孔的工序;
接着,去除前述通孔用的掩模的工序;和,
形成前述沟槽后,对前述基板进行加热而将前述聚合物解聚,由此从前述低介电常数膜内的孔部将前述聚合物去除的工序。
发明的效果
本发明中,对低介电常数膜供给聚合用的原料,在低介电常数膜内的孔部埋入具有脲键的聚合物(聚脲),在蚀刻后对基板进行加热而将聚合物解聚。因此,在进行低介电常数膜的蚀刻时被聚合物保护。而且在形成通孔后、形成沟槽前埋入包含有机物的填充物。因此在蚀刻时保护低介电常数膜免受活性物质影响,因此可抑制损伤的产生。
另一发明中,对低介电常数膜供给聚合用的原料,在低介电常数膜内的孔部埋入具有脲键的聚合物(聚脲),在蚀刻后对基板进行加热而将聚合物解聚。因此在进行低介电常数膜的蚀刻时被聚合物保护。而且在形成沟槽后,形成了通孔,形成通孔后,将用于形成该通孔而形成于沟槽内的掩模去除时,在低介电常数膜内埋入聚脲,因此可抑制用于去除掩模的等离子体带来的损伤。
附图说明
图1为示出本发明的实施方式的概要的说明图。
图2为示出本发明的第1实施方式的制造工序的一部分的说明图。
图3为示出本发明的第1实施方式的制造工序的一部分的说明图。
图4为示出本发明的第1实施方式的制造工序的一部分的说明图。
图5为示出本发明的第1实施方式的制造工序的一部分的说明图。
图6为示出通过基于共聚的反应生成具有脲键的聚合物的情况的说明图。
图7为示出异氰酸酯的一例的分子结构的分子结构图。
图8为示出具有脲键的聚合物形成低聚物的反应的说明图。
图9为示出使用仲胺生成具有脲键的聚合物的情况的说明图。
图10为示出使具有脲键的单体交联而生成具有脲键的聚合物的情况的说明图。
图11为示出用于使异氰酸酯与胺各自以蒸气形式反应而生成具有脲键的聚合物的装置的截面图。
图12为示出用于对形成有聚脲膜的基板进行加热的加热装置的截面图。
图13为示出第1实施方式的变形例的制造工序的一部分的说明图。
图14为示出第1实施方式的变形例的制造工序的一部分的说明图。
图15为示出第1实施方式的变形例的制造工序的一部分的说明图。
图16为示出第1实施方式的变形例的制造工序的一部分的说明图。
图17为示出本发明的第2实施方式的制造工序的一部分的说明图。
图18为示出本发明的第2实施方式的制造工序的一部分的说明图。
图19为示出第2实施方式的变形例的制造工序的一部分的说明图。
图20为示出第2实施方式的变形例的制造工序的一部分的说明图。
图21为示出第2实施方式的变形例的制造工序的一部分的说明图。
图22为示出第2实施方式的变形例的制造工序的一部分的说明图。
图23为示出第2实施方式的变形例的制造工序的一部分的说明图。
图24为示出对埋入聚脲前的低介电常数膜的表面部通过XPS得到的组成的图。
图25为示出对埋入聚脲后的低介电常数膜的表面部通过XPS得到的组成的图。
图26为示出对埋入聚脲后的低介电常数膜的表面部通过XPS得到的组成的图。
图27为示出对埋入聚脲后的低介电常数膜的表面部通过XPS得到的组成的图。
图28为示出低介电常数膜的聚脲的埋入前后及加热处理后的吸光度的特性图。
附图标记说明
11 下层侧的层间绝缘膜
12 铜布线
13 蚀刻终止膜
W 半导体晶圆
20 低介电常数膜
21 孔部
31 硅氧化膜
32 硬掩模
33 图案掩模
34 填充物
35 阻挡层
36 铜布线
100 填充物
201 通孔
202 沟槽
具体实施方式
[本发明的实施方式的概要]
半导体装置中,多个形成有集成电路的层层叠的情况下,必需在层间绝缘膜形成用于将下层侧的电路和上层侧的电路连接的布线所埋入的通孔(导通孔)、和成为各层的集成电路的一部分的布线所埋入的沟槽(槽部)。
在形成通孔及沟槽时,有在层间绝缘膜形成通孔、接着形成沟槽的方法;和,形成沟槽、接着形成通孔的方法。本申请说明书中,将先形成通孔的方法称为先通孔(viafront),先形成沟槽的方法称为先沟槽(trench front)。
图1为极为示意性地示出本发明的实施方式的概要的图,示出了先通孔及先沟槽的方法。本发明的实施方式中,使用多孔质的低介电常数膜20作为层间绝缘膜,在低介电常数膜20的孔部内埋入聚脲。作为在孔部内埋入有聚脲的状态的表示,对低介电常数膜20标记点。由20a表示的部位为示意性地示出低介电常数膜20的下层侧的层的部位。
通常进行的先通孔的方法中,形成通孔201、接着形成沟槽202,但本发明的实施方式中,在形成通孔201后、形成沟槽202前,如由白色箭头所示工序的插入那样,在通孔201内埋入保护用的填充物100。通孔201表示比沟槽的底面更靠近下方侧的部分的孔,在本说明书中,方便起见,在比通孔更靠近上方侧、且该通孔的投影区域的孔的部分也称为通孔,表示为符号201。
在先沟槽的方法中,形成沟槽202、接着在沟槽202内形成通孔用的蚀刻掩模101、使用该掩模101对低介电常数膜20的底部进行蚀刻而形成通孔201。然后,通过蚀刻或灰化将沟槽202内的掩模101去除。
[第1实施方式]
本发明的第1实施方式为应用于先通孔的方法的方法。图2~图5为阶段性地示出在下层侧的电路部分形成上层侧的电路部分的情况的说明图,11为下层侧的例如层间绝缘膜、12为埋入至层间绝缘膜11的作为布线材料的铜布线、13为具有蚀刻时的终止的功能的蚀刻终止膜。蚀刻终止膜13由例如SiC(碳化硅)、SiCN(碳氮化硅)等形成。
在蚀刻终止膜13上形成有作为层间绝缘膜的低介电常数膜20。低介电常数膜20在该例中使用SiOC膜,SiOC膜例如通过对DEMS(二乙氧基甲基硅烷,Diethoxymethylsilane)进行等离子体化并通过CVD法进行成膜。低介电常数膜20为多孔质,附图中极为示意性地示出了低介电常数膜20内的孔部21。需要说明的是,关于下层侧的层间绝缘膜11,也可以使用SiOC膜。
本实施方式的方法中,如图2的(a)所示,从在作为基板的半导体晶圆(以下称为晶圆)的表面形成下层侧的电路部分、并在该电路部分上形成有低介电常数膜20的状态开始处理。
接着,如图2的(b)所示,在低介电常数膜20的表面在例如真空气氛下、300℃的工艺温度下通过CVD(化学气相沉积,Chemical Vapor Deposition)将硅氧化膜31成膜。硅氧化膜31例如通过有机系的硅原料的蒸气与氧或臭氧等氧化气体的反应来生成。硅氧化膜31在后述的蚀刻时发挥作为图案掩模(硬掩模)的一部分的作用、并且在后述的硬掩模32的蚀刻时还发挥保护低介电常数膜20的作用。接着,如该图所示,通过公知的方法形成与沟槽对应的部位开口的例如由TiN(氮化钛)膜形成的蚀刻用的图案掩模即硬掩模32。
然后,利用例如将CH3F气体活化(等离子体化)而成的气体对硅氧化膜31进行蚀刻(图2的(c)),如下利用作为埋入材料的具有脲键的聚合物(聚脲)填埋低介电常数膜20内的孔部21(图2的(d))。在图2中,方便起见用“斜线”表示孔部21被聚脲填埋的状态。埋入至低介电常数膜20内的孔部21的聚脲发挥保护作为被保护膜的低介电常数膜20免受后述的等离子体处理中的等离子体的影响的作用。
聚脲膜例如如图6所示可以使用异氰酸酯和胺通过共聚来生成。R例如为烷基(直链状烷基或环状烷基)或芳基,n为2以上的整数。
作为异氰酸酯,例如可以使用脂环式化合物、脂肪族化合物、芳香族化合物等。作为脂环式化合物,例如如图7的(a)所示,可以使用1,3-双(异氰酸根合甲基)环己烷(H6XDI)。另外作为脂肪族化合物,如图7的(b)所示,可以使用例如六亚甲基二异氰酸酯。
作为胺,例如可以使用1,3-双(氨基甲基)环己烷(H6XDA)。
将用于使原料单体以气体形式反应而将聚脲成膜(蒸镀聚合)的CVD装置示于图11。70为划分真空气氛的真空容器。71a、72a为以液体形式收纳作为各个原料单体的异氰酸酯及胺的原料供给源,异氰酸酯的液体及胺的液体被夹设于供给管71b、72b的气化器71c、72c气化,各蒸气被导入至作为气体排出部的喷头73。喷头73在下面形成有多个排出孔,以将异氰酸酯的蒸气及胺的蒸气从各自的排出孔排出到处理气氛的方式构成。作为基板的表面进行了加工的半导体晶圆W被载置于具备加热机构的载置台74。
关于在低介电常数膜20的孔部21埋入聚脲的方法,可以采用对所述的搭载有电路部分的基板即半导体晶圆(以下简称为“晶圆”)W交替供给异氰酸酯的蒸气和胺的蒸气的方法。该情况下,可以为如下方法:停止异氰酸酯的蒸气的供给,用氮气吹扫真空容器70内后供给胺的蒸气,接着停止胺的蒸气的供给,用氮气吹扫真空容器70内后供给异氰酸酯的蒸气。或者也可以为如下方法:停止一种蒸气的供给后,不插入吹扫工序,接着供给另一蒸气,停止另一蒸气的供给后,不插入吹扫工序,接着供给一种蒸气。另外也可以为同时向晶圆W供给异氰酸酯的蒸气和胺的蒸气的方法。
对于交替供给异氰酸酯的蒸气和胺的蒸气的所述2种方法中的前段的方法(在一种气体的供给和另一气体的供给之间插入吹扫工序的方法),不在低介电常数膜20的表面将聚脲成膜地埋入孔部21内。另外对于后段的方法(不在一种气体的供给和另一气体的供给之间插入吹扫工序的方法),聚脲埋入至孔部21,但在除低介电常数膜20以外的晶圆W的表面(硬掩模32上)聚脲也成膜。需要说明的是,虽然该现象被记载于后述的评价试验中,但可以认为在选定供给循环数等参数值的情况下会发生。
采用后段的方法的情况下,将晶圆W加热至聚脲解聚的温度,将硬掩模32的表面的聚脲去除,由此得到图2的(d)所示的状态。对于聚脲,聚合与解聚的可逆的平衡反应成立,若温度变高,则解聚聚合成为主导。因此,若发生解聚,则生成的单体随着时间的经过发生气化。例如对于200℃、250℃、300℃的各温度,聚脲消失为止的时间在300℃的情况下最短。
因此,通过选择温度和时间,能够仅在低介电常数膜20内保留聚脲。
使用异氰酸酯的蒸气及胺的蒸气的方法中,将晶圆W的温度设定为室温到比聚脲会解聚的温度稍微低的温度的温度范围,例如在20℃~200℃的温度范围促进聚合反应。
进而如图8的(a)~(d)所示,可以使用单官能性分子作为原料单体。进而如图9的(a)、(b)所示,可以使用异氰酸酯和仲胺,该情况下,生成的聚合物中所含的键也是脲键。
然后,可以使具备脲键的原料单体聚合而得到聚脲膜。图10示出这样的例子,对原料单体照射光、例如紫外线而赋予光能,由此引起聚合而生成聚脲膜。该情况下,边向晶圆W供给原料单体边赋予光能来进行。
这样在低介电常数膜20的孔部21埋入聚脲后,形成与通孔对应的部位开口的由SOC(自旋碳,Spin On Carbon)形成的通孔用的图案掩模33(图3的(e)),对低介电常数膜20进行蚀刻,形成通孔201(图3的(f))。SOC为通过旋转涂布进行涂布的以碳为主成分的涂布膜,使用抗蚀剂作为图案掩模而形成。
作为对低介电常数膜20该例中为SiOC膜进行蚀刻的方法,可以利用将C6F6气体等离子体化而得到的等离子体来进行,该情况下,可以进而添加微量的氧气。
接着在通孔201内埋入包含有机物的保护用的填充物、该例中为包含聚脲的保护用的填充物34。埋入填充物34(聚脲)的工序通过对搭载有电路部分的晶圆如所述那样在真空气氛下交替供给例如异氰酸酯的蒸气和胺的蒸气来进行,由此聚脲埋入到通孔201内而形成填充物34,并且在通孔201以外的图案掩模33的表面也成膜(图3的(g))。然后,如所述那样将晶圆加热至聚脲会解聚的温度,将在通孔201以外的图案掩模33的表面成膜的聚脲(聚脲膜)去除(图3的(h))。
接着,将由SOC形成的图案掩模33利用例如将氧气等离子体化而得到的等离子体进行灰化(蚀刻)而去除(图4的(i))。此时埋入至图案掩模33的孔部内的聚脲也与SOC一起被该等离子体蚀刻而去除。
进而使用作为沟槽用的掩模的硅氧化膜31及硬掩模32,对低介电常数膜20进行蚀刻,形成沟槽202(图4的(j)。作为对低介电常数膜20、该例中为SiOC膜进行蚀刻的方法,可以利用将C6F6气体等离子体化而得到的等离子体来进行,该情况下,可以进而添加微量的氧气。通过该蚀刻,包含聚脲的填充物34也与低介电常数膜20一起被蚀刻。需要说明的是,由于聚脲的蚀刻速度比低介电常数膜20的蚀刻速度慢,因此在将低介电常数膜20蚀刻至预定深度时成为填充物34从沟槽202的底部稍微突出的状态。因此可以利用例如将氧气等离子体化而得到的等离子体进行灰化,将突出的填充物34去除,从而将沟槽202平坦化。
接着,若将晶圆加热至聚脲会解聚的温度例如350℃,则解聚为胺并蒸发,如图4的(k)所示,包含聚脲的填充物34被去除。对晶圆进行加热时,为了不给已经形成于晶圆上的元件部分、特别是铜布线带来不良影响,优选在不足400℃例如390℃以下、例如300~350℃下进行加热。对于进行聚脲的解聚的时间、例如在300℃~400℃下加热的时间,从抑制对元件的热损伤的观点出发,例如优选5分钟以下。
对晶圆进行加热的处理例如可以如图12所示,通过将晶圆载置于处理容器51内的载置台52,利用灯罩53内的红外线灯54对晶圆进行加热来进行。图12中,55为透过窗、56为用于供给氮气的供给管、57为排气管。对于处理气氛,例如可以边供给作为非活性气体的氮气边在真空气氛下进行(该情况下,真空排气机构75与排气管57连接,处理容器51使用真空容器),也可以在常压气氛下进行。
另外,作为加热机构,不限于红外线灯54,也可以为设置于载置台52的加热器。
然后去除填充物34后,对通孔201的底部的蚀刻终止膜13进行蚀刻而去除(图4的(l))。对于该蚀刻,在蚀刻终止膜13为例如SiC膜的情况下,可以利用例如将CF4气体等离子体化而得到的等离子体来进行。
其后,在通孔201及沟槽202的内表面将用于防止作为后述的导电路的铜扩散至层间绝缘膜20的阻挡层、例如由Ti和TiON的层叠膜形成的阻挡层35成膜(图5的(m))。然后,在通孔201及沟槽202埋入铜36,通过CMP(化学机械研磨,Chemical Mechanical Polishing)将剩余的铜36、阻挡层35、硅氧化膜31及硬掩模32去除,形成铜布线36(使用与铜相同的符号)(图5的(n))。接着,将晶圆加热至聚脲会解聚的温度例如350℃,将埋入至低介电常数膜20的孔部21的聚脲去除(图5的(o)),这样形成上层的电路部分。
对于将埋入至低介电常数膜20的孔部21的聚脲去除的工序,不限于该例,例如可以在对蚀刻终止膜13进行蚀刻而去除后(图4的(l))、将阻挡层35成膜前进行。
根据第1实施方式,对低介电常数膜20供给聚合用的原料,在低介电常数膜20内的孔部21埋入具有脲键的聚脲,在蚀刻后对晶圆进行加热,使聚脲解聚。因此,在进行低介电常数膜20的蚀刻时被聚脲(聚合物)保护。然后,在形成通孔201后、形成沟槽202前,在通孔201埋入包含聚脲的填充物,因此在形成沟槽202时保护通孔201的内周面免受蚀刻气体影响。因此,与在孔部21埋入聚合物相辅,保护低介电常数膜免受蚀刻气体影响,可抑制低介电常数膜中的损伤的产生。
以下,关于第1实施方式的变形例进行记载。
对于图13及图14所示的变形例,利用硬掩模32在硅氧化膜31形成与沟槽对应的开口的工序之前将聚脲埋入低介电常数膜20的孔部21,这点与第1实施方式不同。即形成低介电常数膜20后,对晶圆如所述那样对聚脲进行真空蒸镀的处理,在低介电常数膜20的孔部21埋入聚脲(图13的(a)、(b))。其后,在低介电常数膜20上将硅氧化膜31成膜,接着在硅氧化膜31上形成硬掩模32(图13的(c)),进而由SOC形成通孔用的图案掩模33(图13的(d))。
接着,利用将CH3F气体等离子体化而得到的等离子体对硅氧化膜31进行蚀刻,接着利用将C6F6气体等离子体化而得到的等离子体对低介电常数膜20进行蚀刻(图14的(e)),在这样形成的与通孔201相对应的凹部,与第1实施方式同样地操作,埋入包含聚脲的填充物34(图14的(f))。进而利用将氧气等离子体化而得到的等离子体对图案掩模33进行灰化,并且对埋入至图案掩模33的孔内的聚脲进行蚀刻而去除(图14的(g))。然后,利用将CH3F气体等离子体化而成的等离子体对硅氧化膜31进行蚀刻而去除。此时,成为如下状态:埋入至硅氧化膜31的孔内的聚脲(填充物34的前端部)未被蚀刻,而从低介电常数膜20的表面突出。然后进而与第1实施方式同样地操作,对低介电常数膜20进行蚀刻,形成沟槽201(图14的(h))。此时形成填充物34也被蚀刻、并从沟槽202的底部稍微突出的状态,但如图4的(j)所说明的,通过稍微进行灰化而将填充物34的突出部分去除,沟槽202的底面变平坦。
第1实施方式中,对低介电常数膜20上的硅氧化膜31进行蚀刻时,低介电常数膜20的表面暴露于蚀刻气体,但对于图13、图14的方法,对硅氧化膜31进行蚀刻时,聚脲已经埋入至低介电常数膜20的孔部21内,因此没有在低介电常数膜20产生由蚀刻气体带来的损伤的担心。
对于图15所示的变形例,从第1实施方式的图3的(h)的状态向图3的(i)的状态转移间的步骤与第1实施方式不同。图15的(a)所示的状态与图3的(h)所示的状态相对应。该变形例中,填充物34从图案掩模33的开口埋入至低介电常数膜20内的通孔201后,将晶圆加热至比作为填充物34的聚脲的解聚的温度高的温度,将图案掩模33的开口内的聚脲去除(图15的(b))。然后,在晶圆的表面形成与图案掩模33相同的涂布膜即SOC(图15的(c)),其后将SOC膜去除(图15的(d))。图15的(d)与图3的(i)的状态相对应。
该情况下,在使填充物34的上表面露出至低介电常数膜20的表面的灰化工序中,去除对象的膜仅为SOC,因此可以期待不用担心产生聚脲的残渣等的优点。
另外,作为其他变形例,可列举出埋入除聚脲以外的材质、例如SOC作为埋入至通孔20的填充物的例子。作为这样的方法,可列举出在第1实施方式的图3的(h)的状态之后,在晶圆的表面形成SOC,在图3的(h)所示的孔内埋入SOC的例子。该情况下,将比低介电常数膜20更靠近上侧的部分的SOC去除后,通孔201内的填充物成为SOC,除了这点以外,形成与第1实施方式的图4的(i)相同的状态。在低介电常数膜20形成沟槽202时,预先在C6F6的气体中添加氧气,由此低介电常数膜20被蚀刻,其后,利用将氧气等离子体化而成的等离子体,对作为填充物34的SOC进行灰化,由此形成与第1实施方式的图4的(k)相同的状态。
对于图16所示的变形例,在低介电常数膜20的孔部21埋入聚脲的时机与在低介电常数膜20埋入填充物34的时机是同时,这点与第1实施方式不同。图16的(a)所示的状态与图2的(b)的状态相对应。该状态之后,如图16的(b)所示,在硅氧化膜31上形成形成有与通孔相对应的开口的由SOC形成的图案掩模33,接着对硅氧化膜31及低介电常数膜20进行蚀刻,形成通孔201。接着,对晶圆如第1实施方式所示那样进行通过蒸镀聚合将聚脲成膜的处理。此时,原料单体从通孔201进入低介电常数膜20内,在孔部21内埋入聚脲,并且在包括通孔201在内的孔内埋入包含聚脲的填充物34(图16的(c))。然后,通过解聚将图案掩模33及图案掩模33的开口内的聚脲去除,由此得到图16的(d)的状态。其后,使用硬掩模32对硅氧化膜31及低介电常数膜20依次进行蚀刻,由此形成与图4的(j)相同的状态。
[第2实施方式]
本发明的第2实施方式为应用于先沟槽的方法的方法。图17的(a)示出了在低介电常数膜20上形成有形成了与沟槽相对应的开口的硅氧化膜31及硬掩模32的层叠体、并且在低介电常数膜20的孔部21内埋入有聚脲的状态。聚脲的埋入可以是在前述层叠体形成了开口后的阶段,也可以是在低介电常数膜20上将硅氧化膜31成膜前的阶段。
然后,将前述层叠体作为掩模,对低介电常数膜20进行蚀刻,形成沟槽202(图17的(b))。接着,在晶圆的表面将聚脲膜41如所述那样成膜(图17的(c)),使聚脲膜41的上层部位解聚而使硬掩模32的表面露出(图17的(d))。然后,在晶圆的表面形成SOC膜33(方便起见,赋予与由SOC形成的图案掩模相同的符号),接着在该SOC膜33上形成包含图案加工用的防反射膜37的加工用掩模(图18的(e))。
加工用掩模可以通过利用将O2(氧)气体、CO2(二氧化碳)气体、NH3(氨)气体、或N2(氮)气体与H2(氢)气体的混合气体等离子体化而得到的等离子体对防反射膜37进行蚀刻来形成。
接着,使用所述的加工掩模,对SOC膜33及聚脲膜41利用例如将氧气等离子体化而得到的等离子体进行灰化(蚀刻),在与通孔201相对应的部位形成开口(图18的(f))。此时,形成沿沟槽202的内周面形成有聚脲膜41的状态。
接着,如所述那样利用例如将C6F6气体等离子体化而得到的等离子体作为蚀刻气体,对低介电常数膜20进行蚀刻,形成通孔201(图18的(g))。接着,利用将氧气等离子体化而得到的等离子体对图案掩模33进行灰化而去除,进而通过解聚将沿沟槽202的内周面形成的聚脲膜41去除(图18的(h))。
如所述那样将晶圆加热至聚脲会解聚的温度以上的温度,调整加热温度和加热时间,由此聚脲膜41发生解聚,但此时在低介电常数膜20中,在接近通孔201的内周面的部位,聚脲从孔部21脱落。其后的工序与第1实施方式同样地进行。
根据第2实施方式,与第1实施方式同样地,对低介电常数膜20供给聚合用的原料,在低介电常数膜20内的孔部21埋入聚脲,在蚀刻后对晶圆进行加热,使聚脲解聚。因此在进行低介电常数膜20的蚀刻时,低介电常数膜20被聚合物保护。即在该点上,具有与第1实施方式同样的效果。然后形成沟槽202后,用于形成该沟槽202内的通孔201的掩模由聚脲膜41形成,因此从沟槽202内将掩模去除时,能够通过基于加热的聚脲膜41的解聚来进行。因此能够抑制沟槽202的内壁的损伤。
以下记载第2实施方式的变形例。
图19的(a)为与图17的(b)相同的状态,在该状态的晶圆的表面将聚脲膜41成膜(图19的(b)),接着,使用例如由SOC形成的图案掩模,在与聚脲膜41的通孔201相对应的部位形成开口(图19的(c))。接着,将聚脲膜41作为掩模,在低介电常数膜20形成通孔201(图19的(d))。然后,对通孔201的底部的蚀刻终止膜13如所述那样进行蚀刻(图20的(e))。
其后,对晶圆进行加热,通过解聚而去除聚脲膜41,进而继续加热,通过解聚将埋入至低介电常数膜20的孔部21内的聚脲去除(图20的(f))。然后,如第1实施方式的图5的(m)、(n)所示,进行阻挡金属35的形成、相同布线36的形成。
另外,在该例中,由聚脲膜41形成用于蚀刻通孔201的掩模,但也可以由SOG膜代替聚脲膜41来形成掩模。该情况下,记载于图19的(b)~图20的(e)的聚脲膜41被替代为SOC膜。将SOC膜作为掩模的情况下,利用将氧气等离子体化而成的气体对SOC膜进行灰化,但由于在低介电常数膜20的孔部21内埋入有聚脲,因此可抑制该工序时的等离子体带来的损伤。
对图21、图22所示的变形例进行说明。该例中,在低介电常数膜20的孔部21埋入聚脲(图21的(a)、(b)),接着在低介电常数膜20上形成硅氧化膜31(图21的(c)),进而形成具备与沟槽相对应的开口的由TiN形成的硬掩模32。其后,在作为保护膜的硅氧化膜31上也形成与沟槽相对应的开口。然后,将硬掩模32及硅氧化膜31的层叠体作为掩模,对低介电常数膜20进行蚀刻,形成沟槽202(图21的(d))。
进而以在沟槽202埋入聚脲膜41的方式在晶圆上将聚脲膜41成膜(图22的(e))。其后,在聚脲膜41上层叠SOC膜,利用抗蚀剂进行图案化,使用在SOC膜形成有与通孔201相对应的开口的图案掩模33,对聚脲膜41进行蚀刻(图22的(f))。
接着,使用聚脲膜41及图案掩模33对低介电常数膜20进行蚀刻,形成通孔201(图22的(g))。接着如所述那样对图案掩模33进行灰化而去除,进而通过解聚去除聚脲膜41(图22的(h))。此后,例如进行与第1实施方式同样的工序。
图21、图22所示的变形例中,可以以在低介电常数膜20上层叠有形成有与沟槽202相对应的开口部的、硅氧化膜31及硬掩模32的层叠体的状态进行聚脲向低介电常数膜20的孔部21的埋入。另外,将前述层叠体作为掩模对低介电常数膜20进行蚀刻而形成沟槽202、接着将聚脲膜41埋入沟槽202时,可以同时进行聚脲向低介电常数膜20的孔部21的埋入。为了同时进行聚脲膜41向沟槽202的埋入与聚脲向孔部21内的埋入,由后述的评价试验也可以明确,通过例如2个阶段进行原料单体的真空蒸镀处理即可。该情况下,可以是第1阶段采用例如将异氰酸酯的蒸气和胺的蒸气如第1实施方式所述那样借助利用氮气的吹扫工序交替供给的方法,第2阶段采用例如同时供给异氰酸酯的蒸气和胺的蒸气的方法。
图23所示的变形例中,所述的图22的(g)的状态(形成有通孔201的状态)之后,在形成于图案掩模(SOC)33及聚脲膜41的凹部埋入聚脲(图23的(a))。其后,通过蚀刻将图案掩模33及图案掩模33内的聚脲去除(图23的(b)),接着通过解聚去除聚脲膜41。该例中,对图案掩模33进行灰化时,通孔201的内壁被聚脲膜41覆盖,因此能够抑制低介电常数膜20的损伤(图23的(c))。
实施例
[评价试验1]
对具有由SiOC形成的多孔质的低介电常数膜的基板,将作为异氰酸酯的H6XDI和作为胺的H6XDA交替地以气体的状态每3秒进行供给,并且在H6XDI的供给工序及H6XDA的供给工序中的一者结束后、且另一供给工序开始前进行12秒利用氮气进行吹扫的工序,实施进行100个循环的该循环的成膜处理。针对对该基板进行成膜处理前、进行成膜处理后的各个表面部,利用XPS(X射线光电子能谱,X-ray Photoelectron Spectroscopy)对组成进行研究,结果如图24及图25所示。
根据图24(成膜处理前)及图25(成膜处理后)可知,通过进行成膜处理,低介电常数膜内的C(碳)大幅增加,另外N(氮)也增加。因此可知,通过进行成膜处理,聚脲被埋入至低介电常数膜的孔部内。
[评价试验2]
对具有由SiOC形成的多孔质的低介电常数膜的基板,将H6XDI和H6XDA交替地以气体的状态每3秒进行供给,在H6XDI的供给工序及H6XDA的供给工序中的一者结束后不插入吹扫的工序而立即进行另一供给工序,实施进行100个循环的该循环的成膜处理。对成膜处理后的基板的表面部利用XPS对组成进行研究,结果如图26所示。根据图26可知,到距离基板的表面大致50nm的深度为止形成聚脲膜,在更深的区域与图25同样。由此,能够认识到,在低介电常数膜的内的孔部埋入有聚脲,在低介电常数膜的表面层叠有聚脲膜。
[评价试验3]
对具有由SiOC形成的多孔质的低介电常数膜的基板,同时供给H6XDI和H6XDA而进行成膜处理。对成膜处理后的基板的表面部利用XPS对组成进行研究,结果如图27所示。根据图27可知,到距离基板的表面大约25nm的深度为止形成聚脲膜,在更深的区域形成有与图25大致相同的区域。由此能够认识到,在低介电常数膜的内的孔部埋入有聚脲,但在低介电常数膜的表面层叠有比评价试验2的情况薄的聚脲膜。
[评价试验4]
评价试验1中,将成膜处理后的基板在氮气气氛下在280度下加热5分钟。针对成膜处理前的基板、成膜处理后的基板研究吸光度,结果如图28所示。图28中,(1)~(3)分别与埋入前、埋入后、加热后相对应。埋入后(2)中,可见与CH键(箭头a)、CO键(箭头b)相对应的峰,但在埋入前(1)及加热后(3)看不到前述峰。
因此证明了:通过所述的成膜处理,聚脲埋入至低介电常数膜内的孔部;另外通过进行聚脲的去除处理,聚脲在低介电常数膜的中完全不残留。
根据以上的结果可知,可以根据原料气体的供给的方法,仅进行利用聚脲的低介电常数膜的孔部的埋入,或在孔部的埋入的基础上形成聚脲膜。
Claims (12)
1.一种半导体装置的制造方法,其在形成于基板上的作为层间绝缘膜的多孔质的低介电常数膜中通过蚀刻形成沟槽和通孔,其特征在于,
所述制造方法包括如下工序:
埋入工序,对所述低介电常数膜供给聚合用的原料,在所述低介电常数膜内的孔部埋入具有脲键的聚合物;
对所述低介电常数膜进行蚀刻,形成通孔的工序;
接着,在所述通孔内埋入包含有机物的保护用的填充物的工序;
然后,对所述低介电常数膜进行蚀刻,形成沟槽的工序;
接着,去除所述填充物的工序;和,
形成所述沟槽后,对所述基板进行加热而将所述聚合物解聚,由此从所述低介电常数膜内的孔部将所述聚合物去除的工序,
在所述孔部埋入所述聚合物的工序在形成所述沟槽之前进行。
2.根据权利要求1所述的半导体装置的制造方法,其特征在于,所述填充物为具有脲键的聚合物。
3.根据权利要求1或2所述的半导体装置的制造方法,其特征在于,包括如下工序:在所述低介电常数膜的表面形成用于对沟槽进行蚀刻的沟槽用的掩模,然后形成用于对通孔进行蚀刻的通孔用的掩模,
在所述孔部埋入所述聚合物的工序在形成所述沟槽用的掩模后、形成所述通孔前进行。
4.根据权利要求1或2所述的半导体装置的制造方法,其特征在于,包括如下工序:在所述低介电常数膜的表面形成用于对沟槽进行蚀刻的沟槽用的掩模,然后形成用于对通孔进行蚀刻的通孔用的掩模,
在所述孔部埋入所述聚合物的工序在形成所述沟槽用的掩模前进行。
5.根据权利要求1~4中任一项所述的半导体装置的制造方法,其特征在于,在所述孔部埋入所述聚合物的工序与埋入所述填充物的工序同时进行。
6.根据权利要求1~5中任一项所述的半导体装置的制造方法,其特征在于,进行去除所述填充物的工序后,进行对位于通孔的底部的蚀刻终止膜进行蚀刻的工序,
从所述低介电常数膜内的孔部将所述聚合物去除的工序在对所述蚀刻终止膜进行蚀刻的工序之后进行。
7.一种半导体装置的制造方法,其在形成于基板上的作为层间绝缘膜的多孔质的低介电常数膜中通过蚀刻形成沟槽和通孔,其特征在于,
所述制造方法包括如下工序:
埋入工序,对所述低介电常数膜供给聚合用的原料,在所述低介电常数膜内的孔部埋入具有脲键的聚合物;
在所述低介电常数膜的表面形成沟槽用的掩模的工序;
使用所述沟槽用的掩模对所述低介电常数膜进行蚀刻,形成沟槽的工序;
接着,在所述沟槽内形成通孔用的掩模的工序;
然后,使用所述通孔用的掩模,对所述沟槽的底部进行蚀刻,形成通孔的工序;
接着,去除所述通孔用的掩模的工序;和,
形成所述沟槽后,对所述基板进行加热而将所述聚合物解聚,由此从所述低介电常数膜内的孔部将所述聚合物去除的工序。
8.根据权利要求7所述的半导体装置的制造方法,其特征在于,所述通孔用的掩模为具有脲键的聚合物。
9.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,所述埋入工序在形成所述沟槽用的掩模的工序之后进行。
10.根据权利要求7或8所述的半导体装置的制造方法,其特征在于,所述埋入工序在形成所述沟槽用的掩模的工序之前进行。
11.根据权利要求1~10中任一项所述的半导体装置的制造方法,其特征在于,埋入所述聚合物的工序为使异氰酸酯的蒸气及胺的蒸气扩散至所述低介电常数膜内,并使异氰酸酯与胺发生聚合反应的工序。
12.根据权利要求1~11中任一项所述的半导体装置的制造方法,其特征在于,将所述聚合物解聚的工序是将基板加热至300℃~400℃而进行的。
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TWI767096B (zh) | 2022-06-11 |
KR20190070859A (ko) | 2019-06-21 |
US20190181039A1 (en) | 2019-06-13 |
US20210118727A1 (en) | 2021-04-22 |
US11495490B2 (en) | 2022-11-08 |
TW201933435A (zh) | 2019-08-16 |
KR102642184B1 (ko) | 2024-03-04 |
JP2019106490A (ja) | 2019-06-27 |
US10910259B2 (en) | 2021-02-02 |
JP6960839B2 (ja) | 2021-11-05 |
CN110034063B (zh) | 2023-10-20 |
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